MAX1303BEUP+ ,4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCELECTRICAL CHARACTERISTICS(V = V = V = V = 5V, V = V = V = V = V = 0V, f = 3.5MHz (50% dutyAVDD1 AV ..
MAX13041ASD+ ,±80V Fault-Protected High-Speed CAN Transceiver with Low-Power Management and Wake-On CANApplications+Denotes a lead(Pb)-free/RoHS-compliant package.+12V Automotive—Clamp 30 Modules/V Deno ..
MAX13042EETD+ ,1.62V to 3.6V Improved High-Speed LLTApplicationsUCSP is a trademark of Maxim Integrated Products, Inc.CMOS Logic-Level Portable POS Sys ..
MAX13047EEVB+ ,Single- and Dual-Channel, Bidirectional Low-Level TranslatorsApplicationsµDFN1mm × 1.5mm2 ®I C and 1-Wire Level TranslationCMOS Logic-Level TranslationMAX13047E ..
MAX1304ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesFeatures● Up to Eight Channels of Simultaneous Sampling The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312 ..
MAX1305 ,8/4/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesApplications• 55mA Analog Supply Current ● SIN/COS Position Encoder• 1.3mA Digital Supply Current ● ..
MAX381ESE ,Precision, Low-Voltage Analog SwitchesBlock Diagrams/Truth TablesTOP VIEWCOM1 1 16 1 1NO1 COM1 16 NO1 COM1 16 NO1 2N.C. 15 IN1 2 15 IN1 2 ..
MAX3831UCB ,+3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock GeneratorApplicationstern and rolls the demux to maintain proper channelSDH/SONET Backplanes ATM Switching N ..
MAX383CPE ,Precision, Low-Voltage Analog SwitchesGeneral Description ________
MAX383CSE ,Precision, Low-Voltage Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX383CSE ,Precision, Low-Voltage Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX383CSE ,Precision, Low-Voltage Analog SwitchesBlock Diagrams/Truth TablesTOP VIEWCOM1 1 16 1 1NO1 COM1 16 NO1 COM1 16 NO1 2N.C. 15 IN1 2 15 IN1 2 ..
MAX1303BEUP+
4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADC
General DescriptionThe MAX1303 multirange, low-power, 16-bit, succes-
sive-approximation, analog-to-digital converter (ADC)
operates from a single +5V supply and achieves
throughput rates up to 115ksps. A separate digital sup-
ply allows digital interfacing with 2.7V to 5.25V systems
using the SPI-/QSPI™-/MICROWIRE®-compatible serial
interface. Partial power-down mode reduces the supply
current to 1.3mA (typ). Full power-down mode reduces
the power-supply current to 1µA (typ).
The MAX1303 provides four (single-ended) or two (true
differential) analog input channels. Each analog input
channel is independently software programmable for
seven single-ended input ranges (0V to +VREF/2,
-VREF/2 to 0V, 0V to +VREF, -VREFto 0V, ±VREF/4,
±VREF/2, and ±VREF), and three differential input
ranges (±VREF/2, ±VREF, ±2 x VREF).
An on-chip +4.096V reference offers a small convenient
ADC solution. The MAX1303 also accepts an external
reference voltage between 3.800V and 4.136V.
The MAX1303 is available in a 20-pin TSSOP package,
and is specified for operation from -40°C to +85°C.
ApplicationsIndustrial Control Systems
Data-Acquisition Systems
Avionics
Robotics
FeaturesSoftware-Programmable Input Range for Each
ChannelSingle-Ended Input Ranges
0V to +VREF/2, -VREF/2 to 0V, 0V to +VREF, -VREF
to 0V, ±VREF/4, ±VREF/2, and ±VREFDifferential Input Ranges
±VREF/2, ±VREF, and ±2 x VREFFour Single-Ended or Two Differential Analog
Inputs±6V Overvoltage Tolerant InputsInternal or External Reference115ksps Maximum Sample RateSingle +5V Power Supply20-Pin TSSOP Package
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
Pin Configuration
Ordering InformationAGND2
AVDD2
AGND3
REFCH1
CH0
AVDD1
AGND1
REFCAP
DVDD
DVDDO
DGNDDIN
CH3
CH2
DGNDO
DOUTSCLK
SSTRB
MAX1303
TSSOPTOP VIEW
+19-3576; Rev 2; 3/12
PARTPIN-PACKAGEC H A N N EL SMAX1303AEUG+20 TSSOP4
MAX1303BEUG+20 TSSOP4
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Note:All devices are specified over the -40°C to +85°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VVDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD1 to AGND1....................................................-0.3V to +6V
AVDD2 to AGND2....................................................-0.3V to +6V
DVDD to DGND........................................................-0.3V to +6V
DVDDO to DGNDO..................................................-0.3V to +6V
DVDD to DVDDO......................................................-0.3V to +6V
DVDD, DVDDO to AVDD1........................................-0.3V to +6V
AVDD1, DVDD, DVDDO to AVDD2..........................-0.3V to +6V
DGND, DGNDO, AGND3, AGND2 to AGND1......-0.3V to +0.3V
CS, SCLK, DIN, DOUT, SSTRB to
DGNDO..........................................-0.3V to (VDVDDO+ 0.3V)
CH0–CH7 to AGND1...................................................-6V to +6V
REF, REFCAP to AGND1....................-0.3V to (VAVDD1+ 0.3V)
Continuous Current (any pin)...........................................±50mA
Continuous Power Dissipation (Multilayer board, TA= +70°C)
20-Pin TSSOP (derate 13.6mW/°C above +70°C).....1084mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Notes 1, 2)Resolution16Bits
MAX1303A±1.0±2Integral NonlinearityINLMAX1303B±1.0±4LSB
Differential NonlinearityDNLNo missing codes-1+2LSB
Transition NoiseExternal or internal reference1LSBRMS
Unipolar0±10Single-ended inputsBipolar-1.0±10
Unipolar0±20Offset Error
Differential inputs
(Note 3)Bipolar-2.0±20
Channel-to-Channel Gain
MatchingUnipolar or bipolar0.025%FSR
Channel-to-Channel Offset Error
MatchingUnipolar or bipolar1.0mV
Unipolar10Offset Temperature CoefficientBipolar5ppm/°C
Unipolar±0.5Gain ErrorBipolar±0.3%FSR
Unipolar1.5Gain Temperature CoefficientBipolar1.0ppm/°C
Unipolar Endpoint OverlapNegative unipolar full scale to positive
unipolar zero-scale020LSB
DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB, fSAMPLE = 130ksps (Notes 1, 2)Differential inputs, FSR = 2 x VREF90
Single-ended inputs, FSR = VREF88
Single-ended inputs, FSR = VREF/285Signal-to-Noise Plus DistortionSINAD
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VVDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential inputs, FSR = 2 x VREF90
Single-ended inputs, FSR = VREF88
Single-ended inputs, FSR = VREF/285Signal-to-Noise RatioSNR
Single-ended inputs, FSR = VREF/482
Total Harmonic Distortion
(Up to the 5th Harmonic)THD-98dB
Spurious-Free Dynamic RangeSFDR9299dB
Aperture DelaytADFigure 1915ns
Aperture JittertAJFigure 19100ps
Channel-to-Channel Isolation105dB
CONVERSION RATEExternal clock mode, Figure 1114
External acquisition mode, Figure 284Byte-Wide Throughput RatefSAMPLE
Internal clock mode, Figure 3106
ksps
ANALOG INPUTS (CH0–CH3, AGND1)Small-Signal BandwidthAll input ranges, VIN = 100mVP-P (Note 2)1.5MHz
Full-Power BandwidthAll input ranges, VIN = 4VP-P (Note 2)700kHz
R[2:1] = 001-VREF/4+VREF/4
R[2:1] = 010-VREF/20
R[2:1] = 0110+VREF/2
R[2:1] = 100-VREF/2+VREF/2
R[2:1] = 101-VREF0
R[2:1] = 1100+VREF
Input Voltage Range (Table 6)VCH_
R[2:1] = 111-VREF+VREF
Tr ue- D i ffer enti al Anal og C om m on- od e V ol tag e Rang eVCMDRDIF/SGL = 1 (Note 4)-4.75+5.50V
Common-Mode Rejection RatioCMRRD IF/S G L = 1, i np ut vol tag e r ang e = ± V R E F /475dB
Input CurrentICH_-VREF < VCH_ < +VREF-1500+650µA
Input CapacitanceCCH_5pF
Input ResistanceRCH_6kΩ
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VVDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)Reference Output VoltageVREF4.0564.0964.136V
Reference Temperature
CoefficientTCREF±30ppm/°C
REF shorted to AGND110Reference Short-Circuit CurrentIREFSCREF shorted to AVDD-1mA
Reference Load RegulationIREF = 0 to 0.5mA0.110mV
EXTERNAL REFERENCE (REFCAP = AVDD)Reference Input Voltage RangeVREF3.8004.136V
REFCAP Buffer Disable
ThresholdVRCTH(Note 5)V AV D D 1 0.4
VAVDD1
- 0.1V
VREF = +4.096V, external clock mode,
external acquisition mode, internal clock
mode, or partial power-down mode200Reference Input CurrentIREF
VREF = +4.096V, full power-down mode±0.1±10
External clock mode, external acquisition
mode, internal clock mode, or partial
power-down mode45kΩReference Input ResistanceRREF
Full power-down mode40MΩ
DIGITAL INPUTS (DIN, SCLK, CS)Input High VoltageVIH0.7 x
VD V DD OV
Input Low VoltageVIL0.3 x
VD V DD OV
Input HysteresisVHYST0.2V
Input Leakage CurrentIINVIN = 0 to VDVDDO-10+10µA
Input CapacitanceCIN10pF
DIGITAL OUTPUTS (DOUT, SSTRB)VDVDDO = 4.75V, ISINK = 10mA0.4Output Low VoltageVOLVDVDDO = 2.7V, ISINK = 5mA0.4V
Output High VoltageVOHISOURCE = 0.5mAVDVDDO
- 0.4V
DOUT Tri-State Leakage CurrentIDDOCS = DVDDO-10+10µA
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)Analog Supply VoltageAVDD14.755.25V
Digital Supply VoltageDVDD4.755.25V
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VVDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPreamplifier Supply VoltageAVDD24.755.25V
Digital I/O Supply VoltageDVDDO2.705.25V
Internal reference33.5
AVDD1 Supply CurrentIAVDD1
External clock mode,
external acquisition
mode, or internal
clock modeExternal reference2.53
DVDD Supply CurrentIDVDDExternal clock mode, external acquisition
mode, or internal clock mode0.92mA
AVDD2 Supply CurrentIAVDD2External clock mode, external acquisition
mode, or internal clock mode17.525mA
DVDDO Supply CurrentIDVDDOExternal clock mode, external acquisition
mode, or internal clock mode0.21mA
Partial power-down mode1.3mATotal Supply CurrentFull power-down mode2µA
Power-Supply Rejection RatioPSRRAll analog input ranges±0.5LSB
TIMING CHARACTERISTICS (Figures 14 and 15)External clock mode27262
External acquisition mode22862SCLK PeriodtCP
Internal clock mode10083
External clock mode109
External acquisition mode92SCLK High Pulse Width (Note 6)tCH
Internal clock mode40
External clock mode109
External acquisition mode92SCLK Low Pulse Width (Note 6)tCL
Internal clock mode40
DIN to SCLK SetuptDS40ns
DIN to SCLK HoldtDH0ns
SCLK Fall to DOUT ValidtDO40ns
CS Fall to DOUT EnabletDV40ns
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VVDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCS Rise to DOUT DisabletTR40ns
CS Fall to SCLK Rise SetuptCSS40ns
CS High Minimum Pulse WidthtCSPW40ns
SCLK Fall to CS Rise HoldtCSH0ns
SSTRB Rise to CS Fall Setup(Note 4)40ns
DOUT Rise/Fall TimeCL = 50pF10ns
SSTRB Rise/Fall TimeCL = 50pF10ns
Note 1:Parameter tested at VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V.
Note 2:See definitions in the Parameter Definitionssection at the end of the data sheet.
Note 3:Guaranteed by correlation with single-ended measurements.
Note 4:Not production tested. Guaranteed by design.
Note 5:To ensure external reference operation, VREFCAPmust exceed (VAVDD1- 0.1V). To ensure internal reference operation, VREFCAP
must be below (VAVDD1- 0.4V). Bypassing REFCAP with a 0.1µF or larger capacitor to AGND1 sets VREFCAP≈4.096V. The tran-
sition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold
minimum and maximum values (Figures 16 and 17).
Note 6:The SCLK duty cycle can vary between 40% and 60%, as long as the tCLand tCHtiming requirements are met.
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1303 toc01
VAVDD1 (V)
AVDD1
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGEMAX1303 toc02
VAVDD2 (V)
AVDD2
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1303 toc03
VDVDD (V)
IDVDD
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
Typical Operating Characteristics(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
DIGITAL I/O SUPPLY CURRENT
vs. DIGITAL I/O SUPPLY VOLTAGEMAX1303 toc04
VDVDDO (V)
DVDDO
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1303 toc05
VAVDD1 (V)
IAVDD1
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
ypical Operating Characteristics (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGEMAX1303 toc06
VAVDD2 (V)
IAVDD2
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1303 toc07
VDVDD (V)
IDVDD
(mA)
PARTIAL POWER-DOWN MODE
TA = +85°C
TA = +25°C
TA = -40°C
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
ANALOG SUPPLY CURRENT
vs. CONVERSION RATEMAX1303 toc08
CONVERSION RATE (ksps)
IAVDD1
(mA)
EXTERNAL CLOCK MODE
PARTIAL
POWER-DOWN MODE
FULL
POWER-DOWN MODE
PREAMPLIFIER SUPPLY CURRENT
vs. CONVERSION RATEMAX1303 toc09
IAVDD2
(mA)
CONVERSION RATE (ksps)
fCLK = 7.5MHz (NOTE 6)
EXTERNAL CLOCK MODE
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
ypical Operating Characteristics (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. CONVERSION RATEMAX1303 toc10
IDVDD
(mA)
CONVERSION RATE (ksps)
fCLK = 7.5MHz (NOTE 6)
FULL POWER-DOWN MODE
EXTERNAL CLOCK MODE,
PARTIAL POWER-DOWN MODE
DIGITAL I/O SUPPLY CURRENT
vs. CONVERSION RATEMAX1303 toc11
CONVERSION RATE (ksps)
IDVDDO
(mA)
fCLK = 7.5MHz (NOTE 6)
EXTERNAL CLOCK MODE
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
Note 6:For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.
Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found
by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down
or full power-down modes.
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE INPUT VOLTAGEMAX1303 toc12
EXTERNAL REFERENCE VOLTAGE (V)
EXTERNAL REFERENCE CURRENT (mA)
ALL MODES
GAIN DRIFT
vs. TEMPERATURE
MAX1303 toc13
TEMPERATURE (°C)
GAIN DRIFT (%)
+VREF/2 BIPOLAR
±VREF BIPOLAR RANGE
±VREF/4 BIPOLAR
OFFSET DRIFT
vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET ERROR (mV)
+VREF/4 BIPOLAR RANGE
±VREF BIPOLAR
CHANNEL-TO-CHANNEL ISOLATION
vs. INPUT FREQUENCYMAX1303 toc15
FREQUENCY (kHz)
ISOLATION (dB)
-12010,000
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
CH0 TO CH2
COMMON-MODE REJECTION RATIO
vs. FREQUENCYMAX1303 toc16
FREQUENCY (kHz)
CMRR (dB)
-10010,000
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
2.016,38432,76849,15265,535
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1303 toc17
DIGITAL OUTPUT CODE
INL (LSB)
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
2.016,38432,76849,15265,535
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1303 toc18
DNL (LSB)
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
FFT AT 5kHz
MAX1303 toc19
MAGNITUDE (dB)
fSAMPLE = 115ksps
fIN(SINE WAVE) = 5kHz±VREF BIPOLAR RANGE
SNR, SINAD, ENOB
vs. ANALOG INPUT FREQUENCY
MAX1303 toc20
SNR, SINAD (dB)
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
ENOB
SNR
SINAD
Typical Operating Characteristics (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
SNR, SINAD, ENOB
vs. SAMPLE RATEMAX1303 toc21
SAMPLE RATE (ksps)
SNR, SINAD (dB)
ENOB (BITS)
fIN(SINE WAVE) = 5kHz±VREF BIPOLAR RANGE
ENOB
SNR, SINAD
-SFDR, THD
vs. SAMPLE RATEMAX1303 toc22
SAMPLE RATE (ksps)
-SFDR, THD (dB)
fIN(SINE WAVE) = 5kHz±VREF BIPOLAR RANGE
THD
-SFDR
-SFDR, THD
vs. ANALOG INPUT FREQUENCY
MAX1302 toc23
FREQUENCY (kHz)
-SFDR, THD (dB)
fSAMPLE = 115ksps±VREF BIPOLAR RANGE
THD-SFDR
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
MAX1303 toc24
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT CURRENT (mA)-20-4246
SMALL-SIGNAL BANDWIDTHMAX1303 toc25
ATTENUATION (dB)
-3010,000
ypical Operating Characteristics (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
NOISE HISTOGRAM
(CODE EDGE)MAX1303 toc27
CODE
NUMBER OF HITS
32,771
10,000
15,000
20,000
25,000
30,000
35,000
32,76932,77232,77432,77032,773
65,534 SAMPLES
NOISE HISTOGRAM
(CODE CENTER)MAX11303 toc28
CODE
NUMBER OF HITS
32,769
10,000
15,000
20,000
25,000
30,000
35,000
40,000
32,77032,76832,77232,77132,77332,767
65,534 SAMPLES
REFERENCE VOLTAGE vs. TIMEMAX1303 toc29
1V/div
4ms/div
FULL-POWER BANDWIDTHMAX1303 toc26
FREQUENCY (kHz)
ATTENUATION (dB)
-6010,000
Typical Operating Characteristics (continued)(VAVDD1= VAVDD2= VDVDD= VDVDDO= 5V, VAGND1= VDGND= VDGNDO= VAGND2= VAGND3= 0V, fCLK= 3.5MHz (50% duty
cycle), external clock mode, VREF= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT= 50pF, CSSTRB= 50pF; unless otherwise noted.)
MAX1303
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
Pin Description
PINNAMEFUNCTIONAGND1Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.AVDD1Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to
AGND1 with a 0.1µF capacitor.CH0Analog Input Channel 0CH1Analog Input Channel 1CH2Analog Input Channel 2CH3Analog Input Channel 3CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising edge
of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high, activity
on SCLK and DIN is ignored and DOUT is high impedance.
8DINSerial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high,
transitions on DIN are ignored.SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is
ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB
does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.SCLKSerial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS is
high, transitions on SCLK are ignored.DOUTSerial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition. When
CS is high, DOUT is high impedance.DGNDODigital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.DGNDDigital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.DVDDODigital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass
DVDDO to DGNDO with a 0.1µF capacitor.DVDDDigital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass DVDD
to DGND with a 0.1µF capacitor.REFCAPBandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For internal
reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1 (VREFCAP ≈ 4.096V).REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external
reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a
1µF capacitor to AGND1 sets VREF = 4.096V ±1%.AGND3Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.AVDD2Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to
AGND2 with a 0.1µF capacitor.AGND2Analog Ground 2. This ground carries approximately five times more current than AGND1. DGND,
DGNDO, AGND3, AGND2, and AGND1 must be connected together.
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADC
Detailed DescriptionThe MAX1303 multirange, low-power, 16-bit successive-
approximation ADC operates from a single +5V supply and
has a separate digital supply allowing digital interface with
2.7V to 5.25V systems. This 16-bit ADC has internal track-
and-hold (T/H) circuitry that supports single-ended and
fully differential inputs. For single-ended conversions, the
valid analog input voltage range spans from -VREFbelow
ground to +VREFabove ground. The maximum allowable
differential input voltage spans from -2 x VREFto +2 x
VREF. Data can be converted in a variety of software-pro-
grammable channel and data-acquisition configurations.
Microprocessor (µP) control is made easy through an
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The MAX1303 has four single-ended analog input chan-
nels or two differential channels. Each analog input chan-
nel is independently software programmable for seven
single-ended input ranges (0V to +VREF/2, -VREF/2 to 0V,
0V to +VREF, -VREFto 0V, ±VREF/4, ±VREF/2, and ±VREF)
and three differential input ranges (±VREF/2, ±VREF, and
±2 x VREF). Additionally, all analog input channels are fault
tolerant to ±6V. A fault condition on an idle channel does
not affect the conversion result of other channels.
Power SuppliesTo maintain a low-noise environment, the MAX1303 pro-
vides separate power supplies for each section of cir-
cuitry. Table 1 shows the four separate power supplies.
Achieve optimal performance using separate AVDD1,
AVDD2, DVDD, and DVDDO supplies. Alternatively, con-
nect AVDD1, AVDD2, and DVDD together as close to the
device as possible for a convenient power connection.
Connect AGND1, AGND2, AGND3, DGND, and DGNDO
together as close as possible to the device. Bypass
each supply to the corresponding ground using a 0.1µF
capacitor (Table 1). If significant low-frequency noise is
present, add a 10µF capacitor in parallel with the 0.1µF
bypass capacitor.
Converter OperationThe MAX1303 ADC features a fully differential, succes-
sive-approximation register (SAR) conversion tech-
nique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended
and differential configurations are supported with pro-
grammable unipolar and bipolar signal ranges.
Table 1. MAX1303 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)CIRCUIT SECTIONBYPASSINGDVDDO/DGNDO2.7 to 5.250.2Digital I/O0.1µF to DGNDO
AVDD2/AGND24.75 to 5.2517.5Analog Circuitry0.1µF to AGND2
AVDD1/AGND14.75 to 5.253.0Analog Circuitry0.1µF to AGND1
DVDD/DGND4.75 to 5.250.9Digital Control Logic and
Memory0.1µF to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBERNAMEDESCRIPTIONSTARTStart Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).DIF/SGL
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 6.
MAX1303
Track-and-Hold CircuitryThe MAX1303 features a switched-capacitor T/H archi-
tecture that allows the analog input signal to be stored as
charge on sampling capacitors. See Figures 1, 2, and 3
for T/H timing and the sampling instants for each operat-
ing mode. The MAX1303 analog input circuitry buffers
the input signal from the sampling capacitors, resulting
in a constant analog input impedance with varying input
voltage (Figure 4).
Analog Input CircuitrySelect differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6kΩinput resistance (Figure 5).
Figure 5shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-mode
voltage:
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 4.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according toTables3and5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±VREFdif-
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±VREFrange
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.RVRVSJCM . =+⎜⎞⎟×+++⎜⎞⎟⎛⎜⎞⎟×1237511
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADCSCLK2345678911121314151617181920212223242526272829303132
DINSC2C1C00000
ANALOG INPUT
TRACK AND HOLD*
DOUTB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0
BYTE 1BYTE 2BYTE 3BYTE 4
SSTRB
HOLDTRACKHOLD
HIGH
IMPEDANCE
tACQ
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE ≈ fSCLK/32
SAMPLING INSTANT
Figure 1. External Clock-Mode Conversion (Mode 0)
4-Channel, ±VREFMultirange Inputs,
Serial 16-Bit ADCSCLK2345678911121314151617181920212223242526272829303132
DINSC2C1C00000
ANALOG INPUT
TRACK AND HOLD*HOLD
DOUTB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0
BYTE 1BYTE 2BYTE 3BYTE 4
SSTRB
INTCLK**23151617
TRACKHOLD
HIGH IMPEDANCE
tACQ
100ns to 400ns
fINTCLK ≈ 4.5MHz
fSAMPLE ≈ fSCLK/32 + fINTCLK/17
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
Figure 2. External Acquisition-Mode Conversion (Mode 1)
