MAX1301BEUP+ ,8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCsFeatures● Software-Programmable Input Range for Each ChannelThe MAX1300/MAX1301 multirange, low-pow ..
MAX13020ASA+T ,±60V Fault-Protected LIN TransceiversApplications MAX13020ASA+ — 8 SOMAX13021ASA+ Yes 8 SO+12V/+42V AutomotiveMAX13021ASA/V+ Yes 8 SO+24 ..
MAX13032EETE+ ,6-Channel High-Speed Logic-Level TranslatorsELECTRICAL CHARACTERISTICS(V = +2.2V to +3.6V, V = +1.62V to +3.2V, EN = V , T = -40°C to +85°C, un ..
MAX13032EETE+T ,6-Channel High-Speed Logic-Level TranslatorsApplicationsTypical Operating Circuits continued at end of data sheet.SD Card Level TranslationMini ..
MAX13036ATI+ ,Contact Monitor and Level ShifterFeaturesThe MAX13036 contact monitor and level shifter monitors ● +6V to +26V Operating Voltage Ran ..
MAX1303BEUP , 8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
MAX3814CHJ+T ,DVI/HDMI TMDS FR-4 and Cable Equalizer/DriverFeaturesThe MAX3814 TMDS™ EQ/driver IC compensates for ♦ Equalizes FR-4 Board Microstrip and Cable ..
MAX3815CCM+TD ,TMDS Digital Video Equalizer for DVI/HDMI CablesELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +70°C. Typical Values are at V = +3.3V, e ..
MAX3816ACUE+ ,I²C 2-Wire Extender for DDC in DVI, HDMI, and VGA InterfacesApplicationsFront-Projector DVI/HDMI InputsPART TEMP RANGE PIN-PACKAGE High-Definition Televisions, ..
MAX381CPE ,Precision, Low-Voltage Analog SwitchesMAX381/MAX383/MAX38519-0300; Rev 0; 9/94Precision, Low-Voltage Analog Switches_______________
MAX381CSE ,Precision, Low-Voltage Analog SwitchesApplicationsMAX381ESE -40°C to +85°C 16 Narrow SOSample-and-Hold Circuits Military RadiosMAX381EJE ..
MAX381EJE ,Precision, Low-Voltage Analog SwitchesMAX381/MAX383/MAX38519-0300; Rev 0; 9/94Precision, Low-Voltage Analog Switches_______________
MAX1301BEUP+
8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs
General DescriptionThe MAX1300/MAX1301 multirange, low-power, 16-bit,
successive-approximation, analog-to-digital converters
(ADCs) operate from a single +5V supply and achieve
throughput rates up to 115ksps. A separate digital sup-
ply allows digital interfacing with 2.7V to 5.25V systems
using the SPI-/QSPI™-/MICROWIRE®-compatible serial
interface. Partial power-down mode reduces the supply
current to 1.3mA (typ). Full power-down mode reduces
the power-supply current to 1µA (typ).
The MAX1300 provides eight (single-ended) or four (true
differential) analog input channels. The MAX1301 pro-
vides four (single-ended) or two (true differential) analog
input channels. Each analog input channel is indepen-
dently software programmable for seven single-ended
input ranges [0 to (3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to 3
x VREF, -3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3
x VREF] and three differential input ranges [(±3 x VREF)/2,
±3 x VREF, ±6 x VREF].
An on-chip +4.096V reference offers a small convenient
ADC solution. The MAX1300/MAX1301 also accept an
external reference voltage between 3.800V and 4.136V.
The MAX1300 is available in a 24-pin TSSOP package
and the MAX1301 is available in a 20-pin TSSOP pack-
age. Each device is specified for operation from -40°C to
+85°C.
Applications●Industrial Control Systems●Data-Acquisition Systems●Avionics●Robotics
Features●Software-Programmable Input Range for Each Channel●Single-Ended Input Ranges (VREF = 4.096V) 0 to (3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to 3 x VREF, -3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3 x VREF●Differential Input Ranges (±3 x VREF)/2, ±3 x VREF, ±6 x VREF●Eight Single-Ended or Four Differential Analog Inputs
(MAX1300)●Four Single-Ended or Two Differential Analog Inputs
(MAX1301)●±16.5V Overvoltage Tolerant Inputs●Internal or External Reference●115ksps Maximum Sample Rate●Single +5V Power Supply●20-/24-Pin TSSOP Package
Pin Configurations continued at end of data sheet.+Denotes lead(Pb)-free/RoHS-compliant package.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
PARTTEMP RANGEPIN-
PACKAGECHANNELS
MAX1300AEUG+-40°C to +85°C24 TSSOP8
MAX1300BEUG+-40°C to +85°C24 TSSOP8
MAX1301AEUP+-40°C to +85°C20 TSSOP4
MAX1301BEUP+-40°C to +85°C20 TSSOP4
AGND1
AGND2
AVDD2
AGND3CH2
CH1
CH0
AVDD1
TOP VIEW
REF
REFCAP
DVDD
DVDD0CH6
CH5
CH4
CH3
DGND
DGNDO
DOUT
SCLKSSTRB
DIN
CH7
TSSOP
MAX1300
MAX1300/MAX13018- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
Ordering Information
Pin Conigurations
EVALUATION KIT AVAILABLE
AVDD1 to AGND1 ...................................................-0.3V to +6V
AVDD2 to AGND2 ...................................................-0.3V to +6V
DVDD to DGND .......................................................-0.3V to +6V
DVDDO to DGNDO .................................................-0.3V to +6V
DVDD to DVDDO ....................................................-0.3V to +6V
DVDD, DVDDO to AVDD1.......................................-0.3V to +6V
AVDD1, DVDD, DVDDO to AVDD2 .........................-0.3V to +6V
DGND, DGNDO, AGND3, AGND2 to AGND1 .....-0.3V to +0.3V
CS, SCLK, DIN, DOUT, SSTRB to
DGNDO .........................................-0.3V to (VDVDDO + 0.3V)
CH0–CH7 to AGND1 ........................................-16.5V to +16.5V
REF, REFCAP to AGND1 ...................-0.3V to (VAVDD1 + 0.3V)
Continuous Current (any pin) ...........................................±50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 11mW/°C above +70°C) .........879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) ......976mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Notes 1, 2)Resolution16Bits
Integral NonlinearityINLMAX130_A±1.0±2LSBMAX130_B±1.0±4
Differential NonlinearityDNLNo missing codes-1+2LSB
Transition NoiseExternal or internal reference1LSBRMS
Offset ErrorSingle-ended inputsUnipolar0±20Bipolar-1.0±12
Differential inputs (Note 3)Bipolar-2.0±20
Channel-to-Channel Gain
MatchingUnipolar or bipolar0.025%FSR
Channel-to-Channel Offset Error
MatchingUnipolar or bipolar1.0mV
Offset Temperature Coeficient
Unipolar3
µV/°CBipolar1
Fully differential2
Gain Error
Unipolar±0.5
%FSRBipolar±0.8
Fully differential±1
Gain Temperature Coeficient
Unipolar2
ppm/°CBipolar1
Fully differential2
DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB (Notes 1, 2)Signal-to-Noise Plus DistortionSINAD
Differential inputs, FSR = ±6 x VREF91
Single-ended inputs, FSR = ±3 x VREF89
Single-ended inputs, FSR = (±3 x VREF)/286
Single-ended inputs, FSR = (±3 x VREF)/48083
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSignal-to-Noise RatioSNR
Differential inputs, FSR = ±6 x VREF91Single-ended inputs, FSR = ±3 x VREF89
Single-ended inputs, FSR = (±3 x VREF)/286
Single-ended inputs, FSR = (±3 x VREF)/483
Total Harmonic Distortion
(Up to the 5th Harmonic)THD-97dB
Spurious-Free Dynamic RangeSFDR9299dB
Aperture DelaytADFigure 2115ns
Aperture JittertAJFigure 21100ps
Channel-to-Channel Isolation105dB
CONVERSION RATEByte-Wide Throughput RatefSAMPLE
External clock mode, Figure 2114
kspsExternal acquisition mode, Figure 384
Internal clock mode, Figure 4106
ANALOG INPUTS (CH0–CH3 MAX1301, CH0–CH7 MAX1300, AGND1)Small-Signal BandwidthAll input ranges, VIN = 100mVP-P (Note 2)2MHz
Full-Power BandwidthAll input ranges, VIN = 4VP-P (Note 2)700kHz
Input Voltage Range (Table 6)VCH_
R[2:1] = 001(-3 x VREF)/
(+3 x VREF)/
R[2:1] = 010(-3 x VREF)/ 0
R[2:1] = 0110(+3 x VREF)/
R[2:1] = 100(-3 x VREF)/
(+3 x VREF)/
R[2:1] = 101-3 x VREF0
R[2:1] = 1100+3 x VREF
R[2:1] = 111-3 x VREF+3 x VREF
True-Differential Analog Common-
Mode Voltage RangeVCMDRDIF/SGL = 1 (Note 4)-14+9V
Common-Mode Rejection
RatioCMRRDIF/SGL = 1,
input voltage range = (±3 x VREF)/475dB
Input CurrentICH_-3 x VREF < VCH_ < +3 x VREF-1250+900µA
Input CapacitanceCCH_5pF
Input ResistanceRCH_17kΩ
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)Reference Output VoltageVREF4.0564.0964.136V
Reference Temperature CoeficientTCREF±30ppm/°C
Reference Short-Circuit CurrentIREFSCREF shorted to AGND110mA
REF shorted to AVDD-1
Reference Load RegulationIREF = 0 to 0.5mA0.110mV
EXTERNAL REFERENCE (REFCAP = AVDD)Reference Input Voltage RangeVREF3.8004.136V
REFCAP Buffer Disable
ThresholdVRCTH(Note 5)VAVDD1
- 0.4
VAVDD1
- 0.1V
Reference Input CurrentIREF
VREF = +4.096V, external clock mode,
external acquisition mode, internal clock
mode, or partial power-down mode200
VREF = +4.096V, full power-down mode±0.1±10
Reference Input ResistanceRREF
External clock mode, external acquisition
mode, internal clock mode, or partial
power-down mode 45kΩ
Full power-down mode 40MΩ
DIGITAL INPUTS (DIN, SCLK, CS)Input High VoltageVIH0.7 x
VDVDDOV
Input Low VoltageVIL0.3 x
VDVDDOV
Input HysteresisVHYST0.2V
Input Leakage CurrentIINVIN = 0 to VDVDDO-10+10µA
Input CapacitanceCIN10pF
DIGITAL OUTPUTS (DOUT, SSTRB)Output Low VoltageVOL
VDVDDO = 4.75V, ISINK = 10mA0.4VDVDDO = 2.7V, ISINK = 5mA0.4
Output High VoltageVOHISOURCE = 0.5mAVDVDDO
- 0.4V
DOUT Tri-State Leakage Current IDDOCS = VDVDDO-10+10µA
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO) Analog Supply VoltageAVDD14.755.25V
Digital Supply VoltageDVDD4.755.25V
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Electrical Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPreampliier Supply VoltageAVDD24.755.25V
Digital I/O Supply VoltageDVDDO2.705.25V
AVDD1 Supply CurrentIAVDD1
External clock mode,
external acquisition
mode, or internal
clock mode
Internal reference33.5
External reference2.33
DVDD Supply CurrentIDVDDExternal clock mode, external acquisition
mode, or internal clock mode0.82mA
AVDD2 Supply CurrentIAVDD2External clock mode, external acquisition
mode, or internal clock mode13.520mA
DVDDO Supply CurrentIDVDDOExternal clock mode, external acquisition
mode, or internal clock mode0.011mA
Total Supply CurrentPartial power-down mode 1.3mA
Full power-down mode 0.5µA
Power-Supply Rejection RatioPSRRAll analog input ranges±0.5LSB
TIMING CHARACTERISTICS (Figures 15 and 16)SCLK PeriodtCP
External clock mode0.27262External acquisition mode0.22862
Internal clock mode0.1
SCLK High Pulse Width (Note 6)tCH
External clock mode109External acquisition mode92
Internal clock mode40
SCLK Low Pulse Width (Note 6)tCL
External clock mode109External acquisition mode92
Internal clock mode40
DIN to SCLK SetuptDS40ns
DIN to SCLK HoldtDH0ns
SCLK Fall to DOUT ValidtDO40ns
CS Fall to DOUT EnabletDV40ns
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Electrical Characteristics (continued)
Note 1: Parameter tested at VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V.
Note 2: See definitions in the Parameter Definitions section at the end of the data sheet.
Note 3: Guaranteed by correlation with single-ended measurements.
Note 4: Not production tested. Guaranteed by design.
Note 5: To ensure external reference operation, VREFCAP must exceed (VAVDD1 - 0.1V). To ensure internal reference operation,
VREFCAP must be below (VAVDD1 - 0.4V). Bypassing REFCAP with a 0.1μF or larger capacitor to AGND1 sets VREFCAP ≈
4.096V. The transition point between internal reference mode and external reference mode lies between the REFCAP buffer
disable threshold minimum and maximum values (Figures 17 and 18).
Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met.
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCS Rise to DOUT DisabletTR40ns
CS Fall to SCLK Rise SetuptCSS40ns
CS High Minimum Pulse WidthtCSPW40ns
SCLK Fall to CS Rise HoldtCSH0ns
SSTRB Rise to CS Fall Setup(Note 4)40ns
DOUT Rise/Fall TimeCL = 50pF10ns
SSTRB Rise/Fall TimeCL = 50pF10ns
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGEMAX1300 toc02
VAVDD2 (V)
IAVDD2
(mA)
EXTERNAL CLOCK MODE
AIN1–AIN7 = AGND2
AIN0 = +FS
TA = +85°C
TA = +25°C
TA = -40°C
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1300 toc03
VDVDD (V)
DVDD
(mA)
EXTERNAL CLOCK MODE
DATA RATE = 115ksps
TA = +85°C
TA = +25°C
TA = -40°C
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1300 toc01
VAVDD1 (V)
IAVDD1
(mA)
EXTERNAL CLOCK MODE
TA = +85°C
TA = +25°C
TA = -40°C
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Electrical Characteristics (continued)
Typical Operating Characteristics
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1300 toc05
VAVDD1 (V)
IAVDD1
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1300 toc07
VDVDD (V)
IDVDD
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
DIGITAL I/O SUPPLY CURRENT
vs. DIGITAL I/O SUPPLY VOLTAGEMAX1300 toc04
VDVDDO (V)
IDVDDO
(µA)
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
DATA RATE = 115ksps
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGEMAX1300 toc06
VAVDD2 (V)
IAVDD2
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
AIN1 - AIN7 = AGND2
AIN0 = +FS
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
Note 7: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.
Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found
by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down
or full power-down modes.
ANALOG SUPPLY CURRENT
vs. CONVERSION RATEMAX1300 toc09
CONVERSION RATE (ksps)
IAVDD2
(mA)
CONTINUOUS EXTERNAL CLOCK MODE
DIGITAL I/O SUPPLY CURRENT
vs. CONVERSION RATEMAX1300 toc11
CONVERSION RATE (ksps)
DVDDO
(mA)
CONTINUOUS EXTERNAL CLOCK MODE
ANALOG SUPPLY CURRENT
vs. CONVERSION RATEMAX1300 toc08
CONVERSION RATE (ksps)
IAVDD1
(mA)
CONTINUOUS EXTERNAL CLOCK MODE
DIGITAL SUPPLY CURRENT
vs. CONVERSION RATEMAX1300 toc10
CONVERSION RATE (ksps)
IDVDD
(mA)
CONTINUOUS EXTERNAL CLOCK MODE
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
GAIN DRIFT vs. TEMPERATUREMAX1300 toc13
TEMPERATURE (°C)
GAIN ERROR (%FSR)3510-15
±3 x VREF BIPOLAR RANGE
(±3 x VREF)/4 BIPOLAR RANGE
COMMON-MODE REJECTION RATIO
vs. FREQUENCYMAX1300 toc16
FREQUENCY (kHz)
CMRR (dB)
-10010,000
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
OFFSET DRIFT vs. TEMPERATUREMAX1300 toc14
TEMPERATURE (°C)
OFFSET ERROR (mV)3510-15
±3 x VREF BIPOLAR RANGE
(±3 x VREF)/4 BIPOLAR RANGE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1300 toc17
DIGITAL OUTPUT CODE
INL (LSB)
52,42839,32113,10726,214
-2.065,535
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
FFT AT 5kHzMAX1300 toc19
MAGNITUDE (dB)
fSAMPLE = 115ksps
fIN(SINE WAVE) = 5kHz
±3 x VREF BIPOLAR RANGE
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE INPUT VOLTAGEMAX1300 toc12
EXTERNAL REFERENCE VOLTAGE (V)
EXTERNAL REFERENCE CURRENT (µA)
CHANNEL-TO-CHANNEL ISOLATION
vs. INPUT FREQUENCY
MAX1300 toc15
FREQUENCY (kHz)
ISOLATION (dB)
-12010,000
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
CH0 TO CH2
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1300/01 toc18
DNL (LSB)
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
SNR, SINAD, ENOB vs. SAMPLE RATEMAX1300 toc21
SAMPLE RATE (ksps)
SNR, SINAD (dB)
fIN(SINE WAVE) = 5kHz
±3 x VREF BIPOLAR RANGE
ENOB (BITS)
ENOB
SNR, SINAD
-SFDR, THD
vs. ANALOG INPUT FREQUENCYMAX1300 toc23
FREQUENCY (kHz)
-SFDR, THD (dB)
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
THD
-SFDR
SMALL-SIGNAL BANDWIDTHMAX1300 toc25
ATTENUATION (dB)
SNR, SINAD, ENOB
vs. ANALOG INPUT FREQUENCY
MAX1300 toc20
FREQUENCY (kHz)
SNR, SINAD (dB)
ENOB (BITS)
ENOB
SINAD
SNR
fSAMPLE = 115ksps
±3 x VREF BIPOLAR RANGE
-SFDR, THD vs. SAMPLE RATEMAX1300 toc22
SAMPLE RATE (ksps)
-SFDR, THD (dB)
fIN(SINE WAVE) = 5kHz
±3 x VREF BIPOLAR RANGE
THD
-SFDR
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGEMAX1300 toc24
ANALOG INPUT CURRENT (mA)
ALL MODES
VREF = 4.096V
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
REFERENCE VOLTAGE vs. TIMEMAX1300 toc27
1V/div
4ms/div
NOISE HISTOGRAM
(CODE CENTER)MAX1300 toc29
CODE
NUMBER OF HITS
32,776
5,000
10,000
15,000
20,000
25,000
30,000
35,000
40,000
32,779
65,534 SAMPLES
32,77732,77532,77832,78032,774
FULL-POWER BANDWIDTHMAX1300 toc26
FREQUENCY (kHz)
ATTENUATION (dB)
-4510,000
NOISE HISTOGRAM
(CODE EDGE)MAX1300 toc28
CODE
NUMBER OF HITS
32,787
5,000
10,000
15,000
20,000
25,000
30,000
35,000
32,78532,789
65,534 SAMPLES
32,78632,78832,790
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Typical Operating Characteristics (continued)
PINNAMEFUNCTIONMAX1300MAX13012AVDD1Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass
AVDD1 to AGND1 with a 0.1µF capacitor.3CH0Analog Input Channel 04CH1Analog Input Channel 15CH2Analog Input Channel 26CH3Analog Input Channel 3—CH4Analog Input Channel 4—CH5Analog Input Channel 5—CH6Analog Input Channel 6—CH7Analog Input Channel 77CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the
rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.
When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.8DINSerial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.9SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that
data is ready to be read from the device. When operating in external clock mode, SSTRB is
always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.10SCLKSerial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.11DOUTSerial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.12DGNDODigital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.13DGNDDigital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.14DVDDODigital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage.
Bypass DVDDO to DGNDO with a 0.1µF capacitor.15DVDDDigital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.
Bypass DVDD to DGND with a 0.1µF capacitor.16REFCAP
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD.
For internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1
(VREFCAP ≈ 4.096V).17REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
bypassing REF with a 1µF capacitor to AGND1 sets VREF = 4.096V ±1%.
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Pin Description
Detailed DescriptionThe MAX1300/MAX1301 multirange, low-power, 16-bit
successive-approximation ADCs operate from a single
+5V supply and have a separate digital supply allowing
digital interface with 2.7V to 5.25V systems. These 16-bit
ADCs have internal track-and-hold (T/H) circuitry that sup-
ports single-ended and fully differential inputs. For single-
ended conversions, the valid analog input voltage range
spans from -3 x VREF below ground to +3 x VREF above
ground. The maximum allowable differential input voltage
spans from -6 x VREF to +6 x VREF. Data can be con-
verted in a variety of software-programmable channel and data-acquisition configurations. Microprocessor (μP) con-
The MAX1300 has eight single-ended analog input chan-
nels or four differential channels (see the Block Diagram
at the end of the data sheet). The MAX1301 has four
single-ended analog input channels or two differential
channels. Each analog input channel is independently
software programmable for seven single-ended input
ranges [0 to (+3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to +3 x
VREF, -3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3 x
VREF] and three differential input ranges [(±3 x VREF)/2,
±3 x VREF, ±6 x VREF]. Additionally, all analog input chan-
nels are fault tolerant to ±16.5V. A fault condition on an
idle channel does not affect the conversion result of other
channels.
Figure 1. Typical Application Circuit
PINNAMEFUNCTIONMAX1300MAX130118AGND3Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to
AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. 19AVDD2Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass
AVDD2 to AGND2 with a 0.1µF capacitor.20AGND2Analog Ground 2. This ground carries approximately ive times more current than AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.1AGND1Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
4–20mA
PLC
ACCELERATION
PRESSURE
TEMPERATURE
WHEATESTONE
WHEATESTONE
1µF
0.1µFAGND2DGNDOAGND3DGND
AVDD2DVDDAVDD1
0.1µF0.1µF0.1µF
5.0V5.0V5.0V
MAX1300CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
AGND1
REFCAP
0.1µF
3.3V
MC68HCXX
DVDDO
SCLK
DIN
SSTRB
DOUT
VDD
SCK
I/O
MOSI
I/O
MISO
VSS
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Pin Description (continued)
Power SuppliesTo maintain a low-noise environment, the MAX1300
and MAX1301 provide separate power supplies for
each section of circuitry. Table 1 shows the four sepa-
rate power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD togeth-
er as close to the device as possible for a convenient
power connection. Connect AGND1, AGND2, AGND3,
DGND, and DGNDO together as close to the device
as possible. Bypass each supply to the corresponding ground using a 0.1μF capacitor (Table 1). If significant low-frequency noise is present, add a 10μF capacitor in parallel with the 0.1μF bypass capacitor.
Converter OperationThe MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conversion
technique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended and
differential configurations are supported with program-
mable unipolar and bipolar signal ranges.
Track-and-Hold CircuitryThe MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for each
operating mode. The MAX1300/MAX1301 analog input
circuitry buffers the input signal from the sampling capaci-
tors, resulting in a constant input impedance with varying
input voltage (Figure 5).
Analog Input CircuitrySelect differential or single-ended conversions using the
associated analog input configuration byte (Table 2). The
analog input signal source must be capable of driving the ADC’s 17kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The ana-
log inputs are ±16.5V fault tolerant and are protected by
back-to-back diodes. The summing junction voltage, VSJ,
is a function of the channel’s input common-mode voltage:CMR1V 2.375V 1 VR1 R2R1 R2=×++×++
As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
Table 2. Analog Input Configuration Byte
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)CIRCUIT SECTIONBYPASSINGDVDDO/DGNDO2.7 to 5.250.03Digital I/O0.1µF to DGNDO
AVDD2/AGND24.75 to 5.25135Analog Circuitry 0.1µF to AGND2
AVDD1/AGND14.75 to 5.253.0Analog Circuitry0.1µF to AGND1
DVDD/DGND4.75 to 5.250.8Digital Control Logic and Memory0.1µF to DGND
BIT
NUMBERNAMEDESCRIPTIONSTARTStart Bit. The irst logic 1 after CS goes low deines the beginning of the analog input coniguration byte.C2
Channel-Select Bits. SEL[2:0] select the analog input channel to be conigured (Tables 4 and 5).5C1C0DIF/SGL
Differential or Single-Ended Coniguration Bit. DIF/SGL = 0 conigures the selected analog input channel
for single-ended operation. DIF/SGL = 1 conigures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.R2
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±3 x VREF
differential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±3 x VREF range
(1010 1100). To initiate a conversion for the CH2 and CH3
differential pair, issue the command 1010 0000.
Analog Input BandwidthThe MAX1300/MAX1301 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD and
-SFDR vs. Input Frequency plot in the Typical Operating
Characteristics.
Analog Input Range and Fault ToleranceFigure 7 illustrates the software-selectable single-ended
analog input voltage range that produces a valid digital
output. Each analog input channel can be independently
programmed to one of seven single-ended input ranges
by setting the R[2:0] control bits with DIF/SGL = 0.
Figure 2. External Clock-Mode Conversion (Mode 0)
HIGH
IMPEDANCE
SCLK1234567891011121314151617181920212223242526272829303132
DINSC2C1C00000
ANALOG INPUT
TRACK AND HOLD*
DOUTB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0
BYTE 1BYTE 2BYTE 3BYTE 4
SSTRB
HOLDTRACKHOLD
tACQ
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE fSCLK / 32
SAMPLING INSTANT
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be inde-
pendently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±16.5V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered. Any
voltage beyond FSR, but within the ±16.5V fault tolerant
range, applied to an analog input results in a full-scale
output voltage for that channel.
Clamping diodes with breakdown thresholds in excess of
16.5V protect the MAX1300/MAX1301 analog inputs dur-
ing ESD and other transient events (Figure 6). The clamp-
ing diodes do not conduct during normal device opera-
tion, nor do they limit the current during such transients.
When operating in an environment with the potential for
high-energy voltage and/or current transients, protect the
MAX1300/MAX1301 externally.
Figure 3. External Acquisition-Mode Conversion (Mode 1)
SCLK1234567891011121314151617181920212223242526272829303132
DINSC2C1C00000
ANALOG INPUT
TRACK AND HOLD*HOLD
DOUTB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0
BYTE 1BYTE 2BYTE 3BYTE 4
SSTRB
INTCLK**12314151617
TRACKHOLD
tACQ
100ns to 400ns
fINTCLK 4.5MHz
fSAMPLE fSCLK / 32 + fINTCLK / 17
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
HIGH IMPEDANCE
MAX1300/MAX13018- and 4-Channel, ±3 x V
REF Multirange Inputs,
Serial 16-Bit ADCs
