MAX1296AEEG+ ,420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at REF ..
MAX1296BCEG ,420ksps / +5V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1294/MAX1296 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1296BCEG ,420ksps / +5V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD9 1 24 D10Industrial Control Systems Data LoggingD8 2 23 D11Energy Management Patient ..
MAX1297ACEG ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interfaceapplications or for other circuits with demanding power-24-Pin QSOP (MAX1297)consumption and space ..
MAX1297BCEG ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1295/MAX1297 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1299CEAE+ ,12-Bit Serial-Output Temperature Sensors with 5-Channel ADCApplicationsMAX1299CEAE+ -40°C to +85°C 16 SSOPTemperature/Voltage Supervision of +Denotes a lead(P ..
MAX3801UTG+T ,3.2Gbps Adaptive EqualizerApplicationsTEMP PIN- PACKAGESDH/SONET Transmission EquipmentPARTRANGE PACKAGE CODEMAX3801UGG 0°C t ..
MAX3802UGK ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverApplications ESD Protection on Cable Inputs and OutputsHigh-Speed Links in Communications and Data ..
MAX3802UGK-D ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverApplications● High-Speed Links in Communications and Data Ordering Information Systems● Backplane ..
MAX3802UTK+ ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverElectrical Characteristics(V = 3.14V to 3.46V, T = 0°C to +85°C. Typical values are at V = 3.3V and ..
MAX3802UTK+D ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverElectrical Characteristics(V = 3.14V to 3.46V, T = 0°C to +85°C. Typical values are at V = 3.3V and ..
MAX3803UBP-T ,DC-Coupled / UCSP 3.125Gbps EqualizerApplicationsBackplane InterconnectOrdering InformationRack-to-Rack InterconnectCommon-Mode Voltage ..
MAX1296AEEG+
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1294/MAX1296 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed 12-bit parallel interface. They operate with
a single +5V analog supply.
Power consumption is only 10mW at the maximum sam-
pling rate of 420ksps. Two software-selectable power-
down modes enable the MAX1294/MAX1296 to be shut
down between conversions; accessing the parallel
interface returns them to normal operation. Powering
down between conversions can reduce supply below
10µA at lower sampling rates.
Both devices offer software-configurable analog inputs for
unipolar/bipolar and single-ended/pseudo-differential
operation. In single-ended mode, the MAX1294 has six
input channels and the MAX1296 has two (three input
channels and one input channel, respectively, when in
pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power-consumption and space requirements.
The MAX1294/MAX1296 tri-states INTwhen CSgoes
high. Refer to MAX1266/MAX1268 if tri-stating INTis not
desired.
The MAX1294 is offered in a 28-pin QSOP package, while
the MAX1296 is available in a 24-pin QSOP. For pin-com-
patible +3V, 12-bit versions, see the MAX1295/MAX1297.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouchscreens
Features12-Bit Resolution, ±0.5 LSB LinearitySingle +5V OperationInternal +2.5V ReferenceSoftware-Configurable Analog Input Multiplexer
6-Channel Single-Ended/
3-Channel Pseudo-Differential (MAX1294)
2-Channel Single-Ended/
1-Channel Pseudo-Differential (MAX1296)Software-Configurable Unipolar/Bipolar
Analog InputsLow Current
2.8mA (420ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)Internal 6MHz Full-Power Bandwidth Track/HoldParallel 12-Bit InterfaceSmall Footprint
28-Pin QSOP (MAX1294)
24-Pin QSOP (MAX1296)
MAX1294/MAX1296, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Ordering Information
Pin Configurations
Typical Operating Circuits appear at end of data sheet.
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0–CH5, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW
Operating Temperature Ranges
MAX1294_C_ _/MAX1296_C_ _.........................0°C to +70°C
MAX1294_E_ _/MAX1296_E_ _......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +5V, COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS(VDD= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceINTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1294/6toc01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1294/6toc02
DIGITAL OUTPUT CODE
DNL (LSB)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1294/6 toc03
VDD (V)
IDD
(mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX1294/6 toc04
TEMPERATURE (°C)
IDD
(mA)
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1294/6 toc05
VDD (V)
STANDBY I
STANDBY CURRENT vs. TEMPERATURE
MAX1294/6 toc06
TEMPERATURE (°C)
STANDBY I
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1294/6 toc07
VDD (V)
POWER-DOWN I
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1294/6 toc08
TEMPERATURE (°C)
POWER-DOWN I
Typical Operating Characteristics(VDD= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interfaceypical Operating Characteristics (continued)(VDD= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description (continued)
_______________Detailed Description
Converter OperationThe MAX1294/MAX1296 ADCs use a successive-approx-
imation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal to
a 12-bit digital output. This output format provides easy
interface to standard microprocessors (µPs). Figure 2
shows the simplified internal architecture of the MAX1294/
MAX1296.
Figure 2. Simplified Functional Diagram
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 1. Control-Byte Functional Description
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADCs’ analog com-
parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen-
tial to the effect that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5
LSB (±0.1 LSB for best performance) with respect to
GND during a conversion. To accomplish this, connect
a 0.1µF capacitor from IN- (the selected input) to GND.
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceDuring the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLDas a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(VIN+ - VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/HoldThe MAX1294/MAX1296 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next on ris-
ing edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive input “-”, and the difference of |(IN+) - (IN-)|is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF= 1)
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF= 0)*Channels CH2–CH5 apply to MAX1294 only.
*Channels CH2–CH5 apply to MAX1294 only.
