MAX1297BCEG ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1295/MAX1297 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1299CEAE+ ,12-Bit Serial-Output Temperature Sensors with 5-Channel ADCApplicationsMAX1299CEAE+ -40°C to +85°C 16 SSOPTemperature/Voltage Supervision of +Denotes a lead(P ..
MAX13013EXT+T ,+1.2V to +3.6V, 0.1µA, 100Mbps, Single-/Dual-/Quad-Level TranslatorsApplications +1.8V +3.3V0.1μF 0.1μFCMOS Logic-Level TranslationLow-Voltage ASIC Level Translation V ..
MAX13014EKA+T ,+1.2V to +3.6V, 0.1µA, 100Mbps, Single-/Dual-/Quad-Level TranslatorsELECTRICAL CHARACTERISTICS(V = +1.65V to +3.6V, V = +1.2V to (V - 0.4V), EN = V , EN = open (MAX302 ..
MAX1301BEUP , 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs
MAX1301BEUP+ ,8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCsFeatures● Software-Programmable Input Range for Each ChannelThe MAX1300/MAX1301 multirange, low-pow ..
MAX3802UTK+D ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverElectrical Characteristics(V = 3.14V to 3.46V, T = 0°C to +85°C. Typical values are at V = 3.3V and ..
MAX3803UBP-T ,DC-Coupled / UCSP 3.125Gbps EqualizerApplicationsBackplane InterconnectOrdering InformationRack-to-Rack InterconnectCommon-Mode Voltage ..
MAX3804ETE+ ,12.5Gbps Settable Receive EqualizerFeaturesThe MAX3804 driver with integrated analog equalizer Compensates Up to 30in (0.75m) of 6-mi ..
MAX3812USA ,Multirate SMPTE SD/HD Cable Driver with Selectable Slew RateApplications♦ 0°C to +85°C Operating Temperature RangeSMPTE 292M, SMPTE 344M, SMPTE 259M, andDVB-AS ..
MAX3814CHJ+T ,DVI/HDMI TMDS FR-4 and Cable Equalizer/DriverFeaturesThe MAX3814 TMDS™ EQ/driver IC compensates for ♦ Equalizes FR-4 Board Microstrip and Cable ..
MAX3815CCM+TD ,TMDS Digital Video Equalizer for DVI/HDMI CablesELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +70°C. Typical Values are at V = +3.3V, e ..
MAX1295BCEI-MAX1295BEEI-MAX1297ACEG-MAX1297BCEG
265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1295/MAX1297 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2μs), on-chip clock, +2.5V internal reference, and
high-speed 12-bit parallel interface. They operate with
a single +2.7V to +3.6V analog supply.
Power consumption is only 5.4mW at the maximum
sampling rate of 265ksps. Two software-selectable
power-down modes enable the MAX1295/MAX1297 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can reduce sup-
ply current below 10μA at lower sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1295 has
six input channels and the MAX1297 has two (three
input channels and one input channel, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power combined
with ease of use and small package size make these con-
verters ideal for battery-powered and data-acquisition
applications or for other circuits with demanding power-
consumption and space requirements. The MAX1295 is
offered in a 28-pin QSOP package, while the MAX1297
comes in a 24-pin QSOP. For pin-compatible +5V, 12-bit
versions, refer to the MAX1294/MAX1296 data sheet.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouchscreens
Features12-Bit Resolution, ±0.5LSB Linearity+3V Single-Supply OperationInternal +2.5V ReferenceSoftware-Configurable Analog Input Multiplexer
6-Channel Single-Ended/
3-Channel Pseudo-Differential (MAX1295)
2-Channel Single-Ended/
1-Channel Pseudo-Differential (MAX1297)Software-Configurable Unipolar/Bipolar
Analog InputsLow Current
1.8mA (265ksps)
1.0mA (100ksps)
400μA (10ksps)
2μA (shutdown)Internal 3MHz Full-Power Bandwidth Track/HoldParallel 12-Bit InterfaceSmall Footprint
28-Pin QSOP (MAX1295)
24-Pin QSOP (MAX1297)
MAX1295/MAX1297, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Ordering Information
Pin Configurations
Typical Operating Circuits appear at end of data sheet.
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7μF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0–CH5, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW
Operating Temperature Ranges
MAX1295_C__/MAX1297_C__........................0°C to +70°C
MAX1295_E__/MAX1297_E__......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7μF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +3V, COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7μF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceDIFFERENTIAL NONLINEARITY vs.
DIGITAL OUTPUT CODE
MAX1295/7-02
DIGITAL OUTPUT CODE
DNL (LSB)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1295/7 toc03
VDD (V)
IDD
(mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX1295/7 toc04
TEMPERATURE (°C)
IDD
(mA)
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1295/7 toc05
VDD (V)
STANDBY I
STANDBY CURRENT vs. TEMPERATURE
MAX1295/7 toc06
TEMPERATURE (°C)
STANDBY I
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1295/7 toc07
VDD (V)
POWER-DOWN I
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1295/7 toc08
TEMPERATURE (°C)
POWER-DOWN I
Typical Operating Characteristics
(VDD= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interfaceypical Operating Characteristics (continued)(VDD= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description (continued)
_______________Detailed Description
Converter OperationThe MAX1295/MAX1297 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (μPs). Figure
2 shows the simplified internal architecture of the
MAX1295/MAX1297.
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1295
(Figure 3a) and to CH0–CH1 for the MAX1297 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 1. Control-Byte Functional Descriptionthe analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5LSB
(±0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1μF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on CHOLDas a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interfaceder of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 12pF (VIN+- VIN-) charge from
CHOLDto the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current
to 4mA.
Track/HoldThe MAX1295/MAX1297 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that in internal clock
mode this is approximately 1μs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive input “-”, and the difference of |(IN+) - (IN-)|is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ= 9 (RS+ RIN) CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩhave no significant impact on the MAX1295/
MAX1297’s AC performance.
Higher source impedances can be used if a 0.01μF
capacitor is connected to the individual analog inputs.
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF= 1)
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF= 0)*Channels CH2–CH5 apply to MAX1295 only.
*Channels CH2–CH5 apply to MAX1295 only.
