MAX1290BCEI+T ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1290/MAX1292 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5 LSB Linearitydigi ..
MAX1290BEEI ,400ksps / +5V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interfaceapplications or for other circuits with demand-ing power consumption and space requirements. Pin Co ..
MAX1290BEEI+ ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at ..
MAX1291BCEI ,250ksps / +3V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +2.7V to +3.6V, COM = GND, REFADJ = V , V = +2.5V, 4.7μF capacit ..
MAX1292BCEG ,400ksps / +5V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 20 GNDIndustrial Control Systems Data LoggingMAX1292D3/D11 6 19 COMEnergy Manageme ..
MAX1293ACEG ,250ksps / +3V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 24 GNDMAX1291Industrial Control Systems Data LoggingD3/D11 6 23 COMEnergy Manageme ..
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersMAX378/MAX37919-1902; Rev 1; 8/94High-Voltage, Fault-ProtectedAnalog Multiplexers_______________
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersApplicationsMAX378MJE -55°C to +125°C 16 CERDIPData Acquisition SystemsMAX378MLP -55°C to +125°C 20 ..
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersApplicationsMAX378MJE -55°C to +125°C 16 CERDIPData Acquisition SystemsMAX378MLP -55°C to +125°C 20 ..
MAX379CPE+ ,8-Channel, High-Voltage, Fault-Protected MultiplexersFeatures' Fault Input Voltage ±75V with Power Supplies OffThe MAX378 8-channel single-ended (1-of-8 ..
MAX379CWG ,High-Voltage, Fault-Protected Analog MultiplexersGeneral Description ________
MAX379CWG+ ,8-Channel, High-Voltage, Fault-Protected MultiplexersApplicationsMAX378MJE -55°C to +125°C 16 CERDIPData Acquisition SystemsMAX378MLP -55°C to +125°C 20 ..
MAX1290AEEI+-MAX1290BCEI+T-MAX1290BEEI+
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1290/MAX1292 low-power,12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and
a high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
VLOGICpin that allows them to interface directly with a
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (VDD= VLOGIC) at a
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1290/MAX1292 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1290 has
eight input channels and the MAX1292 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1290/MAX1292 tri-states INTwhen CSgoes
high. Refer to MAX1262/MAX1264 if tri-stating INTis not
desired.
The MAX1290 is available in a 28-pin QSOP package,
while the MAX1292 comes in a 24-pin QSOP. For pin-
compatible +3V, 12-bit versions, refer to the MAX1291/
MAX1293 data sheet.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouchscreens
Features12-Bit Resolution, ±0.5 LSB Linearity+5V Single-Supply OperationUser-Adjustable Logic Level (+2.7V to +5.5V)Internal +2.5V ReferenceSoftware-Configurable Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1290)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1292)Software-Configurable Unipolar/Bipolar Analog
InputsLow Current:2.5mA (400ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)Internal 6MHz Full-Power Bandwidth Track/HoldByte-Wide Parallel (8 + 4) InterfaceSmall Footprint:28-Pin QSOP (MAX1290)
24-Pin QSOP (MAX1292)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface19-1531; Rev 3; 12/02
PART
MAX1290ACEI0°C to +70°C
TEMP RANGEPIN-PACKAGE28 QSOP
Ordering Information
Pin Configurations±0.5
INL
(LSB)MAX1290BCEI0°C to +70°C±128 QSOP
MAX1290BEEI
MAX1290AEEI
-40°C to +85°C±1
-40°C to +85°C±0.528 QSOP
28 QSOP
Ordering Information continued at end of data sheet.Typical Operating Circuits appear at end of data sheet.VLOGIC
VDD
REF
REFADJ
GND
COM
CH0
CH1
CH2
CH3
CLKWR
INT
D0/D8
D1/D9
D2/D10
D3/D11
HBEN
QSOPMAX1292
TOP VIEW
Pin Configurations continued at end of data sheet.
EVALUATION KIT
AVAILABLE
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
External acquisition or external clock mode
Internal acquisition/internal clock mode
MAX129_A
External acquisition/internal clock mode
External clock mode
-3dB rolloff
SINAD > 68dB
fIN= 175kHz, VIN= 2.5VP-P(Note 4)
fIN1= 49kHz, fIN2= 52kHz
MAX129_B
No missing codes over temperature
CONDITIONS25Aperture Delay400tACQT/H Acquisition Time
tCONVConversion Time (Note 5)
MHz6Full-Power Bandwidth
kHz350Full-Linear Bandwidth-78Channel-to-Channel Crosstalk76IMDIntermodulation Distortion80SFDRSpurious-Free Dynamic Range-80Total Harmonic Distortion
(including 5th-order harmonic)THD
±0.5INLRelative Accuracy (Note 2)
Bits12RESResolution6770SINADSignal-to-Noise Plus Distortion
LSB±0.2Channel-to-Channel Offset
Matching
ppm/°C±2Gain Temperature Coefficient
LSB±1
LSB±1DNLDifferential Nonlinearity
LSB±4Offset Error
LSB±4Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETERInternal acquisition/internal clock mode
External acquisition or external clock mode
<200ps<50Aperture Jitter
MHz0.17.6fCLKExternal Clock Frequency3070Duty Cycle
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (fIN(sine wave)= 50kHz, VIN= 2.5VP-P, 400ksps, external fCLK= 7.6MHz, bipolar input mode)
CONVERSION RATEVDDto GND..............................................................-0.3V to +6V
VLOGICto GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT)
to GND...........................................-0.3V to (VLOGIC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C).........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C).......667mW
Operating Temperature Ranges
MAX1290_C_ _/MAX1292_C_ _.......................0°C to +70°C
MAX1290_E_ _/MAX1292_E_ _.....................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER0 to 0.5mA output load
To power down the internal reference
For small adjustments
On/off-leakage current, VIN= 0 or VDD
Unipolar, VCOM= 01.0VDD +
50mVVREFREF Input Voltage Range4.710Capacitive Bypass at REF0.011Capacitive Bypass at REFADJ
mV/mA0.2Load Regulation (Note 7)VDD- 1REFADJ High Threshold±100REFADJ Input Range
±20ppm/°CTCREFREF Temperature Coefficient15REF Short-Circuit Current2.492.52.51REF Output Voltage12CINInput Capacitance±0.01±1Multiplexer Leakage Current
Analog Input Voltage Range
Single Ended and Differential
(Note 6)
0VREF
VIN= VDD
ISOURCE= 1mA
ISINK= 1.6mA
VIN= 0 or VDD
VLOGIC= 4.5V±0.1±1ILEAKAGEThree-State Leakage CurrentVLOGIC- 0.5VOHOutput Voltage High 0.4VOLOutput Voltage Low 15CINInput Capacitance±0.1±1IINInput Leakage Current200VHYSInput Hysteresis0.8VILInput Voltage Low 4.0= VDDpF15COUTThree-State Output Capacitance
Bipolar, VCOM= VREF / 2-VREF/2+VREF/2
VLOGIC= 2.7V2.0VIHInput Voltage High
VREF= 2.5V, fSAMPLE= 400ksps200300
Shutdown modeµA2IREFShutdown REF Input Current
ANALOG INPUTS
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REF
DIGITAL INPUTS AND OUTPUTS
Operating mode,
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERStandby mode
Operating mode,
fSAMPLE= 400ksps
1.01.2mA2.52.9
IDDPositive Supply Current4.55.5VDDAnalog Supply Voltage
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
VLOGICCurrentILOGICCL= 20pF210µA
Power-Supply RejectionPSRVDD= +5V ±10%, full-scale input±0.3±0.9mV
fSAMPLE= 400ksps
Nonconverting2.7VDD+
0.3VLOGICDigital Supply Voltageto CLK Fall Setup TimetCWS40nsCLK Pulse Width HighCLK Period
tCH40
tCP132
CLK Pulse Width LowtCL40ns
Data Valid to WRRise TimetDS40nsRise to Data Valid Hold TimetDH0ns
CLK Fall to WRHold TimetCWH40nsto CLK or WRSetup TimetCSWS60ns
CLK or WRto CSHold TimetCSWH0nsPulse WidthtCS100nsPulse Width (Note 8)tWR60ns
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONSShutdown mode210
POWER REQUIREMENTS
External reference
Internal reference
External reference
Internal reference
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +5V, COM = GND, = 0, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
3kΩ
3kΩ
DOUT
DOUT
VLOGIC
a) HIGH-Z TO VOH AND VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOLCLOAD
20pFCLOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times
tTR1040nsCLOAD= 20pF, Figure 1RDRise to Output DisableFall to Output Data ValidtDO1050nsFall to INTHigh DelaytINT150nsFall to Output Data ValidtDO2100ns
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
tTC1060nsCLOAD= 20pF, Figure 1
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONSRise to Output Disable
HBEN Rise to Output Data ValidtDO11050nsCLOAD= 20pF, Figure 1
HBEN Fall to Output Data ValidtDO11080nsCLOAD= 20pF, Figure 1
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics(VDD= VLOGIC= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1290/2 toc01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1290/2 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
0.110k1011001k100k1000k
SUPPLY CURRENT
vs. SAMPLE FREQUENCYMAX1290/2 toc03
fSAMPLE (Hz)
IDD
10k
WITH INTERNAL
REFERENCE
WITH EXTERNAL
REFERENCE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1290/2 toc04
VDD (V)
IDD
(mA)
RL = ∞
CODE = 101010100000
SUPPLY CURRENT vs. TEMPERATURE
MAX1290/2 toc05
TEMPERATURE (°C)
IDD
(mA)
RL = ∞
CODE = 101010100000
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1290/2 toc06
VDD (V)
STANDBY I
STANDBY CURRENT vs. TEMPERATURE
MAX1290/2 toc07
TEMPERATURE (°C)
STANDBY I
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1290/2 toc08
VDD (V)
POWER-DOWN I
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1290/2 toc09
TEMPERATURE (°C)
POWER-DOWN I
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceINTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1290/2 toc10
VDD (V)
REF
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1290/2 toc 11
TEMPERATURE (°C)
REF
(V)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1290/2 toc12
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1290/2 toc13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1290/2 toc14
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1290/2 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1290/2 toc16
VDD (V)
ILOGIC
4.505.004.755.255.50
ypical Operating Characteristics (continued)(VDD= VLOGIC= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
MAX1290/2 toc 17
TEMPERATURE (°C)
ILOGIC
2040020060080010001200
FFT PLOTMAX1290/2 toc18
FREQUENCY (kHz)
AMPLITUDE (dB)
VDD = 5V
fIN = 50kHz
fSAMPLE = 400ksps
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
NAMEFUNCTIONHBEN
High Byte Enable. Used to multiplex the 12-bit conversion result.
1: Four MSBs are multiplexed on the data bus.
0: Eight LSBs are available on the data bus.
PIND7Three-State Digital I/O Line (D7)D6Three-State Digital I/O Line (D6)D5Three-State Digital I/O Line (D5)D4Three-State Digital I/O Line (D4)D3/D11Three-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1)D2/D10Three-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1)D1/D9Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)D0/D8Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)INTINTgoes low when the conversion is complete and the output data is ready.RDActive-Low Read Select. If CSis low, a falling edge on RDenables the read operation on the
data bus.WR
Active-Low Write Select. When CSis low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CSis
low in external acquisition mode, the first rising edge on WRends acquisition and starts a
conversion.CLKClock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible
clock. In internal clock mode, connect this pin to either VDDor GND.CSActive-Low Chip Select. When CSis high, digital outputs (INT, D7–D0) are high impedance.CH7Analog Input Channel 7CH6Analog Input Channel 6CH5Analog Input Channel 5CH4Analog Input Channel 4CH3Analog Input Channel 3CH2Analog Input Channel 2CH1Analog Input Channel 1CH0Analog Input Channel 0COMGround Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.GNDAnalog and Digital GroundREFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF
capacitor. When using an external reference, connect REFADJ to VDDto disable the internal
bandgap reference.REFBandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND
when using the internal reference.VDDAnalog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.VLOGICDigital Power Supply. VLOGICpowers the digital outputs of the data converter and can range
from +2.7V to VDD+ 300mV.
MAX1290MAX1292
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________Detailed Description
Converter OperationThe MAX1290/MAX1292 ADCs use a successive-
approximation (SAR) conversion technique and an input
track-and-hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4) out-
put format provides an easy interface to standard micro-
processors (µPs). Figure 2 shows the simplified internal
architecture of the MAX1290/MAX1292.
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuits in
Figures 3a and 3b. In single-ended mode, IN+ is inter-
nally switched to channels CH0–CH7 for the MAX1290
(Figure 3a) and to CH0–CH3 for the MAX1292 (Figure
3b), while IN- is switched to COM (Table 3). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 4).
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLDas a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
17kΩ888
SUCCESSIVE-
APPROXIMATION
REGISTER
MUX
( ) ARE FOR MAX1290 ONLY.
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
LATCHES
REFREFADJ
1.22V
REFERENCE
D0–D7
8-BIT DATA BUS
(CH5)
(CH4)
CH3
CH2
CH1
CH0
COM
CLK
INT
VDD
HBEN
GND
VLOGIC
MAX1290
MAX1292
AV =
COMP
(CH7)
(CH6)
Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1290/MAX1292
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/HoldThe MAX1290/MAX1292 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part enters
its hold mode on the fourth falling edge of clock after
writing the control byte. Note that, in internal clock mode,
this is approximately 1µs after writing the control byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive input “-” and the difference of |(IN+) - (IN-)|is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ= 9 (RS + RIN)CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩhave no significant impact on the MAX1290/
MAX1292’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Along with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX1290/MAX1292 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth that make it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing high-frequency signals into the frequen-
cy band of interest, anti-alias filtering is recommended.
Starting a ConversionInitiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1290/MAX1292 for either unipolar or bipolar opera-
tion. A write pulse (WR+ CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceCH0
CH2
CH1
CH3
CH4
CH6
CH7
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3a. MAX1290 Simplified Input Structure
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3b. MAX1292 Simplified Input Structure
