MAX1290ACEI ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 20 GNDIndustrial Control Systems Data LoggingMAX1292D3/D11 6 19 COMEnergy Manageme ..
MAX1290AEEI ,400ksps / +5V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1290/MAX1292 low-power, 12-bit analog-to- 12-Bit Resolution, ±0.5 LSB Linearitydigi ..
MAX1290AEEI+ ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceMAX1290/MAX129219-1531; Rev 3; 12/02400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference an ..
MAX1290AEEI+ ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 20 GNDIndustrial Control Systems Data LoggingMAX1292D3/D11 6 19 COMEnergy Manageme ..
MAX1290BCEI ,400ksps / +5V / 8-/4-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceMAX1290/MAX129219-1531; Rev 3; 12/02400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference an ..
MAX1290BCEI+T ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1290/MAX1292 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5 LSB Linearitydigi ..
MAX378EJE ,High-Voltage, Fault-Protected Analog MultiplexersELECTRICAL CHARACTERISTICS (continued)(V+ = +15V, V- = -15V; V (Logic Level High) = +2.4V, V (Logic ..
MAX3795ETG ,3.3 V +/-10%, 1 to 4.25 Gbps multirate VCSEL driver with diagnostic monitorfeatures.♦ 2mA to 15mA Modulation CurrentThe automatic power control (APC) adjusts the laser♦ 1mA t ..
MAX3795ETG+T ,1Gbps to 4.25Gbps Multirate VCSEL Driver with Diagnostic Monitorsfeatures.♦ 2mA to 15mA Modulation CurrentThe automatic power control (APC) adjusts the laser♦ 1mA t ..
MAX3798ETJ+ ,1.0625Gbps to 10.32Gbps, Integrated, Low-Power SFP+ Limiting Amplifier and VCSEL DriverFeaturesThe MAX3798 is a highly integrated limiting amplifier♦ Low Power Dissipation of 320mW at 3. ..
MAX3799ETJ+ ,1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driverapplications.♦ -21.5dBm Optical Sensitivity at 1.25Gbps Using aBy providing a selectable data path ..
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersMAX378/MAX37919-1902; Rev 1; 8/94High-Voltage, Fault-ProtectedAnalog Multiplexers_______________
MAX1290ACEI
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1290/MAX1292 low-power,12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and
a high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
VLOGICpin that allows them to interface directly with a
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (VDD= VLOGIC) at a
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1290/MAX1292 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1290 has
eight input channels and the MAX1292 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1290/MAX1292 tri-states INTwhen CSgoes
high. Refer to MAX1262/MAX1264 if tri-stating INTis not
desired.
The MAX1290 is available in a 28-pin QSOP package,
while the MAX1292 comes in a 24-pin QSOP. For pin-
compatible +3V, 12-bit versions, refer to the MAX1291/
MAX1293 data sheet.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouchscreens
Features12-Bit Resolution, ±0.5 LSB Linearity+5V Single-Supply OperationUser-Adjustable Logic Level (+2.7V to +5.5V)Internal +2.5V ReferenceSoftware-Configurable Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1290)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1292)Software-Configurable Unipolar/Bipolar Analog
InputsLow Current:2.5mA (400ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)Internal 6MHz Full-Power Bandwidth Track/HoldByte-Wide Parallel (8 + 4) InterfaceSmall Footprint:28-Pin QSOP (MAX1290)
24-Pin QSOP (MAX1292)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface19-1531; Rev 3; 12/02
Ordering Information
Pin Configurations
Ordering Information continued at end of data sheet.Typical Operating Circuits appear at end of data sheet.
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
VLOGICto GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT)
to GND...........................................-0.3V to (VLOGIC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C).........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C).......667mW
Operating Temperature Ranges
MAX1290_C_ _/MAX1292_C_ _.......................0°C to +70°C
MAX1290_E_ _/MAX1292_E_ _.....................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +5V, COM = GND, = 0, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)(VDD= VLOGIC= +5V ±10%, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 7.6MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Figure 1. Load Circuits for Enable/Disable Times
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics(VDD= VLOGIC= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel InterfaceINTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1290/2 toc10
VDD (V)
REF
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1290/2 toc 11
TEMPERATURE (°C)
REF
(V)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1290/2 toc12
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1290/2 toc13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1290/2 toc14
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1290/2 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1290/2 toc16
VDD (V)
ILOGIC
4.505.004.755.255.50
ypical Operating Characteristics (continued)(VDD= VLOGIC= +5V, VREF= +2.500V, fCLK= 7.6MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________Detailed Description
Converter OperationThe MAX1290/MAX1292 ADCs use a successive-
approximation (SAR) conversion technique and an input
track-and-hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4) out-
put format provides an easy interface to standard micro-
processors (µPs). Figure 2 shows the simplified internal
architecture of the MAX1290/MAX1292.
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuits in
Figures 3a and 3b. In single-ended mode, IN+ is inter-
nally switched to channels CH0–CH7 for the MAX1290
(Figure 3a) and to CH0–CH3 for the MAX1292 (Figure
3b), while IN- is switched to COM (Table 3). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 4).
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLDas a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1290/MAX1292
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/HoldThe MAX1290/MAX1292 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part enters
its hold mode on the fourth falling edge of clock after
writing the control byte. Note that, in internal clock mode,
this is approximately 1µs after writing the control byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive input “-” and the difference of |(IN+) - (IN-)|is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ= 9 (RS + RIN)CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩhave no significant impact on the MAX1290/
MAX1292’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Along with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX1290/MAX1292 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth that make it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing high-frequency signals into the frequen-
cy band of interest, anti-alias filtering is recommended.
Starting a ConversionInitiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1290/MAX1292 for either unipolar or bipolar opera-
tion. A write pulse (WR+ CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
MAX1290/MAX1292
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
