MAX1286EKA-MAX1286ETA+-MAX1287EKA+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX1286ETA+ ,150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, V = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5 ..
MAX1287EKA+T ,150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCsApplicationsLow-Power Data Acquisition PART PIN-PACKAGE TOP MARKPortable Temperature MonitorsMAX128 ..
MAX128AEAI ,Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
MAX128BCAI ,Multirange, +5V, 12-bit DAS with 2-wire serial interface. INL(LSB) +1,-1FeaturesThe MAX127/MAX128 are multirange, 12-bit data' 12-Bit Resolution, 1/2 LSB Linearityacquisit ..
MAX128BCNG+ ,Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interfacefeatures include a 5MHz band-● Two Power-Down Modeswidth track/hold, an 8ksps throughput rate, and ..
MAX1290ACEI ,400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 20 GNDIndustrial Control Systems Data LoggingMAX1292D3/D11 6 19 COMEnergy Manageme ..
MAX3785UTT+ ,6.25Gbps, 1.8V PC Board EqualizerApplicationsPin ConfigurationsHSBI for ≤ 6.4GbpsTOP VIEW (BUMPS ON BOTTOM OF DIE)Double IEEE 802.3a ..
MAX3786UTJ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationMAX378619-2727; Rev 2; 6/041.5Gbps Serial ATA-Compatible Mux/Buffer withLoopback and Equalization
MAX3786UTJ+ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationApplications+Denotes lead-free package.*EP = Exposed pad.1.5Gbps Serial ATA RedundancyTypical Appli ..
MAX3786UTJ+T ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationFeaturesThe MAX3786 is an AC-coupled, serial-ATA (SATA)-♦ < 50ps Total Residual Jitter (20in FR-4, ..
MAX3786UTJ-T ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +85°C. Typical values at V = +3.3V, T = + ..
MAX3787ABL ,1Gbps to 12.5Gbps Passive Equalizer for Backplanes and CablesApplications Pin ConfigurationBackplane Interconnect CompensationTOP VIEW1 2 3Cable Interconnect Co ..

MAX1286EKA-MAX1286ETA+-MAX1287EKA+T
150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs
General Description
The MAX1286–MAX1289 are low-cost, micropower, seri-
al output 12-bit analog-to-digital converters (ADCs)
available in a tiny 8-pin SOT23 and an 8-pin TDFN. The
MAX1286/MAX1288 operate with a single +5V supply.
The MAX1287/MAX1289 operate with a single +3V sup-
ply. The devices feature a successive-approximation
ADC, automatic shutdown, fast wakeup (1.4µs), and a
high-speed 3-wire interface. Power consumption is only
0.5mW (VDD= +2.7V) at the maximum sampling rate of
150ksps. AutoShutdown™ (0.2µA) between conversions
results in reduced power consumption at slower
throughput rates. The MAX1286/MAX1287 provide
2-channel, single-ended operations and accept input
signals from 0 to VREF. The MAX1288/MAX1289 accept
true-differential inputs ranging from 0 to VREF. Data is
accessed using an external clock through the 3-wire
SPI™-/QSPI™-/MICROWIRE™-compatible serial inter-
face. Excellent dynamic performance, low power, ease
of use, and small package size make these converters
ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and minimal space.
Applications
Low-Power Data Acquisition
Portable Temperature Monitors
Flowmeters
Touch Screens
FeaturesSingle-Supply Operation
+3V (MAX1287/MAX1289)
+5V (MAX1286/MAX1288)Autoshutdown Between ConversionsLow Power
245µA at 150ksps
150µA at 100ksps
15µA at 10ksps
2µA at 1ksps
0.2µA in ShutdownTrue-Differential Track/Hold, 150kHz Sampling RateSoftware-Configurable Unipolar/Bipolar
Conversion (MAX1288/MAX1289 Only) SPI-/QSPI-/MICROWIRE-Compatible Interface for
DSPs and ProcessorsInternal Conversion Clock8-Pin SOT23 and 8-Pin TDFN Packages
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
CNVST
REFGND
SCLK
DOUTAIN1 (AIN+)
AIN2 (AIN-)
VDD
SOT23
TOP VIEW
( ) ARE FOR THE MAX1288/MAX1289
MAX1286–
MAX1289
CNVST
GND78
DOUT
SCLKREF21
AIN1 (AIN+)
TDFN
MAX1286–
MAX1289
AIN2 (AIN-)
Pin Configurations
19-2231; Rev 3; 8/10
Ordering Information
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
PARTPIN-PACKAGETOP MARK
MAX1286EKA-T8 SOT23AAFA
MAX1286ETA+T8 TDFN-EP*+AFR
MAX1287EKA-T8 SOT23AAEW
MAX1287ETA+T8 TDFN-EP*+AFN
MAX1288EKA-T8 SOT23AAFC
MAX1288ETA+T8 TDFN-EP*+AFT
MAX1289EKA-T8 SOT23AAEY
MAX1289ETA+T8 TDFN-EP*+AFP
Note:All devices specified over the -40°C to +85°C operating
range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
-Denotes a package containing lead(Pb).
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +3.6V, VREF= +2.5V for MAX1287/MAX1289, or VDD= +4.75V to +5.25V, VREF= +4.096V for MAX1286/MAX1288,
0.1µF capacitor at REF, fSCLK= 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA= TMINto TMAX,unless otherwise
noted. Typical values at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CNVST, SCLK, DOUT to GND....................-0.3V to (VDD+ 0.3V)
REF, AIN1 (AIN+), AIN2 (AIN-) to GND......-0.3V to (VDD+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 9.70mW/°C above TA= +70°C)...696mW
8-Pin TDFN (derate 18.5mW/°C above TA= +70°C)...1481mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)
Lead(Pb)-Free Packages...............................................+260°C
Packages Containing Lead(Pb).....................................+240°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)
Resolution12Bits
Relative Accuracy (Note 2)INL±1.0LSB
Differential NonlinearityDNLNo missing codes over temperature±1.0LSB
Offset Error±2±4LSB
Gain Error (Note 3)±2±4LSB
Gain Temperature Coefficient±0.4ppm/°C
Offset Tem p er atur e C oeffi ci ent±0.4p p m/°C
Channel-to-Channel Offset Matching±0.1LSB
Channel-to-Channel Gain Matching±0.1LSB
Input Common-Mode RejectionCMRVCM = 0V to VDD; zero scale input±0.1mV
DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1286/MAX1288 or VIN = 2.5Vp-p
for MAX1287/MAX1289, 150ksps, fSCLK = 8MHz, (50% duty cycle) AIN- = GND for MAX1288/MAX1289)
Signal to Noise Plus DistortionSINAD70dB
Total Harmonic Distortion
(up to the 5th harmonic)THD-82dB
Spurious-Free Dynamic RangeSFDR86dB
Full-Power Bandwidth-3dB point1MHz
Full-Linear BandwidthSINAD > 68dB100kHz
CONVERSION RATE
Conversion TimetCONVDoes not include tACQ3.7µs
T/H Acquisition TimetACQ1.4µs
Aperture Delay30ns
Aperture Jitter<50ps
Maximum Serial Clock FrequencyfSCLK8MHz
Duty Cycle3070%
ANALOG INPUT
Unipolar0VREFInput Voltage Range (Note 4)Bipolar-VREF /2VREF/2V
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +3.6V, VREF= +2.5V for MAX1287/MAX1289, or VDD= +4.75V to +5.25V, VREF= +4.096V for MAX1286/MAX1288,
0.1µF capacitor at REF, fSCLK= 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. TA= TMINto TMAX,unless otherwise
noted. Typical values at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input Leakage CurrentC hannel not sel ected or conver si on stop p ed ±0.01±1µA
Input Capacitance34pF
EXTERNAL REFERENCE INPUT
Input Voltage RangeVREF1.0VDD
+50mVV
VREF = +2.5V at 150ksps1630
VREF = +4.096V at 150ksps2645Input CurrentIREF
Acquisition/Between conversions±0.01±1
DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT)
Input Low VoltageVIL0.8V
Input High VoltageVIHVDD -1V
Input Leakage CurrentIL±0.01±1.0µA
Input CapacitanceCIN15pF
ISINK = 2mA0.4VOutput Low VoltageVOLISINK = 4mA0.8V
Output High VoltageVOHISOURCE = 1.5mAVDD
-0.5V
Three-State Leakage CurrentCNVST = GND±0.05±10µA
Three-State Output CapacitanceCOUTCNVST = GND15pF
POWER REQUIREMENTS
MAX1286/MAX12884.755.05.25Positive Supply VoltageVDDMAX1287/MAX12892.73.03.6V
fSAMPLE =150ksps245350
fSAMPLE =100ksps150
fSAMPLE =10ksps15VDD = +3V
fSAMPLE =1ksps2
fSAMPLE =150ksps320400
fSAMPLE =100ksps215
fSAMPLE =10ksps22VDD = +5V
fSAMPLE =1ksps2.5
Positive Supply CurrentIDD
Shutdown0.25
VDD = 5V ±5%; full-scale input±0.3±1.0Positive Supply RejectionPSRVDD = +2.7V to +3.6V; full-scale input±0.4±1.2mV
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
TIMING CHARACTERISTICS (Figures 1, 2, and 5)
(VDD= +2.7V to +3.6V, VREF= +2.5V, 0.1µF capacitor at REF, or VDD= +4.75V to +5.25V for MAX1286/MAX1288, VREF= +4.096V,
0.1µF capacitor at REF, fSCLK= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. TA= TMINto TMAX,unless otherwise
noted. Typical values at TA= +25°C.)
PARAMETERSSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK Pulse Width HightCH38ns
SCLK Pulse Width LowtCL38ns
SCLK Fall to DOUT TransitiontDOTCLOAD = 30pF60ns
SCLK Rise to DOUT DisabletDODCLOAD = 30pF100500ns
CNVST Rise to DOUT EnabletDOECLOAD = 30pF80ns
CNVST Fall to MSB ValidtCONVCLOAD = 30pF3.7µs
CNVST Pulse WidthtCSW30ns
Note 1:Unipolar mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset nulled.
Note 4:The absolute input voltage range for the analog inputs is from GND to VDD.
• • •
• • •
• • •
CNVST
SCLK
DOUT
tDOE
HIGH-ZHIGH-Z
tCSWtCL
tCH
tDODtDOT
DOUT
6kΩ
6kΩ
GND
DOUT
GND
VDD
a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Zb) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z
Figure 1. Detailed Serial-Interface Timing Sequence
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1286-9 toc01
OUTPUT CODE
INL (LSB)
MAX1287/MAX1289
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1286-9 toc02
OUTPUT CODE
INL (LSB)
MAX1286/MAX1288
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1286-9 toc03
OUTPUT CODE
DNL (LSB)
MAX1287/MAX1289
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1286-9 toc04
OUTPUT CODE
DNL (LSB)
MAX1286/MAX1288
SUPPLY CURRENT
vs. SAMPLING RATE
MAX1286-9 toc05
SAMPLING RATE (ksps)
SUPPLY CURRENT (
MAX1287/MAX1289
SUPPLY CURRENT
vs. SAMPLING RATE
MAX1286-9 toc06
SAMPLING RATE (ksps)
SUPPLY CURRENT (
MAX1286/MAX1288
Typical Operating Characteristics
(VDD= +3V, VREF= +2.5V for MAX1287/MAX1289. VDD= +5V, VREF= +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,
fSCLK= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA= +25°C, unless otherwise noted.)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1286-9 toc08
SHUTDOWN CURRENT (nA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1286-9 toc07
SUPPLY CURRENT (
SUPPLY CURRENT
vs. TEMPERATURE
MAX1286-9 toc09
SUPPLY CURRENT (
MAX1286
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
Typical Operating Characteristics (continued)
(VDD= +3V, VREF= +2.5V for MAX1287/MAX1284. VDD= +5V, VREF= +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,
fSCLK= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, TA= +25°C, unless otherwise noted.)
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1286-9 toc10
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
OFFSET ERROR
vs. TEMPERATURE
MAX1286-9 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1286-9 toc12
VDD (V)
OFFSET ERROR (LSB)
GAIN ERROR
vs. TEMPERATURE
MAX1286-9 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
GAIN ERROR
vs. SUPPLY VOLTAGE
MAX1286-9 toc14
VDD (V)
GAIN ERROR (LSB)
-2015k30k45k60k
FFT PLOT (SINAD)
MAX1286-9 toc15
FREQUENCY (Hz)
AMPLITUDE (dB)
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
Detailed Description
The MAX1286–MAX1289 ADCs use a successive-
approximation conversion (SAR) technique and an on-
chip track-and-hold (T/H) structure to convert an
analog signal into a 12-bit digital result.
The serial interface provides easy interfacing to micro-
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1286/MAX1287 (2 channels, sin-
gle ended) and the MAX1288/MAX1289 (1 channel,
true differential).
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the
MAX1286–MAX1289s’ input architecture, which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1286/
MAX1287) or AIN+ (MAX1288/MAX1289). The negative
input capacitor is connected to GND (MAX1286/
MAX1287) or AIN- (MAX1288/MAX1289). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the
T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input sig-
nal’s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
period of time. The acquisition time, tACQ, is the maxi-
mum time needed for the signal to be acquired, plus the
power-up time. It is calculated by the following equation:
tACQ= 9 x (RS+ RIN) x 24pF + tPWR
12-BIT
SAR
ADC
CONTROL
OSCILLATOR
INPUT SHIFT
REGISTER
T/H
REF
CNVST
SCLK
DOUT
AIN2
(AIN-)
AIN1
(AIN+)
MAX1286–MAX1289
( ) ARE FOR MAX1288/MAX1289
Figure 3. Simplified Functional Diagram
NAME
PINMAX1286
MAX1287
MAX1288
MAX1289
FUNCTION
1VDDVDDPositive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V
(MAX1286/MAX1288). Bypass with a 0.1µF capacitor to GND.AIN1AIN+Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)AIN2AIN-Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)GNDGNDGroundREFREFExternal Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.CNVSTCNVST
Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).DOUTDOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high
impedance once data has been fully clocked out.SCLKSCLKSerial Clock Input. Clocks out data at DOUT MSB first.EPEPExposed Pad. Connect the exposed pad to ground or leave unconnected.
Pin Description
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
where RIN= 1.5kΩ, RSis the source impedance of the
input signal, and tPWR= 1µs is the power-up time of the
device.
Note:tACQis never less than 1.4µs and any source
impedance below 300Ωdoes not significantly affect the
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening tACQor by
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
Selecting AIN1 or AIN2
(MAX1286/MAX1287)
Select one of the MAX1286/MAX1287s’ two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
tACQto fully acquire the signal. Drive CNVST low to
place the T/H in hold mode. The ADC then performs a
conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be
clocked out using SCLK. Clock out all 12 bits of data
before driving CNVST high for the next conversion. If all
12 bits of data are not clocked out before CNVST is dri-
ven high, AIN2 is selected for the next conversion.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This powers up the ADC and places the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for tACQto fully
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC then performs a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
If all 12 bits of data are not clocked out before CNVST
is driven high, AIN2 is selected for the next conversion.
Selecting Unipolar or Bipolar Conversions
(MAX1288/MAX1289)
Initiate true-differential conversions with the
MAX1288/MAX1289s’ unipolar and bipolar modes,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
exceed AIN- by up to VREF. The output format is
straight binary. In bipolar mode, either input can
exceed the other by up to VREF/2. The output format is
two’s complement.
Note:In both modes, AIN+ and AIN- must not exceed
VDDby more than 50mV or be lower than GND by more
than 50mV.
If unipolar mode is desired (Figure 5a), drive CNVST
high to power up the ADC and place the T/H in track
mode with AIN+ and AIN- connected to the input
capacitors. Hold CNVST high for tACQto fully acquire
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC then performs a conversion and shut-
down automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
Clock out all 12 bits of data before driving CNVST high
for the next conversion. If all 12 bits of data are not
clocked out before CNVST is driven high, bipolar mode
is selected for the next conversion.
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This places the T/H in track mode
with AIN+ and AIN- connected to the input capacitors.
Now hold CNVST high for tACQto fully acquire the sig-
nal. Drive CNVST low to place the T/H in hold mode.
The ADC then performs a conversion and shutdown
automatically. The MSB is available at DOUT after
3.7µs. Data can then be clocked out using SCLK. If all
12 bits of data are not clocked out before CNVST is dri-
ven high, bipolar mode is selected for the next conver-
sion.
Input Bandwidth
The ADC’s input tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
RIN+
HOLD
RIN-
CIN+
REF
GNDDAC
CIN-
TRACKVDD/2
COMPARATOR
GND (AIN-)
AIN2
AIN1 (AIN+)
HOLD
HOLD
( ) ARE FOR MAX1288/MAX1289
Figure 4. Equivalent Input Circuit

Partno	Mfg	Dc	Qty	Available	Descript
MAX1286EKA	MAXIM	N/a	750	avai	150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs
MAX1286ETA+	MAIXM	N/a	2500	avai	150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs
MAX1287EKA+T	MAXIM	N/a	180	avai	150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs