MAX1282BEUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 12-Bit ADCs with Internal ReferenceFeaturesThe MAX1282/MAX1283 12-bit analog-to-digital convert- 4-Channel Single-Ended or 2-Channele ..
MAX1284BCSA ,400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1284(V = +4.5V to +5.5V; f = 6.4MHz, 50% duty cycle, 16 clocks/conver ..
MAX1284BESA ,400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal ReferenceApplicationsTEMP. PIN- SUPPLYPARTPortable Data Logging RANGE PACKAGE VOLTAGE (V)Data Acquisition MA ..
MAX1284BESA+ ,400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1284(V = +4.5V to +5.5V; f = 6.4MHz, 50% duty cycle, 16 clocks/conver ..
MAX1284BESA+T ,400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal ReferenceApplicationsPIN- SUPPLYPART TEMP RANGEPortable Data LoggingPACKAGE VOLTAGE (V)Data AcquisitionMAX12 ..
MAX1285BCSA ,400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1284 (continued)(V = +4.5V to +5.5V; f = 6.4MHz, 50% duty cycle, 16 c ..
MAX3783UCM , 2.7Gbps Dual Mux/Buffer with Loopback
MAX3784AUGE ,+3.3 V, 5 Gbps, PC board equalizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel16 15 14 134x Multiplexed 1.25Gbps ..
MAX3784AUTE+ ,5Gbps PCB EqualizerELECTRICAL CHARACTERISTICS(V = +3V to +3.6V, T = 0°C to +85°C. Typical values are at V = +3.3V and ..
MAX3784AUTE+T ,5Gbps PCB EqualizerFeaturesThe MAX3784/MAX3784A 5Gbps equalizers provide♦ Spans 40in (1m) of FR-4 PCBcompensation for ..
MAX3784UGE-T ,5Gbps PCB EqualizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel12 11 9104x Multiplexed 1.25Gbps Et ..
MAX3785UTT+ ,6.25Gbps, 1.8V PC Board EqualizerApplicationsPin ConfigurationsHSBI for ≤ 6.4GbpsTOP VIEW (BUMPS ON BOTTOM OF DIE)Double IEEE 802.3a ..
MAX1282BEUE
300ksps/400ksps / Single-Supply / 4-Channel / Serial 12-Bit ADCs with Internal Reference
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference19-1688; Rev 0; 5/00
Typical Operating Circuit appears at end of data sheet.
Pin Configuration
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
General DescriptionThe MAX1282/MAX1283 12-bit analog-to-digital convert-
ers (ADCs) combine a 4-channel analog-input multiplexer,
high-bandwidth track/hold (T/H), and serial interface with
high conversion speed and low power consumption. The
MAX1282 operates from a single +4.5V to +5.5V supply;
the MAX1283 operates from a single +2.7V to +3.6V sup-
ply. Both devices’ analog inputs are software configurable
for unipolar/bipolar and single-ended/pseudo-differential
operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1282/
MAX1283 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDDrange may
also be used.
The MAX1282/MAX1283 provide a hardwired SHDNpin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions.
The MAX1282/MAX1283 are available in 16-pin TSSOP
packages.
ApplicationsPortable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Features4-Channel Single-Ended or 2-Channel
Pseudo-Differential InputsInternal Multiplexer and Track/HoldSingle-Supply Operation
+4.5V to +5.5V (MAX1282)
+2.7V to +3.6V (MAX1283)Internal +2.5V Reference400kHz Sampling Rate (MAX1282)Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
Software-Configurable Unipolar or Bipolar Inputs16-Pin TSSOP Package
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX1282
(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fOSC= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD_ to GND...........................................................-0.3V to +6V
VDD1to VDD2.......................................................-0.3V to +0.3V
CH0–CH3, COM to GND..........................-0.3V to (VDD_ +0.3V)
REF, REFADJ to GND................................-0.3V to VDD_ +0.3V)
Digital Inputs to GND..............................................-0.3V to +6V
Digital Outputs to GND.............................-0.3V to (VDD_ +0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 6.7mW/°C above +70°C)........535mW
Operating Temperature Ranges
MAX1282BCUE/MAX1283BCUE.......................0°C to +70°C
MAX1282BEUE/MAX1283BEUE.....................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fOSC= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fOSC= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS—MAX1283
(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fOSC= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fOSC= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fOSC= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS—MAX1282
(Figures 1, 2, 5, 6; VDD1= VDD2= +4.5V to +5.5V, TA= TMINto TMAX, unless otherwise noted.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1283
(Figures 1, 2, 5, 6; VDD1= VDD2= +2.7V to +3.6V, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD1= VDD2= VDD(MIN), COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset nulled.
Note 4:Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH3–CH0 and COM) is from GND to VDD1.
Note 7: External load should not change during conversion for specified accuracy.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p. An external reference below 2.5V compro-
mises the performance of the ADC.
Note 9:Electrical characteristics are guaranteed from VDD1(MIN)= VDD2(MIN)to VDD1(MAX)= VDD2(MIN). For operations beyond
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10:AIN = midscale, unipolar mode. MAX1282 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK= 6.4MHz, 0 to 5V.
MAX1283 tested with same loads, fSCLK= 4.8MHz, 0 to 3V.
Note 11:SCLK = DIN = GND, CS= VDD1.
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics
(MAX1282: VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1283: VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
REFERENCE VOLTAGE
vs. TEMPERATUREMAX1282/3-10
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1282/3-11
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1282/3-12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1282/3-13
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1282/3-14
TEMPERATURE (°C)
GAIN ERROR (LSB)
-4010-15356085
ypical Operating Characteristics (continued)(MAX1282: VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1283: VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
Detailed DescriptionThe MAX1282/MAX1283 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 12-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1282/MAX1283.
Pseudo-Differential InputThe equivalent circuit of Figure 4 shows the MAX1282/
MAX1283’s input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1 and
CH2/CH3. Configure the channels according to Tables
1 and 2.
The MAX1282/MAX1283 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
The maximum voltage variation is determined by:
A 0.65Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLDas a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLDfrom IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1 / 2 within the limits of 12-bit resolu-
tion. This action is equivalent to transferring a
12pF ✕(VIN+ - VIN-) charge from CHOLDto the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, the difference of [(IN+) - (IN-)]is con-
verted. At the end of the conversion, the positive input
connects back to IN+ and CHOLDcharges to the input
signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
tACQ= 9 ✕(RS+ RIN) ✕18pF
where RIN= 800Ωand RS= the source impedance of
the input signal; tACQis never less than 400ns
(MAX1282) or 625ns (MAX1283). Note that source
impedances below 2kΩdo not significantly affect the
ADC’s AC performance.
Input BandwidthThe ADC’s input tracking circuitry has a 6MHz
(MAX1282) or 3MHz (MAX1283) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDD1and GND, allow the channel input pins to swing
from GND -0.3V to VDD1+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD1by more than 50mV or be
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Starting a ConversionStart a conversion by clocking a control byte into DIN.
With CSlow, each rising edge on SCLK clocks a bit from
DIN into the MAX1282/MAX1283’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
The MAX1282/MAX1283are compatible with SPI/
QSPI/MICROWIREdevices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time.Using the Typical Operating Circuit, the sim-
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
