MAX1261ACEI+ ,250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 24 GNDMAX1261Industrial Control Systems Data LoggingD3/D11 6 23 COMEnergy Manageme ..
MAX1265ACEI ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1266BEEI ,420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAX126CCAX ,2x4-Channel, Simultaneous-Sampling 14-Bit DASELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0V; f = 2.0MHz; external clock (50% duty cycl ..
MAX126CCAX+D ,2x4-Channel, Simultaneous-Sampling, 14-Bit DASApplicationsMultiphase Motor ControlPower-Grid SynchronizationPower-Factor MonitoringTypical Operat ..
MAX126CCAX+D ,2x4-Channel, Simultaneous-Sampling, 14-Bit DASFeaturesThe MAX125/MAX126 are high-speed, multichannel,♦ Four Simultaneous-Sampling T/H Amplifiers ..
MAX3735AETG ,2.7Gbps, Low-Power SFP Laser DriversApplications*Dice are designed to operate from -40°C to +85°C, but areGigabit Ethernet SFP/SFF Tran ..
MAX3735AETG+ ,2.7Gbps, Low-Power SFP Laser DriversELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values at V = +3.3V, I ..
MAX3735AETG+T ,2.7Gbps, Low-Power SFP Laser DriversApplicationsMAX3735AETG+ -40°C to +85°C 24 Thin QFN-EP**Gigabit Ethernet SFP/SFF Transceiver Module ..
MAX3735EGG ,2.7Gbps, Low-Power SFP Laser DriversELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values at V = +3.3V, I ..
MAX3736ETE+ ,3.2Gbps, Low-Power, Compact, SFP Laser DriverApplicationsMAX3736ETE -40°C to +85°C 16 Thin QFN-EP* MAX3736ETE+ -40°C to +85°C 16 Thin QFN-EP* Gi ..
MAX3736ETE+T ,3.2Gbps, Low-Power, Compact, SFP Laser DriverELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values are at V = +3.3 ..
MAX1261ACEI+
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1261/MAX1263 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a VLOGIC
pin that allows them to interface directly with a +1.8V to
+5.5V digital supply.
Power consumption is only 5.7mW (VDD = VLOGIC) at
the maximum sampling rate of 250ksps. Two software-
selectable power-down modes enable the MAX1261/
MAX1263 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can
cut supply current to under 10µA at reduced sampling
rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1261 has
eight input channels and the MAX1263 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1261 is available in a 28-pin QSOP package,
while the MAX1263 is available in a 24-pin QSOP. For
pin-compatible +5V, 12-bitversions, refer to the
MAX1262/MAX1264 data sheet.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouch Screens
Features12-Bit Resolution, ±0.5 LSB Linearity+3V Single OperationUser-Adjustable Logic Level (+1.8V to +3.6V)Internal +2.5V ReferenceSoftware-Configurable, Analog Input Multiplexer
8-Channel Single Ended/
4-Channel Pseudo-Differential (MAX1261)
4-Channel Single Ended/
2-Channel Pseudo-Differential (MAX1263)Software-Configurable, Unipolar/Bipolar InputsLow Power
1.9mA (250ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)Internal 3MHz Full-Power Bandwidth Track/HoldByte-Wide Parallel (8 + 4) InterfaceSmall Footprint
28-Pin QSOP (MAX1261)
24-Pin QSOP (MAX1263)
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface19-2719; Rev 0; 04/03
PART
MAX1261ACEI0°C to +70°C
TEMP RANGEPIN-PACKAGE28 QSOP
Ordering Information
Pin Configurations±0.5
INL
(LSB)MAX1261BCEI0°C to +70°C±128 QSOP
Ordering Information continued at end of data sheet.Typical Operating Circuits appear at end of data sheet.14CH7CS
QSOPTOP VIEW
VLOGIC
VDD
REF
REFADJ
GND
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6CLK
INT
D0/D8
D1/D9
D2/D10
D3/D11
HBEN
MAX1261
Pin Configurations continued at end of data sheet.MAX1261BEEI
MAX1261AEEI
-40°C to +85°C±1
-40°C to +85°C±0.528 QSOP
28 QSOP
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle); TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
VLOGICto GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND ................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND...-0.3V to (VLOGIC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C) ..........762mW
28-Pin QSOP (derate 8.0mW/°C above +70°C) ..........667mW
Operating Temperature Ranges
MAX1261_C_ _/MAX1263_C_ _..........................0°C to +70°C
MAX1261_E_ _/MAX1263_E_ _.......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
External acquisition or external clock mode
Internal acquisition/internal clock mode
MAX126_A
External acquisition/internal clock mode
External clock mode
-3dB rolloff
SINAD > 68dB
fIN= 125kHz, VIN= 2.5VP-P(Note 4)
fIN1= 49kHz, fIN2= 52kHz
MAX126_B
No missing codes overtemperature
(Note 3)
CONDITIONS50Aperture Delay625tACQTrack/Hold Acquisition Time
tCONVConversion Time (Note 5)
MHz3Full-Power Bandwidth
kHz250Full-Linear Bandwidth-78Channel-to-Channel Crosstalk76IMDIntermodulation Distortion80SFDRSpurious-Free Dynamic Range-78Total Harmonic Distortion
(Including 5th-Order Harmonic)THD
±0.5INLRelative Accuracy (Note 2)
Bits12RESResolution6770SINADSignal-to-Noise Plus Distortion
LSB±0.2Channel-to-Channel Offset
Matching
ppm/°C±2.0Gain Temperature Coefficient
LSB±1
LSB±1DNLDifferential Nonlinearity
LSB±4Offset Error
LSB±4Gain Error
UNITSMINTYPMAXSYMBOLPARAMETERInternal acquisition/internal clock mode
External acquisition or external clock mode
<200ps<50Aperture Jitter
MHz0.14.8fCLKExternal Clock Frequency3070Duty Cycle
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (fIN(sine wave)= 50kHz, VIN= 2.5VP-P, 250ksps, external fCLK= 4.8MHz, bipolar input mode)
CONVERSION RATE
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle); TA= TMINto TMAXunless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER0 to 0.5mA output load (Note 7)
To power down the internal reference
For small adjustments= 0°C to +70°C
On-/off-leakage current, VIN= 0 or VDD
Unipolar, VCOM= 01.0VDD +
50mVVREFREF Input Voltage Range4.710Capacitive Bypass at REF0.011Capacitive Bypass at REFADJ
mV/mA0.2Load RegulationVDD- 1.0REFADJ High Threshold±100REFADJ Input Range
±20ppm/°CTCREFREF Temperature Coefficient15REF Short-Circuit Current2.492.52.51REF Output Voltage12CINInput Capacitance±0.01±1Multiplexer Leakage Current
Analog Input Voltage Range,
Single Ended and Differential
(Note 6)
0VREF
VIN= VDD
ISOURCE= 1mA
ISINK= 1.6mA
VIN= 0 or VDD
VLOGIC= 2.7V±0.1±1ILEAKAGETri-State Leakage CurrentVLOGIC- 0.5VOHOutput High Voltage0.4VOLOutput Low Voltage15CINInput Capacitance±0.1±1IINInput Leakage Current200VHYSInput Hysteresis
2.0= VDDpF15COUTTri-State Output Capacitance
Bipolar, VCOM= VREF / 2-VREF/2+VREF/2
VREF= 2.5V, fSAMPLE= 250kspsµA200300IREFREF Input CurrentShutdown mode2
VLOGIC= 1.8VV1.5VIHInput High Voltage
VLOGIC= 1.8VV0.5VILInput Low VoltageVLOGIC= 2.7V0.8
ANALOG INPUTS
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REF
DIGITAL INPUTS AND OUTPUTS
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle); TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERShutdown mode
Standby mode
Operating mode,
fSAMPLE= 250ksps210
0.91.2mA
2.32.62.73.6VDDAnalog Supply Voltage
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle); TA= TMINto TMAXunless otherwise noted. Typical values are at TA= +25°C.)
VLOGICCurrentILOGICCL= 20pF210µA
Power-Supply RejectionPSRVDD= 3V ±10%, full-scale input±0.4±0.9mV
fSAMPLE= 250ksps
Not converting1.8VDD+
0.3VLOGICDigital Supply Voltageto CLK Fall Setup TimetCWS40nsCLK Pulse Width HighCLK Period
tCH40
tCP208
CLK Pulse Width LowtCL40ns
Data Valid to WRRise TimetDS40nsRise to Data Valid Hold TimetDH0ns
CLK Fall to WRHold TimetCWH40nsto CLK or WR
Setup TimetCSWS60ns
CLK or WRto CS
Hold TimetCSWH0nsPulse WidthtCS100nsPulse WidthtWR60ns
tTC20100ns
(Note 8)
CLOAD= 20pF (Figure 1)
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONSRise to Output Disable
POWER REQUIREMENTSInternal reference
Internal reference
External reference
External reference
IDDPositive Supply Current
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +3V, COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle); TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
tTR2070nsCLOAD= 20pF, Figure 1RDRise to Output DisableFall to Output Data ValidtDO2070nsFall to INTHigh DelaytINT1100nsFall to Output Data ValidtDO2110ns
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONSHBEN to Output Data ValidtDO120110nsCLOAD= 20pF, Figure 1
3kΩ
3kΩ
DOUT
DOUT
VLOGIC
a) HIGH-Z TO VOH AND VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOLCLOAD
20pFCLOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics(VDD= VLOGIC= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1261/63 toc01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1261/63 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
0.110k1011001k100k1M
SUPPLY CURRENT
vs. SAMPLE FREQUENCYMAX1261/63 toc03
fSAMPLE (Hz)
IDD
10,000
WITH INTERNAL
REFERENCE
WITH EXTERNAL
REFERENCE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc04
VDD (V)
IDD
(mA)
RL = ∞
CODE = 101010100000
SUPPLY CURRENT vs. TEMPERATURE
MAX1261/63 toc05
TEMPERATURE (°C)
IDD
(mA)
RL = ∞
CODE = 101010100000
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc06
VDD (V)
STANDBY I
STANDBY CURRENT vs. TEMPERATURE
MAX1261/63 toc07
TEMPERATURE (°C)
STANDBY I
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1261/63 toc08
VDD (V)
POWER-DOWN I
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1261/63 toc09
TEMPERATURE (°C)
POWER-DOWN I
-4035-15106085
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel InterfaceINTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1261/63 toc11
TEMPERATURE (°C)
REF
(V)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1261/63 toc12
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1261/63 toc13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1261/63 toc14
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1261/63 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1261/63 toc16
VDD (V)
ILOGIC
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
MAX1261/63 toc17
TEMPERATURE (°C)
ILOGIC
-401035-156085
ypical Operating Characteristics (continued)(VDD= VLOGIC= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1261/63 toc10
VDD (V)
REF
(V)
2040020060080010001200
FFT PLOTMAX1261/63 toc18
FREQUENCY (kHz)
AMPLITUDE (dB)
VDD = 3V
fIN = 50kHz
fSAMPLE = 250ksps
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
MAX1263MAX1261FUNCTION
PINDigital Power Supply. VLOGICpowers the digital outputs of the data converter and can
range from +1.8V to (VDD + 300mV).VLOGIC28
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.VDD27
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to
GND when using the internal reference.REF26
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01µF capacitor. When using an external reference, connect REFADJ to VDDto disable
the internal bandgap reference.
REFADJ25
Analog and Digital GroundGND24
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.COM23
Analog Input Channel 0CH022
Analog Input Channel 1CH121
Analog Input Channel 2CH220
Analog Input Channel 3CH319
Analog Input Channel 4CH418
Analog Input Channel 5CH517
Analog Input Channel 6CH616
Analog Input Channel 7CH715
Active-Low Chip Select. When CSis high, digital outputs (D7–D0) are high impedance.CS14
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In
internal clock mode, connect this pin to either VDDor GND.CLK13
Active-Low Write Select. When CSis low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CSis
low in external acquisition mode, the first rising edge on WRends acquisition and starts a
conversion.12
Active-Low Read Select. If CSis low, a falling edge on RDenables the read operation on
the data bus.RD11
INTgoes low when the conversion is complete and the output data is ready.INT10
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)D0/D89
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)D1/D98
Tri-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1)D2/D107
Tri-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1)D3/D116
Tri-State Digital I/O Line (D4)D45
Tri-State Digital I/O Line (D5)D54
Tri-State Digital I/O Line (D6)D63
Tri-State Digital I/O Line (D7)D72
High Byte Enable. Used to multiplex the 12-bit conversion result:
1: Four MSBs are multiplexed on the data bus.
0: Eight LSBs are available on the data bus.
HBEN1
NAME
Detailed Description
Converter OperationThe MAX1261/MAX1263 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1261/MAX1263.
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1261
(Figure 3a) and to CH0–CH3 for the MAX1263 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode, IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLDas a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 12-bit resolution. This action is equivalent to
transferring a 12pF[(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
MAX1261/MAX1263
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel InterfaceT/H
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
17kΩ888
SUCCESSIVE-
APPROXIMATION
REGISTER
MUX
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
( ) ARE FOR MAX1261 ONLY.
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
AND
LATCHES
REFREFADJ
1.22V
REFERENCE
D0–D7
8-BIT DATA BUS
(CH5)
(CH4)
(CH7)
(CH6)
CH3
CH2
CH1
CH0
COM
CLK
VDD
HBEN
GND
VLOGIC
MAX1261
MAX1263
AV =
COMP
INT
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1261/MAX1263
MAX1261/MAX1263
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/HoldThe MAX1261/MAX1263 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative (-) input, and the difference of (IN+) - (IN-)is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ= 9(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the ADC’s input capacitance. Source impedances
below 3kΩhave no significant impact on the MAX1261/
MAX1263s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX1261/MAX1263 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1261/MAX1263 for either unipolar or bipolar opera-
tion. A write pulse (WR+ CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
250ksps, +3V, 8-/4-Channel,12-Bit ADCs
with +2.5V Reference and Parallel InterfaceCH0
CH2
CH1
CH3
CH4
CH6
CH7
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3a. MAX1261 Simplified Input Structure
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3b. MAX1263 Simplified Input Structure
