MAX12555ETL+ ,14-Bit, 95Msps, 3.3V ADCfeatures a 300µW power-down mode to ±0.35V to ±1.10Vconserve power during idle periods.♦ Common-Mod ..
MAX12557ETK ,Dual, 65Msps, 14-Bit, IF/Baseband ADCApplications(Msps) (Bits)IF and Baseband Communication ReceiversMAX12557 65 14Cellular, LMDS, Point ..
MAX1257BETM ,2.5 V, 12-bit, multichannel ADC/DAC with FIFO, temperature sensing, and GPIO portFeaturesage from +2.7V to +3.6V (MAX1221/MAX1223/MAX1257)and from +4.75V to +5.25V (MAX1220/MAX1222 ..
MAX1257BETM+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsGeneral Description Benefits and
MAX1257BETM+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsElectrical Characteristics(V = V = 2.7V to 3.6V (MAX1257), external reference V = 2.5V (MAX1257), V ..
MAX1258BETM ,4.096 V, 12-bit, multichannel ADC/DAC with FIFO, temperature sensing, and GPIO portApplicationsControls for Optical ComponentsBase-Station Control Loops SPI and QSPI are trademarks o ..
MAX3680EAI+ ,+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3680EAI+T ,+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL OutputsApplications ________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RA ..
MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential loads = 100W , T = -40°C to +85°C, unle ..
MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RA ..
MAX3681EAG+ ,+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RAN ..
MAX368CPN ,Fault-Protected Analog Multiplexer with LatchGeneral Description
Maxim's MAX368/369 are 8 channel single-ended (1 of
8) and 4 channel differ ..
MAX12555ETL+
14-Bit, 95Msps, 3.3V ADC
General DescriptionThe MAX12555 is a 3.3V, 14-bit, 95Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noiseinternal quantizer. The analog input stage accepts single-
ended or differential signals. The MAX12555 is optimizedfor high dynamic performance, low power, and small
size. Excellent dynamic performance is maintained from
baseband to input frequencies of 175MHz and beyond,making the MAX12555 ideal for intermediate-
frequency (IF) sampling applications.
Powered from a single 3.3V supply, the MAX12555 con-
sumes only 497mW while delivering a typical 72dB sig-nal-to-noise ratio (SNR) performance at a 175MHz input
frequency. In addition to low operating power, theMAX12555 features a 300µW power-down mode to
conserve power during idle periods.
A flexible reference structure allows the MAX12555 to use
the internal 2.048V bandgap reference or accept anexternally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.10V. The MAX12555 provides a com-mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX12555 supports either a single-ended or differ-
ential input clock. Wide variations in the clock dutycycle are compensated with the ADC’s internal duty-
cycle equalizer (DCE).
ADC conversion results are available through a 14-bit,
parallel, CMOS-compatible output bus. The digital out-put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminatesexternal components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing theMAX12555 to interface with various logic levels.
The MAX12555 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
ApplicationsIF and Baseband Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
Medical Imaging Including Positron Emission
Tomography (PET)
Video Imaging
Portable Instrumentation
Low-Power Data Acquisition
FeaturesDirect IF Sampling Up to 400MHzExcellent Dynamic Performance
74dB/72dB SNR at fIN= 3MHz/175MHz
87.4dBc/76.2dBc SFDR at fIN= 3MHz/175MHzLow Noise Floor: 74.6dBFS3.3V Low-Power Operation
465mW (Single-Ended Clock Mode)
497mW (Differential Clock Mode)
300µW (Power-Down Mode)Fully Differential or Single-Ended Analog InputAdjustable Full-Scale Analog Input Range
±0.35V to ±1.10VCommon-Mode ReferenceCMOS-Compatible Outputs in Two’s Complement
or Gray CodeData-Valid Indicator Simplifies Digital InterfaceData Out-of-Range IndicatorMiniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN
Package with Exposed PaddleEvaluation Kit Available (Order MAX12555EVKIT)
MAX12555
14-Bit, 95Msps, 3.3V ADC
Ordering Information19-3447; Rev 1; 2/05
EVALUATION KIT
AVAILABLE
PART*PIN-PACKAGEPKG CODEMAX12555ETL40 Thin QFNT4066-3
MAX12555ETL+40 Thin QFNT4066-3
Pin-Compatible Versions
PART
SAMPLING
RATE
(Msps)
RESOLUTION
(BITS)
TARGET
APPLICATION
MAX125559514IF/BasebandMAX125548014IF/Baseband
MAX125536514IF/Baseband
MAX195389512IF/Baseband
MAX12098012IF
MAX12116512IF
MAX12088012Baseband
MAX12076512Baseband
MAX12064012Baseband
Pin Configuration appears at end of data sheet.+Denotes lead-free package.
*All devices specified over the -40°C to +85°C operating range.
MAX12555
14-Bit, 95Msps, 3.3V ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +3.6V
OVDDto GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INP, INN to GND...-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN, COM
to GND................-0.3V to the lower of (VDD+ 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
D13–D0, DAV, DOR to GND....................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)Resolution14Bits
Integral NonlinearityINLfIN = 3MHz±1.6LSB
Differential NonlinearityDNLfIN = 3MHz±0.65LSB
Offset ErrorVREFIN = 2.048V±0.1±0.78%FS
Gain ErrorVREFIN = 2.048V±0.35±5.3%FS
ANALOG INPUT (INP, INN)Differential Input Voltage RangeVDIFFDifferential or single-ended inputs±1.024V
Common-Mode Input VoltageVDD / 2V
CPARFixed capacitance to ground2Input Capacitance
(Figure 3)CSAMPLESwitched capacitance4.5pF
CONVERSION RATEMaximum Clock FrequencyfCLK95MHz
Minimum Clock Frequency5MHz
Data LatencyFigure 68.0Clock
cycles
DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)Small-Signal Noise FloorSSNFInput at less than -35dBFS-74.6dBFS
fIN = 3MHz at -0.5dBFS (Notes 3, 4)69.874
fIN = 47.5MHz at -0.5dBFS73.6
fIN = 70MHz at -0.5dBFS (Notes 3, 4)69.673.4Signal-to-Noise RatioSNR
fIN = 175MHz at -0.5dBFS (Notes 3, 4)68.772
fIN = 3MHz at -0.5dBFS (Notes 3, 4)68.773.6
fIN = 47.5MHz at -0.5dBFS73.2
fIN = 70MHz at -0.5dBFS (Notes 3, 4)68.372.1Signal-to-Noise and DistortionSINAD
fIN = 175MHz at -0.5dBFS (Notes 3, 4)65.370.3
MAX12555
14-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfIN = 3MHz at -0.5dBFS (Notes 3, 4)74.587.4
fIN = 47.5MHz at -0.5dBFS86
fIN = 70MHz at -0.5dBFS (Notes 3, 4)73.379Spurious-Free Dynamic RangeSFDR
fIN = 175MHz at -0.5dBFS (Notes 3, 4)67.876.2
dBc
fIN = 3MHz at -0.5dBFS-84-73.7
fIN = 47.5MHz at -0.5dBFS-83.2
fIN = 70MHz at -0.5dBFS (Notes 3, 4)-77.8-72.4Total Harmonic DistortionTHD
fIN = 175MHz at -0.5dBFS (Notes 3, 4)-75.5-67.2
dBc
fIN = 3MHz at -0.5dBFS-88.1
fIN = 47.5MHz at -0.5dBFS-90
fIN = 70MHz at -0.5dBFS-92.5Second HarmonicHD2
fIN = 175MHz at -0.5dBFS-84.2
dBc
fIN = 3MHz at -0.5dBFS-90
fIN = 47.5MHz at -0.5dBFS-88.9
fIN = 70MHz at -0.5dBFS-79.2Third HarmonicHD3
fIN = 175MHz at -0.5dBFS-76.5
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS-79
Intermodulation DistortionIMD
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS-75
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS-80
Third-Order IntermodulationIM3
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS-76
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS80
Two-Tone Spurious-Free
Dynamic RangeSFDRTT
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS76
dBc
Aperture DelaytADFigure 41.2ns
Aperture JittertAJFigure 4<0.2psRMS
Output NoisenOUTINP = INN = COM1.07LSBRMS
Overdrive Recovery Time±10% beyond full scale1Clock
cycles
MAX12555
14-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)REFOUT Output VoltageVREFOUT1.9802.0482.066V
COM Output VoltageVCOMVDD / 21.65V
Differential-Reference Output
VoltageVREFVREF = VREFP - VREFN = VREFIN x 3/41.536V
REFOUT Load Regulation-1.0mA < IREFOUT < +0.1mA35mV/mA
REFOUT Temperature CoefficientTCREF+50ppm/°C
Short to VDD—sinking0.24REFOUT Short-Circuit CurrentShort to GND—sourcing2.1mA
U F F ER ED EXT ER N A L R EF ER EN C E ( R EF IN d r i v e n e x t e r n a l ly ; VR EF IN = 2.0 4 8 V, VR EF P, VR EF N , a n d VC OM a r e g e n e r a t e d in t e r n a lly ) REFIN Input VoltageVREFIN2.048V
REFP Output VoltageVREFP(VDD / 2) + (VREFIN x 3/8)2.418V
REFN Output VoltageVREFN(VDD / 2) - (VREFIN x 3/8)0.882V
COM Output VoltageVCOMVDD / 21.601.651.70V
Differential-Reference Output
VoltageVREFVREF = VREFP - VREN = VREFIN x 3/41.4541.604V
Differential-Reference
Temperature Coefficient±25ppm/°C
REFIN Input Resistance>50MΩ
N B U F F ER ED EXT ER N A L R EF ER EN C E ( R EF IN = G N D ; VR EF P, VR EF N , a n d VC OM a r e a p p l ie d e x t e r n a l ly ) COM Input VoltageVCOMVDD / 21.65V
REFP Input VoltageVREFP - VCOM0.768V
REFN Input VoltageVREFN - VCOM-0.768V
Differential-Reference Input
VoltageVREFVREF = VREFP - VREFN = VREFIN x 3/41.536V
REFP Sink CurrentIREFPVREFP = 2.418V1.4mA
REFN Source CurrentIREFNVREFN = 0.882V1.0mA
COM Sink CurrentICOMVCOM = 1.650V1.0mA
REFP, REFN Capacitance13pF
COM Capacitance6pF
CLOCK INPUTS (CLKP, CLKN)Single-Ended Input High
ThresholdVIHCLKTYP = GND, CLKN = GND0.8 x
VDDV
Single-Ended Input Low
ThresholdVILCLKTYP = GND, CLKN = GND0.2 x
VDDV
Minimum Differential Input
Voltage SwingCLKTYP = high0.2VP-P
MAX12555
14-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Input Common-Mode
VoltageCLKTYP = highVDD / 2V
Input ResistanceRCLKFigure 55kΩ
Input CapacitanceCCLK2pF
DIGITAL INPUTS (CLKTYP, DCE, G/T, PD)Input High ThresholdVIH0.8 x
OVDDV
Input Low ThresholdVIL0.2 x
OVDDV
VIH = OVDD±5Input Leakage CurrentVIL = 0±5µA
Input CapacitanceCDIN5pF
DIGITAL OUTPUTS (D13–D0, DAV, DOR)D13–D0, DOR, ISINK = 200µA0.2Output-Voltage LowVOLDAV, ISINK = 600µA0.2V
D13–D0, DOR, ISOURCE = 200µAOVDD -
0.2Output-Voltage HighVOH
DAV, ISOURCE = 600µAOVDD -
Tri-State Leakage CurrentILEAK(Note 5)±5µA
D13–D0, DOR Tri-State Output
CapacitanceCOUT(Note 5)3pF
DAV Tri-State Output
CapacitanceCDAV(Note 5)6pF
POWER REQUIREMENTSAnalog Supply VoltageVDD3.153.33.60V
Digital Output Supply VoltageOVDD1.71.8VDD +
0.3VV
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
Analog Supply CurrentIVDD
Power-down mode clock idle, PD = OVDD0.1
MAX12555
14-Bit, 95Msps, 3.3V ADC
Note 1:Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization.
Note 2:See definitions in the Parameter Definitions section at the end of this data sheet.
Note 3:Specifications guaranteed by design and characterization. Devices tested for performance during production test.
Note 4:Due to test-equipment-jitter limitations at 175MHz, 0.06% of the spectrum on each side of the fundamental is excluded from
the spectral analysis.
Note 5:During power-down, D13–D0, DOR, and DAV are high impedance.
Note 6:Digital outputs settle to VIHor VIL.
Note 7:Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNormal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
Analog Power DissipationPDISS
Power-down mode clock idle, PD = OVDD0.3
Normal operating mode,
fIN = 175MHz at -0.5dBFS, OVDD = 1.8V,
CL ≈ 5pF
10.2mADigital Output Supply CurrentIOVDD
Power-down mode clock idle, PD = OVDD8µA
TIMING CHARACTERISTICS (Figure 6)Clock Pulse-Width HightCH5.2ns
Clock Pulse-Width LowtCL5.2ns
Data-Valid DelaytDAVCL = 5pF (Note 6)5.2ns
Data Setup Time Before Rising
Edge of DAVtSETUPCL = 5pF (Notes 6, 7)5.5ns
Data Hold Time After Rising Edge
of DAVtHOLDCL = 5pF (Notes 6, 7)4.0ns
Wake-Up Time from Power-DowntWAKEVREFIN = 2.048V10ms
MAX12555
14-Bit, 95Msps, 3.3V ADCSINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc01
fCLK = 95MHz
fIN = 3.00354004MHz
AIN = -0.5dBFS
SNR = 73.82dB
SINAD = 73.31dB
THD = -82.8dBc
SFDR = 86.3dBc
HD2
HD3HD5HD7HD9
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc02
fCLK = 95MHz
fIN = 47.30285645MHz
AIN = -0.5dBFS
SNR = 73.13dB
SINAD = 72.74dB
THD = -83.4dBc
SFDR = 85.1dBc
HD2
HD5
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc03
fCLK = 95MHz
fIN = 70.00915527MHz
AIN = -0.5dBFS
SNR = 73.12dB
SINAD = 71.50dB
THD = -76.6dBc
SFDR = 77.8dBc
010152052530354045
HD7HD5HD2
HD3
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc04
fCLK = 95MHz
fIN = 174.8895264MHz
AIN = -0.5dBFS
SNR = 71.29dB
SINAD = 68.98dB
THD = -72.8dBc
SFDR = 74.4dBc
HD2HD5
HD3
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc05
fCLK = 95MHz
fIN = 225.010376MHz
AIN = -0.5dBFS
SNR = 70.67dB
SINAD = 67.70dB
THD = -70.7dBc
SFDR = 72.5dBc
HD3
HD5HD9HD7
HD2
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc06
fCLK = 95MHz
fIN1 = 68.49579MHz
AIN1 = -6.9dBFS
fIN2 = 71.49933MHz
AIN2 = -7.0dBFS
SFDRTT = 77.9dBc
IMD = -76.4dBc
IM3 = -77.5dBc
fIN1
fIN2
fIN1 + fIN2
2 x fIN1 + 3 x fIN22 x fIN2 + fIN1
2 x fIN1 + fIN2
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
FREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX12555 toc07
fCLK = 95MHz
fIN1 = 172.4949MHz
AIN1 = -7.0dBFS
fIN2 = 177.493MHz
AIN2 = -7.0dBFS
SFDRTT = 74.6dBc
IMD = -73.6dBc
IM3 = -74.7dBc
fIN1
fIN2
fIN1 + fIN2
2 x fIN1 + fIN22 x fIN2 + fIN1819240961228816384
INTEGRAL NONLINEARITYMAX12555 toc08
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX12555 toc09
DIGITAL OUTPUT CODE
DNL (LSB)
Typical Operating Characteristics(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADC456585105125
SNR, SINAD
vs. SAMPLING RATEMAX12555 toc10
fCLK (MHz)
SNR, SINAD (dB)
fIN = 70MHz
SNR
SINAD
SFDR, -THD
vs. SAMPLING RATE
MAX12555 toc11
fCLK (MHz)
SFDR, -THD (dBc)
fIN = 70MHz
SFDR
-THD
POWER DISSIPATION
vs. SAMPLING RATE
MAX12555 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fIN = 70MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER456585105125
SNR, SINAD
vs. SAMPLING RATEMAX12555 toc13
fCLK (MHz)
SNR, SINAD (dB)
fIN = 175MHz
SNR
SINAD
SFDR, -THD
vs. SAMPLING RATE
MAX12555 toc14
fCLK (MHz)
SFDR, -THD (dBc)
fIN = 175MHz
SFDR
-THD
POWER DISSIPATION
vs. SAMPLING RATE
MAX12555 toc15
fCLK (MHz)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER10020030050150250350400
SNR, SINAD
vs. ANALOG INPUT FREQUENCYMAX12555 toc16
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
SNR
SINAD
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
MAX12555 toc17
ANALOG INPUT FREQUENCY (MHz)
SFDR, -THD (dBc)
SFDR
-THD200
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
MAX12555 toc18
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADCSNR, SINAD
vs. ANALOG INPUT AMPLITUDE
MAX12555 toc19
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD (dB)
SNR
SINAD
fIN = 175MHz
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
MAX12555 toc20
ANALOG INPUT AMPLITUDE (dBFS)
SFDR, -THD (dBc)
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
MAX12555 toc21
ANALOG INPUT AMPLITUDE (dBFS)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
SNR, SINAD
vs. ANALOG SUPPLY VOLTAGE
MAX12555 toc22
AVDD (V)
SNR, SINAD (dB)
SNR
SINAD
fIN = 175MHz
SFDR, -THD
vs. ANALOG SUPPLY VOLTAGE
MAX12555 toc23
AVDD (V)
SFDR, -THD (dBc)
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGE
MAX12555 toc24
AVDD (V)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
SNR, SINAD
vs. DIGITAL SUPPLY VOLTAGE
MAX12555 toc25
OVDD (V)
SNR, SINAD (dB)
SNR
SINAD
fIN = 175MHz
SFDR, -THD
vs. DIGITAL SUPPLY VOLTAGE
MAX12555 toc26
OVDD (V)
SFDR, -THD (dBc)
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. DIGITAL SUPPLY VOLTAGE
MAX12555 toc27
OVDD (V)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADC
SNR, SINAD vs. TEMPERATUREMAX12555 toc28
TEMPERATURE (°C)
SNR, SINAD (dB)3510-15
SNR
SINAD
fIN = 175MHz
SFDR, -THD vs. TEMPERATURE
MAX12555 toc29
SFDR, -THD (dBc)
TEMPERATURE (°C)3510-15-4085
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. TEMPERATURE
MAX12555 toc30
ANALOG POWER DISSIPATION (mW)
TEMPERATURE (°C)3510-15-4085
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
OFFSET ERROR vs. TEMPERATUREMAX12555 toc31
OFFSET ERROR (%FS)
TEMPERATURE (°C)3510-15-4085
VREFIN = 2.048V
GAIN ERROR vs. TEMPERATURE
MAX12555 toc32
GAIN ERROR (%FS)
TEMPERATURE (°C)3510-15-4085
VREFIN = 2.048V
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADC
REFERENCE OUTPUT VOLTAGE
LOAD REGULATIONMAX12555 toc33
IREFOUT SINK CURRENT (mA)
REFOUT
(V)-0.5-1.0-1.5
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCEMAX12555 toc34
IREFOUT SINK CURRENT (mA)
REFOUT
(V)-1.0-2.0
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATUREMAX12555 toc35
TEMPERATURE (°C)
REFOUT
(V)3510-15
REFP, COM, REFN
LOAD REGULATION
MAX12555 toc36
SINK CURRENT (mA)
VOLTAGE (V)0-1
VREFP
VCOMVREFN
INTERNAL REFERENCE
MODE AND BUFFERED EXTERNAL
REFERENCE MODE
REFP, COM, REFN
SHORT-CIRCUIT PERFORMANCEMAX12555 toc37
SINK CURRENT (mA)
VOLTAGE (V)0-4
VREFP
VCOM
VREFN
INTERNAL REFERENCE
MODE AND BUFFERED
EXTERNAL REFERENCE MODE
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK ≈95MHz (50% duty cycle, 1.4VP-Psquare wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADC
PINNAMEFUNCTIONREFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFN to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on theopposite side of the PC board and connected to the MAX12555 through a via.
4, 7, 16,GNDGround. Connect all ground pins and EP together.INPPositive Analog InputINNNegative Analog InputDCEDuty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.CLKTYPClock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OVDD or VDD to define the differential clock input.
12–15, 36VDDAnalog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34OVDDOutput-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).D13CMOS Digital Output Bit 13 (MSB)D12CMOS Digital Output Bit 12D11CMOS Digital Output Bit 11D10CMOS Digital Output Bit 10D9CMOS Digital Output Bit 9D8CMOS Digital Output Bit 8D7CMOS Digital Output Bit 7D6CMOS Digital Output Bit 6D5CMOS Digital Output Bit 5
Pin Description
MAX12555
14-Bit, 95Msps, 3.3V ADC
PINNAMEFUNCTIOND4CMOS Digital Output Bit 4D3CMOS Digital Output Bit 3D2CMOS Digital Output Bit 2D1CMOS Digital Output Bit 1D0CMOS Digital Output Bit 0 (LSB)DAV
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX12555 output data into an
external back-end digital circuit.PDPower-Down Input. Force PD high for power-down mode. Force PD low for normal operation.REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.REFIN
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes, VREFP - VREFN = VREFIN x 3/4. For unbuffered external
reference mode operation, connect REFIN to GND.G/TOutput-Format-Select Input. Connect G/T to GND for the two’s-complement digital output format.
Connect G/T to OVDD or VDD for the Gray code digital output format.EP
Exposed Paddle. The MAX12555 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
Pin Description (continued)MAX12555Σ
DIGITAL ERROR CORRECTION
FLASH
ADC
T/H
DAC
STAGE 2
D13–D0
INP
INN
STAGE 1T/HSTAGE 9STAGE 10
END OF PIPE
OUTPUT
DRIVERS
D13–D0
Figure 1. Pipeline Architecture—Stage Blocks
MAX12555
Detailed DescriptionThe MAX12555 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output, the total clock-cycle latency is 8.0
clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12555 functional diagram.
Input Track-and-Hold (T/H) CircuitFigure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of VDD / 2 ±0.5V.
The MAX12555 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3) allowing
the analog input signal to be stored as a charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX12555 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (VDD / 2). The MAX12555 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Reference Output (REFOUT) An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12555. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX12555 or when PD transitions from
high to low. REFOUT has approximately 17kΩto GND
when the MAX12555 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUTto be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
14-Bit, 95Msps, 3.3V ADCMAX12555
INP
INN
14-BIT
PIPELINE
ADCDEC
REFERENCE
SYSTEMCOM
REFOUT
REFN
REFP
OVDD
DAVOUTPUT
DRIVERS
D13–D0
DOR
REFIN
T/H
POWER CONTROL
AND
BIAS CIRCUITS
CLKPCLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKN
CLKTYP
VDD
GNDDCE
G/T
Figure 2. Simplified Functional Diagram
MAX12555
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INP
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
4.5pF
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INN
*CSAMPLE
4.5pF
RSAMPLE =1
fCLK x CSAMPLE
Figure 3. Simplified Input T/H Circuit
