MAX1249ACEE+ ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial, 10-Bit ADCs in QSOP-16FeaturesThe MAX1248/MAX1249 10-bit data-acquisition sys-♦ 4-Channel Single-Ended or 2-Channel tems ..
MAX1249AEEE ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16FeaturesThe MAX1248/MAX1249 10-bit data-acquisition sys-' 4-Channel Single-Ended or 2-Channel tems ..
MAX1249AEEE ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16FeaturesThe MAX1248/MAX1249 10-bit data-acquisition sys-' 4-Channel Single-Ended or 2-Channel tems ..
MAX1249AEEE+ ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial, 10-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0V; f = 2.0MHz; external clock (50% duty cycl ..
MAX1249AEEE+T ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial, 10-Bit ADCs in QSOP-16MAX1248/MAX124919-1072; Rev 2; 5/98+2.7V to +5.25V, Low -Pow er, 4-Channel,Serial 10-Bit ADCs in QS ..
MAX1249BCEE ,+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16MAX1248/MAX124919-1072; Rev 2; 5/98+2.7V to +5.25V, Low-Power, 4-Channel,Serial 10-Bit ADCs in QSOP ..
MAX3675ECJ ,622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierApplications+Denotes a lead(Pb)-free/RoHS-compliant package.SDH/SONET Receivers and RegeneratorsSDH ..
MAX3679CTJ+ , 3.3V, Low-Jitter Crystal to LVPECL Clock Generator
MAX367CWN ,Signal-Line Circuit ProtectorsGeneral Description ________
MAX367EWN ,Signal-Line Circuit ProtectorsFeaturesThe MAX366 and MAX367 are multiple, two-terminal circuit' ±40V Overvoltage Protectionprotec ..
MAX1248BCEE+-MAX1249ACEE+-MAX1249AEEE+-MAX1249AEEE+T
+2.7V to +5.25V, Low-Power, 4-Channel, Serial, 10-Bit ADCs in QSOP-16
_______________General DescriptionThe MAX1248/MAX1249 10-bit data-acquisition sys-
tems combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate fromsingle +2.7V to +5.25V supply, and their analog
inputs are software configurable for unipolar/bipolar
and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection
to TMS320-family digital signal processors. The
MAX1248/MAX1249 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions.
The MAX1248 has an internal 2.5V reference, while the
MAX1249 requires an external reference. Both parts
have a reference-buffer amplifier with a ±1.5% voltage
adjustment range.
These devices provide a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX1248/MAX1249, and the quick
turn-on time allows them to be shut down between all
conversions. This technique can cut supply current to
under 60μA at reduced sampling rates.
The MAX1248/MAX1249 are available in a 16-pin DIP
and a very small QSOP that occupies the same board
area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX148/MAX149 data sheet.
________________________ApplicationsPortable Data LoggingData Acquisition
Medical InstrumentsBattery-Powered Instruments
Pen DigitizersSystem Supervision
____________________________Features4-Channel Single-Ended or 2-Channel
Differential InputsSingle +2.7V to +5.25V OperationInternal 2.5V Reference (MAX1248)Low Power:1.2mA (133ksps, +3V supply)
54μA (1ksps, +3V supply)
1μA (power-down mode)SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs16-Pin QSOP Package (same area as 8-pin SO).7V to +5.25V, Low-Power, 4-Channel,rial 10-Bit ADCs in QSOP-1619-1072; Rev 2; 5/98
PART†
MAX1248ACPEMAX1248BCPE
MAX1248ACEE0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGEPIN-PACKAGE16 Plastic DIP
16 Plastic DIP
16 QSOP
_____________Ordering Information
Ordering Information continued at end of data sheet.†Contact factory for availability of alternate surface-mount
packages.
Pin Configuration appears at end of data sheet.MAX1248BCEE0°C to +70°C16 QSOP
INL
(LSB)±1/2
±1/2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIREis a trademark of National Semiconductor Corp.
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
AGND
DGND
VDD
CH3
4.7μF
0.01μF0.1μF
CH0
0V TO
+2.5VANALOG
INPUTSMAX1248
CPU
+3V
VREF
REFADJ
__________Typical Operating Circuit
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7μF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500Vapplied to VREF pin; TA= TMINto TMAX,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND..............................................-0.3V to +6V
AGND to DGND....................................................-0.3V to +0.3V
CH0–CH3, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND............................................-0.3V to +6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C).........842mW
QSOP (derate 8.30mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX1248_C_E/MAX1249_C_E..........................0°C to +70°C
MAX1248_E_E/MAX1249_E_E........................-40°C to +85°C
MAX1248_MJE/MAX1249_MJE....................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C3565tCONVConversion Time (Note 5)
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth-75Channel-to-Channel Crosstalk70SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion66SINADSignal-to-Noise + Distortion Ratio
LSB±0.05Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits10Resolution
Offset Error
LSB±1.0INLRelative Accuracy (Note 2)
LSB±1DNLLSB±2
UNITSMINTYPMAXSYMBOLPARAMETERExternal clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN= VDD
Internal clock, SHDN= FLOAT
MAX124_A
-3dB rolloff
65kHz, 2.500Vp-p (Note 4)
Up to the 5th harmonic
MAX124_A
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
CONDITIONSDifferential Nonlinearity30Aperture Delay
MHz1.8SHDN= FLOAT<50Aperture Jitter
MHz0.12.01.5tACQTrack/Hold Acquisition Time
0.225Internal Clock FrequencySHDN= VDD2.0External Clock Frequency Data transfer only
LSBGain Error (Note 3)±2MAX124_B
DC ACCURACY(Note 1)
DYNAMICSPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
.7V to +5.25V, Low-Power, 4-Channerial 10-Bit ADCs in QSOP-16Multiplexer Leakage Current15CINDIN, SCLK, CSInput Capacitance±0.01±1IINDIN, SCLK, CSInput Leakage0.2VHYSTDIN, SCLK, CSInput Hysteresis0.8VILDIN, SCLK, CSInput Low Voltage
2.00.0110Shutdown VREF Input Current1825VREF Input Resistance100150VREF Input Current1.0VDD+
50mV
VREF Input Voltage Range
(Note 9)16Input Capacitance
0 to VREFV±VREF/ 2
Input Voltage Range, Single-
Ended and Differential (Note 6)±0.01±1
UNITSMINTYPMAXSYMBOLPARAMETER(Note 10)
VIN= 0V or VDD
Unipolar, COM = 0V
VDD ≤3.6V
VREF = 2.500V
Bipolar, COM = VREF / 2
On/off leakage current, VCH_= 0V or VDD
CONDITIONS±4.0ISSHDNInput Current0.4VSLSHDNInput Low VoltageVDD- 0.4VSHSHDNInput High Voltage
SHDN= 0VorVDD
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7μF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500Vapplied to VREF pin; TA= TMINto TMAX,
unless otherwise noted.)3.0VIHDIN, SCLK, CSInput High VoltageVDD> 3.6V2.4702.5002.530VREFOutput VoltageTA= +25°C (Note 7)30VREFShort-Circuit Current
ppm/°C±30VREFTemperature CoefficientMAX12480Capacitive Bypass at VREFInternal compensation mode
4.7External compensation mode0.35Load Regulation (Note 8)0mA to 0.2mA output load0.01Capacitive Bypass at REFADJ
±1.5REFADJAdjustment Range%VDD -
0.5REFADJ Buffer-Disable Threshold
Capacitive Bypass at VREFInternal compensation mode0μFExternal compensation mode4.7
Reference-Buffer GainMAX12482.06V/VMAX12492.00
REFADJ Input CurrentMAX1248±50μAMAX1249±101.1VDD- 1.1VSMSHDNInput Mid Voltage
ANALOG/COM INPUTS
EXTERNALREFERENCE ATVREF (Buffer disabled)
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
EXTERNALREFERENCE AT REFADJ
INTERNALREFERENCE (MAX1248 only, reference buffer enabled)
VDD= 5.25V
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16Operating mode,
full-scale input (Note 11)70Fast power-down (MAX1248)±100SHDNMaximum Allowed
Leakage, Mid InputVDD / 2VFLTSHDNVoltage, Floating
SHDN= FLOAT
SHDN= FLOAT
UNITSMINTYPMAXSYMBOLPARAMETER1.210
IDD
CONDITIONSPositive Supply Current1.63.0±0.01±10ILThree-State Leakage CurrentVDD- 0.5VOHOutput Voltage High0.8VOLOutput Voltage Low0.42.705.25VDDPositive Supply Voltage15COUTThree-State Output Capacitance
Full power-down= VDD(Note 10)= VDD
ISOURCE= 0.5mA
ISINK= 16mA
ISINK= 5mA
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7μF capacitor at VREF pin; MAX1249—external reference; VREF = 2.500Vapplied to VREF pin, TA= TMINto TMAX,
unless otherwise noted.)±0.3PSRSupply Rejection (Note 12)VDD= 2.7V to 5.25V, full-scale input,
external reference = 2.500V
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTSIDD
VDD= 5.25V
VDD= 3.6V
VDD= 5.25V
VDD= 3.6V
.7V to +5.25V, Low-Power, 4-Channerial 10-Bit ADCs in QSOP-16TIMING CHARACTERISTICS(VDD= +2.7V to +5.25V, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX1248—internal reference, offset nulled; MAX1249—external reference (VREF = +2.500V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7Sample tested to 0.1% AQL.
Note 8:External load should not change during conversion for specified accuracy.
Note 9:ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Note 10Guaranteed by design. Not subject to production testing.
Note 11:The MAX1249 typically draws 400μA less than the values shown.
Note 12:Measured as |VFS(2.7V) - VFS(5.25V)|.
DIN to SCLK Setup240tSTRCSRise to SSTRBOutput Disable240tSDVCSFall to SSTRBOutput Enable
240tSSTRBSCLKFall to SSTRBns
200tCLSCLK Pulse Width Low200SCLK Pulse Width High0CSto SCLK Rise Hold100tCSSCSto SCLK Rise Setup240tTRCSRise to Output Disable240tDVCSFall to Output Enable
tDOSCLK Fall to Output Data Valid0tDHDIN to SCLK Hold1.5tACQAcquisition TimetSCKSSTRB Rise to SCLK Rise100tDS
UNITSMINTYPMAXSYMBOLPARAMETERInternal clock mode only (Note 10)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS20240Figure 1
tCSH
tCH
MAX124__C/E
MAX124__M200
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
(m
AX1248-01RL = ∞
CODE = 10101010
MAX1249
MAX1248
CLOAD = 20pF
CLOAD = 50pF
CLOAD = 50pF
CLOAD = 20pF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VDD (V)
(μ
AX1248/49-02FULL POWER-DOWN
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
(V
AX1248-09
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
(m
AX1247-04
MAX1249
MAX1248
RLOAD = ∞
CODE = 1010101000
INTERGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1248-07
SUPPLY VOLTAGE (V)
(L
MAX1248
MAX1249
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
(μ
AX1248-05
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
, V
AX1248-06
VDD = 2.7V
VDD = 3.6V
VDD = 5.25V
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1248-08
TEMPERATURE (°C)
(L
VDD = 2.7V
MAX1248
MAX1249
INTEGRAL NONLINEARITY
vs. CODE
MAX1248-09
(L
CODE
__________________________________________Typical Operating Characteristics
(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA= +25°C, unless otherwise noted.)
.7V to +5.25V, Low-Power, 4-Channerial 10-Bit ADCs in QSOP-16NAMEFUNCTIONVDDPositive Supply Voltage
2–5CH0–CH3Sampling Analog Inputs
PINCOMGround reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.SHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling SHDNhigh puts the reference-buffer amplifier in internal compen-
sation mode. Letting SHDNfloat puts the reference-buffer amplifier in external compensation mode.DOUTSerial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CSis high.DGNDDigital GroundREFADJInput to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.SCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)CSActive-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT is
high impedance.DINSerial Data Input. Data is clocked in at SCLK’s rising edge.SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CSis high (external
clock mode).
______________________________________________________________Pin DescriptionVDD
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOLVDD
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable TimeAGNDAnalog Ground
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16_______________Detailed DescriptionThe MAX1248/MAX1249 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serialinterface provides easy interface to microproces-
sors (μPs). Figure 3 is a block diagram of the
MAX1248/MAX1249.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1248/MAX1249 correspond to
the codes for CH2–CH5 in the eight-channel
(MAX148/MAX149) versions.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1μF capacitor from IN-(the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) -(VIN-)] from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
INPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX1248)
T/HANALOG
INPUT
MUX
SAR
ADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20kA ≈ 2.06*
*A ≈ 2.00 (MAX1249)
CH35
CH24
CH13
CH02
MAX1248
MAX1249
SHDN
Figure 3.Block Diagram
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
CHOLD
HOLD
CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4.Equivalent Input Circuit
.7V to +5.25V, Low-Power, 4-Channerial 10-Bit ADCs in QSOP-16the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ= 7.6 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5μs. Note
that source impedances below 3kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01μF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand AGND, allow the channel input pins to swing
from AGND -0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 4mA.
How to Start a Conversionconversion is started by clocking a control byte into
DIN. With CSlow, each rising edge on SCLK clocks a bit
from DIN into the MAX1248/MAX1249’s internal shift reg-
ister. After CSfalls, the first arriving logic “1” bit defines
the control byte’s MSB. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN with
no effect. Table 1 shows the control-byte format.
The MAX1248/MAX1249 are compatible with SPI/QSPI
and MICROWIREdevices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit,the sim-
Table 1.Control-Byte Format
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BITNAMEDESCRIPTION7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the four channels are used for the conversion (Tables 2 and 3).SEL1SEL0UNI/BIP1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.SGL/DIF1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode0Full power-down1Fast power-down (MAX1248 only)0Internal clock mode1 External clock mode
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
10-bit conversion result). See Figure 19 for MAX1248/
MAX1249 QSPI connections.
Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two sub-bits, and three trailing
zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120μs.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 16). For bipolar inputs, the output is two’s com-
plement (Figure 17). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock ModesThe MAX1248/MAX1249 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1248/MAX1249. The T/H acquires the input signal
as the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 6–9 show the timing characteristics
common to both modes.
External ClockIn external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 10 SCLK falling edges (Figure 5).
SSTRB and DOUT go into a high-impedance state when
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16
SEL2SEL1SEL0CH0CH1CH2CH3COM01+–
01+–
10+–
10+–
Table 2.Channel Selection in Single-Ended Mode (SGL/DDIIFF
= 1)
SEL2SEL1SEL0CH0CH1CH2CH301+–
10+–
01–+
10–+
Table 3.Channel Selection in Differential Mode (SGL/DDIIFF
= 0)
.7V to +5.25V, Low-Power, 4-Channerial 10-Bit ADCs in QSOP-16goes high; after the next CSfalling edge, SSTRB willoutput a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120μs.
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDOtTR
tCSH
Figure 6.Detailed Serial-Interface Timing
SSTRB
SCLK
DIN
DOUT4812162024
START
SEL2SEL1SEL0UNI/
BIP
SGL/
DIFPD1PD0MSBB8B7B6B5B4B3B2B1B0
LSBS1S0
ACQUISITION
(fCLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1RB2RB3
1.5µs
Figure 5.24-Clock External Clock Mode Conversion Timing (MICROWIREand SPI-Compatible, QSPI-Compatible with fSCLK ≤2MHz)
.7V to +5.25V, Low-Power, 4-Channel, rial 10-Bit ADCs in QSOP-16Internal Clock
In internal clock mode, the MAX1248/MAX1249 gener-
ate their own conversion clocks internally. This frees the
μP from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5μs (SHDN= FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CSdoes
not need to be held low once a conversion is started.
Pulling CShigh prevents data from being clocked into
the MAX1248/MAX1249 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CSgoes high.
Figure 9 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1248/MAX1249 at clock rates exceeding
2.0MHz if the minimum acquisition time, tACQ, is kept
above 1.5μs.
SSTRB
SCLK
DIN
DOUT4812182024
START
SEL2SEL1SEL0UNI/
BIP
SGL/
DIFPD1PD0
MSBB8B7B0
LSBS1S0
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = FLOAT)35679101119212223
tCONV
ACQUISITION
(fSCLK = 2MHz)
IDLEA/D STATE1.5µs
Figure 8.Internal Clock Mode Timing
• • •
• • •• • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
tSSTRB
• • •• • •• •
Figure 7.External Clock Mode SSTRBDetailed Timing
