MAX1245ACAP ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCFeaturesThe MAX1245 12-bit data-acquisition system combines' Single +2.375V to +3.3V Operationan 8- ..
MAX1245BCAP ,+2.375V, low-power, 8-channel, serial 12-bit ADC .FeaturesThe MAX1245 12-bit data-acquisition system combines' Single +2.375V to +3.3V Operationan 8- ..
MAX1245BCPP ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCApplicationsPortable Data Logging Medical Instruments___________________Pin ConfigurationBattery-Po ..
MAX1245BCPP ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCELECTRICAL CHARACTERISTICS(V = +2.375V to +3.3V, COM = 0V, f = 1.5MHz, external clock (50% duty cyc ..
MAX1245BCPP+ ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCFeaturesThe MAX1245 12-bit data-acquisition system combines♦ Single +2.375V to +3.3V Operationan 8- ..
MAX1246ACPE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f ..
MAX365ESE ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX3663ETG ,+3.3 V, 622 Mbps SDH/SONET laser driver with current monitor and APCApplicationsTypical Application Circuit+3.3V +3.3VLASERVCCR-124Ω124ΩR+6.3Ω20ΩDATA+ROUT- D5ΩMAX3693P ..
MAX3664E/D ,622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONETapplications consumes only' 55nA Input-Referred NoiseRMS85mW. Operating from a single +3.3V supply, ..
MAX3664ESA ,622Mbps / Ultra-Low-Power / 3.3V Transimpedance Preamplifier for SDH/SONETapplications consumes only' 55nA Input-Referred NoiseRMS85mW. Operating from a single +3.3V supply, ..
MAX3664EUA ,622Mbps, ultra-low-power, 3.3V transimpedance preamplifier for SDH/SONET.applications consumes only' 55nA Input-Referred NoiseRMS85mW. Operating from a single +3.3V supply, ..
MAX3667E/D ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlApplications622Mbps SDH/SONET Access NodesPin Configuration appears at end of data sheet.Laser Driv ..
MAX1245ACAP-MAX1245BCPP
+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC
& the latest literature: http://,
________________General DescriptionThe MAX1245 12-bit data-acquisition system combines
an 8-channel multiplexer, high-bandwidth track/hold, and
serial interface with high conversion speed and ultra-low
power consumption. It operates from a single +2.375V to
+3.3V supply, and its analog inputs are software config-
urable for unipolar/bipolar and single-ended/differential
operation.
The 4-wire serial interface directly connects to SPI™,
QSPI™, and Microwire™ devices without external logic.
A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1245
works with an external reference, and uses either the
internal clock or an external serial-interface clock to
perform successive-approximation analog-to-digital
conversions.
This device provides a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface powers up
the MAX1245, and the quick turn-on time allows it to be
shut down between conversions. This technique can
cut supply current to under 10µA at reduced sampling
rates.
The MAX1245 is available in a 20-pin DIP package and
an SSOP that occupies 30% less area than an 8-pin DIP.
For supply voltages from +2.7V to +5.25V, use the pin-
compatible MAX147.
________________________ApplicationsPortable Data LoggingMedical Instruments
Battery-Powered InstrumentsData Acquisition
____________________________FeaturesSingle +2.375V to +3.3V Operation8-Channel Single-Ended or 4-Channel
Differential Analog InputsLow Power:0.8mA (100ksps)
10µA (1ksps)
1µA (power-down mode)Internal Track/Hold, 100kHz Sampling RateSPI/QSPI/Microwire/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
________________________________________________________________Maxim Integrated Products1
___________________Pin Configuration
___________Typical Operating Circuit19-1066; Rev 0; 6/96
SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.375V to +3.3V, COM = 0V, fCLK= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMINto TMAX,unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND..............................................-0.3V to +6V
AGND to DGND....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND............................................-0.3V to +6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX1245_C_P...................................................0°C to +70°C
MAX1245_E_P................................................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.375V to +3.3V, COM = 0V, fCLK= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMINto TMAX,unless otherwise noted.)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC_______________________________________________________________________________________
TIMING CHARACTERISTICS(VDD= +2.375V to +3.3V, COM= 0V, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= +2.375V; COM = 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:External reference (VREF = +2.048V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Guaranteed by design. Not subject to production testing.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Measured as |VFS(2.375V) - VFS(3.3V)|.
__________________________________________Typical Operating Characteristics(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VDD (V)
IDD
(mA)
3.3753.1252.625MAX1245-01
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
IDD
(mA)145120-54595
MAX1245-02
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
VDD (V)
INL (LSB)
MAX1245-03
2.3752.8753.3753.1252.625
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________5INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (˚C)
INL (LSB)-57095145120
MAX1245-04
OFFSET vs. SUPPLY VOLTAGE
VDD (V)
OFFSET (LSB)
MAX1245-05
OFFSET vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET (LSB)-57014512095
MAX1245-06
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
OFFSET MATCHING (LSB)
MAX1245-07
GAIN ERROR
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN ERROR (LSB)451201459570
MAX1245-10
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)-57014512095
MAX1245-08
GAIN ERROR
vs. SUPPLY VOLTAGE
VDD (V)
GAIN ERROR (LSB)
MAX1245-09
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
GAIN MATCHING (LSB)
MAX1245-11
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN MATCHING (LSB)451451209570
MAX1245-12
____________________________Typical Operating Characteristics (continued)(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC_______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
CONVERSIONS PER CHANNEL PER SECOND (Hz)
(µA)11k10k100100k
MAX1245-13
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX1245-14
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.0
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________7
______________________________________________________________Pin DescriptionFigure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable Time
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC_______________________________________________________________________________________
_______________Detailed DescriptionThe MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN-is switched to COM. In differential
mode, IN+ and IN-are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN-(the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acqui-
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on CHOLDas a
sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLDfrom the positive input, IN+, to the
negative input, IN-(In single-ended mode, IN-is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) -
(VIN-)] from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ= 9 x (RS+ RIN) x 16pF
Figure 3.Block Diagram
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________9Figure 5.Quick-Look Circuit
where RIN= 12kΩ, RS= the source impedance of the
input signal, and tACQis never less than 2.0µs. Note
that source impedances below 1kΩdo not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from AGND -0.3V to VDD+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quick LookTo quickly evaluate the MAX1245’s analog perfor-
mance, use the circuit of Figure 5. The MAX1245
requires a control byte to be written to DIN before each
conversion. Tying DIN to VDDfeeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the 12-bit conversion result is
shifted out of DOUT. Varying the analog input to CH7
alters the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a ConversionA conversion is started by clocking a control byte into
DIN. With CSlow, each rising edge on SCLK clocks a
bit from DIN into the MAX1245’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
The MAX1245 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit,the simplest soft-
ware interface requires only three 8-bit transfers to
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
