MAX1243AESA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8ApplicationsOrdering Information continued at end of data sheet.Note: Order the MAX1242A in place o ..
MAX1243BCSA ,+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8ApplicationsOrdering Information continued at end of data sheet.Portable Data Logging Process Contr ..
MAX1243BCSA ,+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8FeaturesThe MAX1242/MAX1243 are low-power, 10-bit analog-' +2.7V to +5.25V Single-Supply Operationt ..
MAX1243BCSA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8ELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; 73ksps; f = 2.1MHz (50% duty cycle); MAX1242—4.7µF ..
MAX1243BESA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8FeaturesThe MAX1242/MAX1243 are low-power, 10-bit analog- ♦ +2.7V to +5.25V Single-Supply Operation ..
MAX1245ACAP ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCFeaturesThe MAX1245 12-bit data-acquisition system combines' Single +2.375V to +3.3V Operationan 8- ..
MAX365CPE ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365CPE+ ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX365CSE ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365CSE+ ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365EPE ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX364/MAX365 are precision, quad, single-pole ' Low On Resistance: < 45Ω Typical (85Ω ..
MAX365ESE ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX1243AESA+-MAX1243BCSA+-MAX1243BESA+
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
__________________General DescriptionThe MAX1242/MAX1243 are low-power, 10-bit analog-
to-digital converters (ADCs) available in 8-pin pack-
ages. They operate with a single +2.7V to +5.25V
supply and feature a 7.5µs successive-approximation
ADC, a fast track/hold (1.5µs), an on-chip clock, and a
high-speed, 3-wire serial interface.
Power consumption is only 3mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1242 has an internal 2.5V reference, while the
MAX1243 requires an external reference. The MAX1243
accepts signals from 0V to VREF, and the reference
input range includes the positive supply rail. An exter-
nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI, QSPI™, and
MICROWIRE®.
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
acquisition applications, or for other circuits with
demanding power consumption and space require-
ments. The MAX1242/MAX1243 are available in 8-pin
PDIP and SO packages.
ApplicationsPortable Data LoggingProcess Control Monitoring
Test EquipmentTemperature Measurement
Isolated Data Acquisition
________________________________Features+2.7V to +5.25V Single-Supply Operation10-Bit ResolutionInternal 2.5V Reference (MAX1242)Small Footprint: 8-Pin DIP and SO PackagesLow Power:3.7mW (73ksps, MAX1242)
3mW (73ksps, MAX1243)
66µW (1ksps, MAX1243)
5µW (Power-Down Mode)Internal Track/HoldSPI/QSPI™/MICROWIRE®3-Wire Serial InterfacePin-Compatible 12-Bit Upgrades: MAX1240/MAX1241
Ordering Information continued at end of data sheet.
Note:Order the MAX1242A in place of the MAX1242C. Order the
MAX1242B in place of the MAX1242D.
+Denotes a lead(Pb)-free/RoHS-compliant package.
________________Functional DiagramAINT/H
DOUT6
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC
2.5V
REFERENCE
MAX1242 ONLY
INT
CLOCK
10-BIT
SAR
REF4
SHDN
SCLK
MAX1242
MAX1243
VDD
GND
PARTTEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1242ACPA+0°C to +70°C8 PDIP±1/2
MAX1242BCPA+0°C to +70°C8 PDIP±1
MAX1242ACSA+0°C to +70°C8 SO±1/2
MAX1242BCSA+0°C to +70°C8 SO±1
MAX1242AEPA+- 40°C to + 85°C 8 PDIP±1/2
TOP VIEW
SCLK
DOUT
GNDREF
SHDN
AIN
VDD
PDIP/SOMAX1242
MAX1243
Pin Configuration
_________________Ordering Information
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8Gain Temperature Coefficient
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V; 73ksps; fSCLK= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; VREF= 2.5V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
VDDto GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 9.09mW/°C above +70°C).....................727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
Operating Temperature Ranges
MAX1242/MAX1243_C_A..................................0°C to +70°C
MAX1242/MAX1243_E_ A..............................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)......................................+260°C
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ANALOG INPUT
CONVERSION RATE
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps, fSCLK= 2.1MHz)
DC ACCURACY(Note 1)
MAX124_B±2
Input Voltage Range0VREFV
Input Capacitance
Aperture Jitter<50pspF
MAX124_A
MAX124_B
MAX124_A
Aperture DelaytAP30nsFigure 9
Track/Hold Acquisition TimetACQ1.5µs
Throughput Rate73kspsfSCLK= 2.1MHz
Conversion Time
PARAMETERSYMBOLMINTYPMAXUNITSOffset ErrorLSB
Differential NonlinearityDNL±1LSB
±1.0
Gain Error (Note 3)±1
Resolution10Bits
Relative Accuracy (Note 2)±0.5LSB
tCONV5.57.5µs
Small-Signal Bandwidth
Signal-to-Noise Plus
Distortion RatioSINAD66dB
2.25MHz
Full-Power Bandwidth
Total Harmonic DistortionTHD-70dB
-3dB rolloff
MHz
CONDITIONSSpurious-Free Dynamic Range
ppm/°C
No missing codes over temperature
MAX124_B
±0.25
SFDR70
Up to the 5th harmonic
MAX124_A
LSB
DC ACCURACY(Note1)
CONVERSION RATE
ANALOG INPUT
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5VP-P, 73ksps, fSCLK=2.1MHz)
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V; 73ksps; fSCLK= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; VREF= 2.5V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
Capacitive Bypass at REF4.7µF
Load Regulation (Note 5)0.35mV0mA to 0.2mA output load
REF Temperature Coefficient±30ppm/°CMAX1242
REF Short-Circuit Current30mA
REF Output Voltage2.4702.5002.530VTA= +25°C (Note 4)
Power-Supply Rejection (Note 7)PSRVDD= VDD(min)to VDD(max), full-scale input
1.00VDD+
50mV
Supply CurrentIDD
VDD> 3.6V
ISINK= 16mA
Output Voltage High
SCLK, CSInput High VoltageVIH2.0V
SCLK, CSInput Low Voltage
Capacitive Bypass at REF0.1µF
VIL0.8
VDD≤3.6V
VOHVDD- 0.5V
Three-State Leakage CurrentIL±0.01±10
ISOURCE= 0.5mACS= VDD
Three-State Output CapacitanceCOUT15pFCS= VDD (Note 6)
Output Voltage LowVOL0.4V
PARAMETERSYMBOLMINTYPMAXUNITSISINK= 5mA
SHDNInput Mid VoltageVSM1.1VDD- 1.1V
SHDNVoltage, OpenVFLTVDD/ 2V
SHDNMax Allowed Leakage,
Mid Input±100
SHDN= openSHDN= open
SCLK, CSInput Capacitance
Input Voltage RangeV
CIN15pF
SHDNInput High VoltageVSHVDD- 0.4
(Note 6)
SHDNInput Low VoltageVSL0.4V
Input Resistance
SHDNInput Current±4.025kΩ
REF Input Current in Shutdown VSHDN= 0V or VDD
SCLK, CSInput HysteresisVHYST
±0.0110µAVSHDN= 0V
CONDITIONSInput Current
0.2V
SCLK, CSInput LeakageIIN±0.01±1
100150µAVIN= 0V or VDD
Operating mode (MAX1242)VDD= 5.25V
Operating mode (MAX1243)VDD= 5.25V
VDD= 3.6V
Power-downVDD= 5.25V
VDD= 3.6V
Supply VoltageVDDV
VDD= 3.6V
±0.3
Operating mode (MAX1242)
EXTERNAL REFERENCE (VREF= 2.5V)
INTERNAL REFERENCE(MAX1242 only)
DIGITAL INPUTS: SCLK,CCSS,SSHHDDNN
DIGITAL OUTPUT: DOUT
POWER REQUIREMENTS
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
TIMING CHARACTERISTICS (VDD= +2.7V to +5.25V, circuit of Figure 9, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:Offset nulled.
Note 4:Sample tested to 0.1% AQL.
Note 5:External load should not change during conversion for specified accuracy.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:Measured as [VFS(VDD(min)) - VFS(VDD(max))].
Note 8:To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
DOUTDOUT
6kΩ
DGND
CLOAD = 50pFCLOAD = 50pF
6kΩ
DGND
+2.7V
b) High-Z to VOL and VOH to VOL
a) High-Z to VOH and VOL to VOH
DOUTDOUT
6kΩ
DGNDLOAD = 50pFCLOAD = 50pF
6kΩ
DGND
+2.7V
b) VOLto High-Za) VOH to High-ZFigure 1. Load Circuits for DOUT Enable Time
MAX124_ _C/E
Figure 1, CLOAD= 50pF
Figure 1,
CLOAD= 50pF= VDD(Note 8)
Figure 2, CLOAD= 50pF
CONDITIONS240tDVCSFall to Output Enable20200tDO1.5tACQAcquisition Time
SCLK Fall to Output Data Valid240tCSCSPulse Width0tSTRDOUT Rise to SCLK Rise (Note 6)50tCS0SCLK Low to CSFall Setup Time240tTRCSRise to Output Disable
MHz02.1fSCLKSCLK Clock Frequency200tCHSCLK Pulse Width High200tCLSCLK Pulse Width Low
UNITSMINTYPMAXSYMBOLPARAMETER
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX1242/43-01
RL = ∞
CODE = 1010101000
MAX1243
MAX1242
CLOAD = 20pF
CLOAD = 50pF
CLOAD = 50pFCLOAD = 20pF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
MAX1242/43-02MAX1242/MAX1243
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
MAX1242/43-03MAX1242
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1242/43-04
MAX1243
MAX1242
RLOAD = ∞
CODE = 1010101000
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1242/43-07
SUPPLY VOLTAGE (V)
INL (LSB)
MAX1242
MAX1243
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1242/43-07
SUPPLY VOLTAGE (V)
INL (LSB)
MAX1242
MAX1243
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
MAX1242/43-06
VDD = 2.7V
VDD = 5VVDD = 3.6V
MAX1242
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1242/43-08
TEMPERATURE (°C)
INL (LSB)
VDD = 2.7V
MAX1242
MAX1243
INTEGRAL NONLINEARITY
vs. CODE
MAX1242/43-09
INL (LSB)
CODE
__________________________________________Typical Operating Characteristics
(VDD= +3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CLOAD= 20pF, TA= +25°C, unless otherwise noted.)
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
_______________Detailed Description
Converter OperationThe MAX1242/MAX1243 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 10-bit out-
put. Figure 3 shows the MAX1242/MAX1243 in their
simplest configuration. The MAX1242/MAX1243 convert
input signals in the 0V to VREFrange in 9µs, including
T/H acquisition time. The MAX1242’s internal reference
is trimmed to 2.5V, while the MAX1243 requires an
external reference. Both devices accept external refer-
ence voltages from 1.0V to VDD. The serial interface
requires only three digital lines (SCLK, CS,and DOUT)
and provides an easy interface to microprocessors
(μPs).
The MAX1242/MAX1243 have two modes: normal and
shutdown. Pulling SHDNlow shuts the device down and
reduces supply current below 10µA (VDD≤3.6V), while
pullingSHDNhigh or leaving it open puts the devices
into operational mode. A conversion is initiated by
pulling CSlow.The conversion result is available at
DOUT in unipolar serial format. The serial-data stream
consists of a high bit, signaling the end of conversion
(EOC), followed by the data bits (MSB first).
Analog InputFigure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/HoldIn track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CSlow ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLDto GND. The retained charge on CHOLDrepre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of CHOLDswitches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:ACQ= 7(RS+ RIN) x 16pF
______________________________________________________________Pin DescriptionDOUTSerial-Data Output. Data changes state at SCLK’s falling edge. High impedance when CSis high.SCLKSHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1242/MAX1243 down to 15µA (max)
supply current. Both MAX1242 and MAX1243 are fully operational with either SHDNhigh or open. For
the MAX1242, pulling SHDNhigh enables the internal reference, and letting SHDNopen disables the
internal reference and allows for the use of an external reference.REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242;
bypass with a 4.7µF capacitor. External reference voltage input for MAX1243, or for MAX1242 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference. CSActive-Low Chip Select. Initiates conversions on the falling edge. When CSis high, DOUT is high
impedance.GNDAnalog and Digital GroundAINSampling Analog Input, 0V to VREFrange
NAMEFUNCTIONVDDPositive Supply Voltage: +2.7V to +5.25V
PINSerial-Clock Input. SCLK clocks data out at rates up to 2.1MHz.
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8AINTRACKINPUT
HOLD
GND
TRACK
HOLD
9kΩ
RIN
CHOLD
16pF
CSWITCH
COMPARATOR
ZERO
REF
CAPACITIVE DAC
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
SHUTDOWN
INPUT
ANALOG INPUT
0V TO VREF
+2.7V to +5.25V
VDD
AIN
SHDN
REF
SCLK
DOUT
GND
SERIAL
INTERFACE
*4.7µF, MAX1242
0.1µF, MAX1243
4.7µF0.1µF
REFERENCE
INPUT
MAX1243
MAX1242
MAX1243
Figure 3. Operational DiagramFigure 4. Equivalent Input Circuit
where RIN= 9kΩ, RS= the input signal’s source imped-
ance, and tACQis never less than 1.5µs. Source imped-
ances below 4kΩdo not significantly affect the ADC’s
AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
aliasing of unwanted high-frequency signals into the
frequency band of interest, anti-alias filtering is recom-
mended.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow the input to swing from
GND - 0.3V to VDD+ 0.3V without damage. However,
for accurate conversions near full scale, the input must
not exceed VDDby more than 50mV, or be lower than
GND by 50mV.
If the analog input exceeds 50mV beyond the supplies,
limit the input current to 2mA.
Internal Reference (MAX1242)The MAX1242 has an on-chip voltage reference
trimmed to 2.5V. The internal reference output is con-
nected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
400µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut-
down (see Using SHDNto Reduce Supply Current).
The internal reference is enabled by pulling the SHDN
pin high. Letting SHDN open disables the internal refer-
ence, which allows the use of an external reference, as
described in theExternal Referencesection.
External ReferenceThe MAX1242/MAX1243 operate with an external refer-
ence at the REF pin. To use the MAX1242 with an
external reference, disable the internal reference by let-
ting SHDNopen. Stay within the voltage range 1.0V to
VDDto achieve specified accuracy. The minimum input
impedance is 18kΩfor DC currents. During conver-
sion, the external reference must be able to deliver up
to 250µA of DC load current and have an output
impedance of 10Ωor less. The recommended mini-
mum value for the bypass capacitor is 0.1µF. If the ref-
erence has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.
