MAX1243AESA ,+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8ApplicationsOrdering Information continued at end of data sheet.Portable Data Logging Process Contr ..
MAX1243AESA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8ApplicationsOrdering Information continued at end of data sheet.Note: Order the MAX1242A in place o ..
MAX1243BCSA ,+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8ApplicationsOrdering Information continued at end of data sheet.Portable Data Logging Process Contr ..
MAX1243BCSA ,+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8FeaturesThe MAX1242/MAX1243 are low-power, 10-bit analog-' +2.7V to +5.25V Single-Supply Operationt ..
MAX1243BCSA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8ELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; 73ksps; f = 2.1MHz (50% duty cycle); MAX1242—4.7µF ..
MAX1243BESA+ ,+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8FeaturesThe MAX1242/MAX1243 are low-power, 10-bit analog- ♦ +2.7V to +5.25V Single-Supply Operation ..
MAX365CPE ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365CPE+ ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX365CSE ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365CSE+ ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX365EPE ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX364/MAX365 are precision, quad, single-pole ' Low On Resistance: < 45Ω Typical (85Ω ..
MAX365ESE ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX1242AESA-MAX1242BESA-MAX1243ACSA-MAX1243AESA-MAX1243BCSA
+2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8
__________________General DescriptionThe MAX1242/MAX1243 are low-power, 10-bit analog-
to-digital converters (ADCs) available in 8-pin pack-
ages. They operate with a single +2.7V to +5.25V
supply and feature a 7.5µs successive-approximation
ADC, a fast track/hold (1.5µs), an on-chip clock, and a
high-speed, 3-wire serial interface.
Power consumption is only 3mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1242 has an internal 2.5V reference, while the
MAX1243 requires an external reference. The MAX1243
accepts signals from 0V to VREF, and the reference
input range includes the positive supply rail. An exter-
nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and Microwire™.
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
acquisition applications, or for other circuits with
demanding power consumption and space require-
ments. The MAX1242/MAX1243 are available in 8-pin
DIP and SO packages.
ApplicationsPortable Data LoggingProcess Control Monitoring
Test EquipmentTemperature Measurement
Isolated Data Acquisition
________________________________Features+2.7V to +5.25V Single-Supply Operation10-Bit ResolutionInternal 2.5V Reference (MAX1242)Small Footprint: 8-Pin DIP and SO PackagesLow Power:3.7mW (73ksps, MAX1242)
3mW (73ksps, MAX1243)
66µW (1ksps, MAX1243)
5µW (power-down mode)Internal Track/HoldSPI™/QSPI™/Microwire™3-Wire Serial InterfacePin-Compatible 12-Bit Upgrades:
MAX1240/MAX1241
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-819-1156; Rev 2; 6/98
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
Pin Configuration
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V; 73ksps; fSCLK= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; VREF= 2.5V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
VDDto GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1242/MAX1243_C_A..................................0°C to +70°C
MAX1242/MAX1243_E_ A..............................-40°C to +85°C
MAX1242/MAX1243_MJA............................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V; 73ksps; fSCLK= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; VREF= 2.5V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
TIMING CHARACTERISTICS (VDD= +2.7V to +5.25V, circuit of Figure 9, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:Offset nulled.
Note 4:Sample tested to 0.1% AQL.
Note 5:External load should not change during conversion for specified accuracy.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:Measured as [VFS(VDD(min)) - VFS(VDD(max))].
Note 8:To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
__________________________________________Typical Operating Characteristics(VDD= +3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CLOAD= 20pF, TA= +25°C, unless otherwise noted.)
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
_______________Detailed Description
Converter OperationThe MAX1242/MAX1243 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 10-bit out-
put. Figure 3 shows the MAX1242/MAX1243 in their
simplest configuration. The MAX1242/MAX1243 convert
input signals in the 0V to VREFrange in 9µs, including
T/H acquisition time. The MAX1242’s internal reference
is trimmed to 2.5V, while the MAX1243 requires an
external reference. Both devices accept external refer-
ence voltages from 1.0V to VDD. The serial interface
requires only three digital lines (SCLK, CS,and DOUT)
and provides an easy interface to microprocessorsPs).
The MAX1242/MAX1243 have two modes: normal and
shutdown. Pulling SHDNlow shuts the device down and
reduces supply current below 10µA (VDD≤3.6V), while
pullingSHDNhigh or leaving it open puts the devices
into operational mode. A conversion is initiated by
pulling CSlow.The conversion result is available at
DOUT in unipolar serial format. The serial-data stream
consists of a high bit, signaling the end of conversion
(EOC), followed by the data bits (MSB first).
Analog InputFigure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/HoldIn track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CSlow ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLDto GND. The retained charge on CHOLDrepre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of CHOLDswitches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:
tACQ= 7(RS+ RIN) x 16pF
______________________________________________________________Pin Description
