MAX1241BCSA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOFeaturesThe MAX1240/MAX1241 are low-power, 12-bit analog- ' Single-Supply Operation:to-digital conv ..
MAX1241BCSA+T ,+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SOELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); 73ksps, f = ..
MAX1241BEPA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1240); V = +2.7V to +5.25V (MAX1241); 73ksps, f = ..
MAX1241BESA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOFeaturesThe MAX1240/MAX1241 are low-power, 12-bit analog- ' Single-Supply Operation:to-digital conv ..
MAX1241BESA+T ,+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SOFeatures♦ Single-Supply Operation:The MAX1240/MAX1241 low-power, 12-bit analog-to-+2.7V to +3.6V (M ..
MAX1241CCPA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOapplications, or for other circuits with1MAX1240ACSA 0°C to +70°C 8 SO ± /2demanding power consumpt ..
MAX364ESE ,Precision, Quad, SPST Analog SwitchesMAX364/MAX36519-0181; Rev 0; 9/93Precision, Quad, SPST Analog Switches_______________
MAX364ESE ,Precision, Quad, SPST Analog SwitchesMAX364/MAX36519-0181; Rev 0; 9/93Precision, Quad, SPST Analog Switches_______________
MAX364ESE ,Precision, Quad, SPST Analog SwitchesApplicationsMAX365CPE 0°C to +70°C 16 Plastic DIPSample-and-Hold Circuits Communication SystemsMAX3 ..
MAX364ESE+ ,Precision, Quad, SPST Analog SwitchesMAX364/MAX36519-0181; Rev 1; 9/01Precision, Quad, SPST Analog Switches_______________
MAX364ESE+T ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX364/MAX365 are precision, quad, single-pole ♦ Low On Resistance: < 45Ω Typical (85Ω ..
MAX3656ETG ,155Mbps to 2.5Gbps Burst-Mode Laser DriverApplicationsFiber-to-the-Home (FTTH) and Fiber-to-the-Functional Diagram appears at end of data she ..
MAX1240ACSA-MAX1240AESA-MAX1240BCSA-MAX1240BESA-MAX1240CCSA-MAX1241ACSA-MAX1241AEPA-MAX1241AESA-MAX1241BCSA-MAX1241BEPA-MAX1241BESA-MAX1241CCPA-MAX1241CCSA-MAX1241CESA
+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SO
__________________General DescriptionThe MAX1240/MAX1241 are low-power, 12-bit analog-
to-digital converters (ADCs) available in 8-pin pack-
ages. The MAX1240 operates with a single +2.7V to
+3.6V supply, and the MAX1241 operates with a single
+2.7V to +5.25V supply. Both devices feature a 7.5µs
successive-approximation ADC, a fast track/hold
(1.5µs), an on-chip clock, and a high-speed, 3-wire ser-
ial interface.
Power consumption is only 37mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1240 has an internal 2.5V reference, while the
MAX1241 requires an external reference. The MAX1241
accepts signals from 0V to VREF, and the reference
input range includes the positive supply rail. An exter-
nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and MICROWIRE™.
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
acquisition applications, or for other circuits with
demanding power consumption and space require-
ments. The MAX1240/MAX1241 are available in 8-pin
DIP and SO packages.
ApplicationsBattery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process Control
Instrumentation
________________________________FeaturesSingle-Supply Operation:
+2.7V to +3.6V (MAX1240)
+2.7V to +5.25V (MAX1241)12-Bit ResolutionInternal 2.5V Reference (MAX1240)Small Footprint: 8-Pin DIP/SO PackagesLow Power: 3.7µW (73ksps, MAX1240)
3mW (73ksps, MAX1241)
66µW (1ksps, MAX1241)
5µW (power-down mode)Internal Track/HoldSPI/QSPI/MICROWIRE 3-Wire Serial InterfaceInternal Clock
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
Ordering Information continued at end of data sheet.*Dice are specified at TA=+25°C, DC parameters only.
Pin Configuration
Ordering Information
Functional Diagram
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
VDDto GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1240_C_A/MAX1241_C_A.........................0°C to +70°C
MAX1240_E_ A/MAX1241_E_ A.....................-40°C to +85°C
MAX1240_MJA/MAX1241_MJA...................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:MAX1240—internal reference, offset nulled; MAX1241—external reference (VREF= +2.500V), offset nulled.
Note 4:External load should not change during conversion for specified accuracy.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:Measured as [VFS(2.7V) - VFS(VDD(MAX)].
Note 7:To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
TIMING CHARACTERISTICS (Figure 8)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); TA= TMINto TMAX, unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
__________________________________________Typical Operating Characteristics(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
_______________________________________________________________________Pin DescriptionINTEGRAL NONLINEARITY
vs. CODE
MAX1241-11A/NEW
INL (LSB)
CODE
FFT PLOT
AMPLITUDE (dB)
FREQUENCY (kHz)
MAX1241-TOC12A
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, REF = 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
_______________Detailed Description
Converter OperationThe MAX1240/MAX1241 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 12-bit out-
put. No external-hold capacitor is needed for the T/H.
Figure 3 shows the MAX1240/MAX1241 in its simplest
configuration. The MAX1240/MAX1241 convert input
signals in the 0V to VREFrange in 9µs, including T/H
acquisition time. The MAX1240’s internal reference is
trimmed to 2.5V, while the MAX1241 requires an external
reference.Both devices accept voltages from 1.0V to
VDD. The serial interface requires only three digital lines
(SCLK, CS,and DOUT) and provides an easy interface
to microprocessors (µPs).
The MAX1240/MAX1241 have two modes: normal and
shutdown. Pulling SHDNlow shuts the device down and
reduces supply current below 10µA (VDD≤3.6V), while
pullingSHDNhigh or leaving it open puts the device
into operational mode. Pulling CSlow initiates a conver-
sion. The conversion result is available at DOUT in
unipolar serial format. The serial data stream consists
of a high bit, signaling the end of conversion (EOC), fol-
lowed by the data bits (MSB first).
Analog InputFigure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/HoldIn track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CSlow ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLDto GND. The retained charge on CHOLDrepre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of CHOLDswitches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:
tACQ= 9(RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the input signal’s source imped-
ance, and tACQis never less than 1.5µs. Source imped-
ances below 1kΩdo not significantly affect the ADC’s
AC performance.
Figure 3. Operational DiagramFigure 4. Equivalent Input Circuit
