MAX1240ACSA+T ,+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SOapplications, or for other circuits withMAX1240BCSA+ 0°C to +70°C 8 SO ±1demanding power consumptio ..
MAX1240AESA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOGeneral Description ____________
MAX1240BCSA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOApplicationsOrdering Information continued at end of data sheet.*Dice are specified at T = +25°C, D ..
MAX1240BESA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOapplications, or for other circuits with1MAX1240ACSA 0°C to +70°C 8 SO ± /2demanding power consumpt ..
MAX1240CCSA ,+2.7V / Low-Power / 12-Bit Serial ADCs in 8-Pin SOMAX1240/MAX124119-1155; Rev 2; 11/98+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO_______________ ..
MAX1241 ,+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SOApplicationsOrdering Information continued at end of data sheet.Battery-Powered Systems*Dice are sp ..
MAX3645EEE ,+2.97 to +5.5 V, 125 Mbps to 200 Mbps limiting amplifier with loss-of-signal detectorApplicationsSONET 155Mbps TransceiversTOP VIEWFast Ethernet ReceiversCAZ21 16 THFDDI 125Mbps Receiv ..
MAX3645EEE+ ,+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal DetectorELECTRICAL CHARACTERISTICS(V = +2.97V to +5.5V, PECL outputs are terminated with 50Ω to V - 2V, R = ..
MAX3645EEE+T ,+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detectorfeatures an integrated power detector♦ Output Disable Function and Automatic Squelchwith complement ..
MAX3645ESE ,+2.97 to +5.5 V, 125 Mbps to 200 Mbps limiting amplifier with loss-of-signal detectorELECTRICAL CHARACTERISTICS(V = +2.97V to +5.5V, PECL outputs are terminated with 50Ω to V - 2V, R = ..
MAX3645ESE+T ,+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal DetectorApplications+Denotes lead-free package.SONET 155Mbps Transceivers Pin ConfigurationFast Ethernet Re ..
MAX3646ETG ,155Mbps to 622Mbps SFF/SFP Laser Driver with Extinction Ratio ControlApplicationsMODTCOMP 1 18MDMultirate OC-3 to OC-12 FEC TransceiversV 2 VCC 17 CC125Mbps Ethernet SF ..
MAX1240ACSA+-MAX1240ACSA+T-MAX1241AESA+-MAX1241AESA+T-MAX1241BCPA+-MAX1241BCSA+T-MAX1241BESA+T
+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO
__________________General DescriptionThe MAX1240/MAX1241 low-power, 12-bit analog-to-
digital converters (ADCs) are available in 8-pin pack-
ages. The MAX1240 operates with a single +2.7V to
+3.6V supply, and the MAX1241 operates with a single
+2.7V to +5.25V supply. Both devices feature a 7.5µs
successive-approximation ADC, a fast track/hold
(1.5µs), an on-chip clock, and a high-speed, 3-wire ser-
ial interface.
Power consumption is only 37mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1240 has an internal 2.5V reference, while the
MAX1241 requires an external reference. The MAX1241
accepts signals from 0V to VREF, and the reference
input range includes the positive supply rail. An exter-
nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and MICROWIRE™.
Excellent AC characteristics and very low power com-
bined with ease of use and small package size make
these converters ideal for remote-sensor and data-
acquisition applications, or for other circuits with
demanding power consumption and space require-
ments. The MAX1240/MAX1241 are available in 8-pin
PDIP and SO packages.
ApplicationsBattery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process Control
Instrumentation
________________________________FeaturesSingle-Supply Operation:+2.7V to +3.6V (MAX1240)
+2.7V to +5.25V (MAX1241)12-Bit ResolutionInternal 2.5V Reference (MAX1240)Small Footprint: 8-Pin PDIP/SO PackagesLow Power: 3.7µW (73ksps, MAX1240)3mW (73ksps, MAX1241)
66µW (1ksps, MAX1241)5µW (power-down mode)Internal Track/HoldSPI/QSPI/MICROWIRE 3-Wire Serial InterfaceInternal Clock
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO19-1155; Rev 5; 8/10
Ordering Information continued at end of data sheet.TOP VIEW
SCLK
DOUT
GNDREF
SHDN
AIN
VDD
PDIP/SOMAX1240
MAX1241
Pin Configuration
Ordering Information
EVALUATION KIT
AVAILABLE
Functional DiagramAINT/H
DOUT6
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
12-BIT
SAR
REF4
SHDN
2.5V REFERENCE
(MAX1240 ONLY)
GND
SCLK
MAX1240
MAX1241
VDD
*Dice are specified at TA=+25°C, DC parameters only.
**Future product—contact factory for availability.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART*TEMP RANGEPIN -
PA C K A G E
INL
(LSB)
MAX1240ACPA+0°C to +70°C8 PDIP±1/2
MAX1240BCPA+0°C to +70°C8 PDIP±1
MAX1240CCPA+0°C to +70°C8 PDIP±1
MAX1240ACSA+0°C to +70°C8 SO±1/2
MAX1240BCSA+0°C to +70°C8 SO±1
MAX1240CCSA+0°C to +70°C8 SO±1
MAX1240CC/D0°C to +70°CDice*±1
MAX1240AESA/V+**-40°C to +85°C8 SO±1/2
MAX1240BESA/V+-40°C to +85°C8 SO±1
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
VDDto GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1240_C_A/MAX1241_C_A.........................0°C to +70°C
MAX1240_E_ A/MAX1241_E_ A.....................-40°C to +85°C
MAX1240_MJA/MAX1241_MJA...................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)
PDIP, SO.....................................................................+260°C
CDIP...........................................................................+250°C
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
71.5MAX124_C
Input Voltage Range0VREFV
Input Capacitance
Aperture Jitter<50pspF
MAX124_A
MAX124_B/C
Aperture DelaytAPR30nsFigure 8
Track/Hold Acquisition TimetACQ1.5µs
Throughput Rate73kspsfSCLK= 2.1MHz
Conversion Time
PARAMETERSYMBOLMINTYPMAXUNITS±0.5±3.0Offset ErrorLSB
Differential NonlinearityDNL±1LSB
±1.0
Gain Temperature Coefficient
±0.5±4.0
Gain Error (Note 3)LSB±0.5±4.0
Resolution12Bits
Relative Accuracy (Note 2)INL±0.5LSB
tCONV5.57.5µs
Small-Signal Bandwidth
Signal-to-Noise Plus
Distortion RatioSINAD70dB
2.25MHz
Full-Power Bandwidth
Total Harmonic DistortionTHD-80dB
-3dB rolloff
MHz
CONDITIONSSpurious-Free Dynamic Range
ppm/°C
No missing codes over temperature
MAX124_B/C
±0.25
SFDR
MAX124_A/B
Up to the 5th harmonicMAX124_A/B
MAX124_A
MAX124_A/B
MAX124_C-88
MAX124_C88
ANALOG INPUT
CONVERSION RATE
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, 0V to 2.500Vp-p, 73ksps, fSCLK= 2.1MHz)
DC ACCURACY(Note 1)
ppm/°C
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
VIN= 0V or VDDµA= +25°C100150
±0.01±1IINSCLK, CSInput Leakage0.2
Input Current
CONDITIONSVSHDN= 0VµA±0.0110
VHYSTSCLK, CSInput Hysteresis
VSHDN= 0V or VDDµA
REF Input Current in Shutdown 1825
±4.0SHDNInput Current
Input Resistance0.4VSLSHDNInput Low Voltage
(Note 5)
VDD - 0.4VSHSHDNInput High Voltage15CINREF Output Voltage
SCLK, CSInput Capacitance
SHDN= unconnectednA
SHDN= unconnected
±100SHDNMax Allowed Leakage,
Mid InputVDD/2VFLTSHDNVoltage, Unconnected1.1VDD - 1.1VSMSHDNInput Mid Voltage
ISINK= 5mA
UNITSMINTYPMAXSYMBOLPARAMETER0.4VOLOutput Voltage Low= VDD (Note 5)pF15COUTThree-State Output Capacitance= VDDµA
ISOURCE= 0.5mA
±0.01±10ILThree-State Leakage CurrentVDD - 0.5VOH
VDD≤3.6V
0.8VIL0.1Capacitive Bypass at REF
SCLK, CSInput Low Voltage2.0VIHSCLK, CSInput High Voltage
Output Voltage High
ISINK= 16mA
VDD> 3.6V (MAX1241)
2.4802.5002.520Input Voltage Range1.00VDD +
50mV
MAX1240AC/BC
ppm/°CREF Temperature Coefficient
±30±50
REF Short-Circuit Current30
MAX1240AE/BE±30±60
MAX1240AM/BM±30±80
0mA to 0.2mA output loadLoad Regulation (Note 4)0.35Capacitive Bypass at REF4.7
MAX1240C±30
DIGITAL OUTPUT: DOUT
DIGITAL INPUTS: SCLK, CCSS, SSHHDDNN
EXTERNAL REFERENCE(VREF= 2.500V)
INTERNAL REFERENCE(MAX1240 only)
VDD = 3.6V
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF
capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:MAX1240—internal reference, offset nulled; MAX1241—external reference (VREF= +2.500V), offset nulled.
Note 4:External load should not change during conversion for specified accuracy.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:Measured as [VFS(2.7V) - VFS(VDD(MAX)].
Note 7:To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
SCLK Pulse Width LowtCL200ns
SCLK Pulse Width HightCH200ns
SCLK Clock FrequencyfSCLK02.1MHzRise to Output DisabletTR240ns
SCLK Low to CSFall Setup TimetCS050ns
DOUT Rise to SCLK Rise (Note 5)tSTR0nsPulse WidthtCS240ns
Figure 2, CLOAD= 50pFFall to Output EnabletDV240nsFigure 1, CLOAD= 50pF
PARAMETERSSYMBOLMINTYPMAXUNITSCONDITIONSAcquisition TimetACQ1.5µsCS= VDD(Note 6)
TIMING CHARACTERISTICS (Figure 8)(VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSSYMBOLMINTYPMAXUNITSCONDITIONS2.73.6MAX1240
2.75.25MAX1241VDDSupply VoltageV
±0.3(Note 5)PSRSupply RejectionmV240SCLK Fall to Output Data ValidtDO20200nsFigure 1,
CLOAD= 50pF
MAX124_ _C/E
MAX124_ _M
Operating
mode1.62.5
VDD = 3.6V
VDD = 5.25V
VDD = 3.6V
VDD = 5.25V
IDD
1.910Power-down, digital inputs
at 0V or VDD
VDD = 3.6VMAX1240C
MAX1241A/B
Supply Current
MAX1240A/B
VDD = 3.6V
VDD = 5.25V
0.92.8MAX1241C
POWER REQUIREMENTS
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SOOFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1241-03
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
__________________________________________Typical Operating Characteristics(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1241-D
SUPPLY VOLTAGE (V)
OPERATING SUPPLY CURRENT (mA)
RL = ∞
CODE = 101010100000
MAX1241
MAX1240
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1241-A/NEW
MAX1241
MAX1240
RLOAD = ∞
CODE = 10101010000
DOUTDOUT
DGND
CLOAD = 50pFCLOAD = 50pF
DGND
+2.7V
b) High-Z to VOL and VOH to VOL
a) High-Z to VOH and VOL to VOH
Figure 1. Load Circuits for DOUT Enable Time
DOUTDOUT
DGND
CLOAD = 50pFCLOAD = 50pF
DGND
+2.7V
b) VOLto High-Z
a) VOH to High-Z
Figure 2. Load Circuits for DOUT Disable Time
MAX1240
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
VREF (V)
MAX1241-0Y
VDD = 2.7V
VDD = 3.6V
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1241-09/NEW
INL (LSB)
MAX1240
MAX1241
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
GAIN ERROR
vs. SUPPLY VOLTAGE
MAX1241-07
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
GAIN ERROR
vs. TEMPERATURE
MAX1241-08
TEMPERATURE (°C)
GAIN ERROR (LSB)
VDD = 2.7V
MAX1240
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
VDD (V)
VREF (V)
MAX1241-0X
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1241-B
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (
OFFSET ERROR vs. TEMPERATURE
MAX1241-06
TEMPERATURE (°C)
OFFSET ERROR (LSB)
VDD = 2.7V
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
MAX1241-C/NEW
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1241-10/NEW
INL (LSB)
VDD = 2.7V
MAX1240
MAX1241
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
_______________________________________________________________________Pin DescriptionDOUTSerial Data Output. Data changes state at SCLK’s falling edge. DOUT is high impedance when CSis
high.SCLKSHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1240/MAX1241 down to 15µA (max)
supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDNhigh or
unconnected. For the MAX1240, pulling SHDNhigh enables the internal reference, and letting SHDN
open disables the internal reference and allows for the use of an external reference.REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240;
bypass with 4.7µF capacitor. External reference voltage input for MAX1241, or for MAX1240 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.CSActive-Low Chip Select initiates conversions on the falling edge. When CSis high, DOUT is high
impedance.GNDAnalog and Digital GroundAINSampling Analog Input, 0V to VREFrange
NAMEFUNCTIONVDDPositive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7V to 5.25V (MAX1241)
PINSerial Clock Input. SCLK clocks data out at rates up to 2.1MHz.
INTEGRAL NONLINEARITY
vs. CODE
MAX1241-11A/NEW
INL (LSB)
CODE
FFT PLOT
AMPLITUDE (dB)
FREQUENCY (kHz)
fAIN = 10kHz, 2.5VP-P
fSAMPLE = 73ksps
MAX1241-TOC12A
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, REF = 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
_______________Detailed Description
Converter OperationThe MAX1240/MAX1241 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 12-bit out-
put. No external-hold capacitor is needed for the T/H.
Figure 3 shows the MAX1240/MAX1241 in its simplest
configuration. The MAX1240/MAX1241 convert input
signals in the 0V to VREFrange in 9µs, including T/H
acquisition time. The MAX1240’s internal reference is
trimmed to 2.5V, while the MAX1241 requires an external
reference.Both devices accept voltages from 1.0V to
VDD. The serial interface requires only three digital lines
(SCLK, CS,and DOUT) and provides an easy interface
to microprocessors (µPs).
The MAX1240/MAX1241 have two modes: normal and
shutdown. Pulling SHDNlow shuts the device down and
reduces supply current below 10µA (VDD≤3.6V), while
pullingSHDNhigh or leaving it open puts the device
into operational mode. Pulling CSlow initiates a conver-
sion. The conversion result is available at DOUT in
unipolar serial format. The serial data stream consists
of a high bit, signaling the end of conversion (EOC), fol-
lowed by the data bits (MSB first).
Analog InputFigure 4 illustrates the sampling architecture of the ana-
log-to-digital converter’s (ADC’s) comparator. The full-
scale input voltage is set by the voltage at REF.
Track/HoldIn track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CSlow ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLDto GND. The retained charge on CHOLDrepre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of CHOLDswitches back to AIN, and CHOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. Acquisition time is calculated by:ACQ= 9(RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the input signal’s source imped-
ance, and tACQis never less than 1.5µs. Source imped-
ances below 1kΩdo not significantly affect the ADC’s
AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
AINTRACKINPUT
HOLD
GND
TRACK
HOLD
RIN
CHOLD
16pF
CSWITCH
COMPARATOR
ZERO
REF
12-BIT CAPACITIVE DAC
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
SHUTDOWN
INPUT
ANALOG INPUT
0V TO VREF
+2.7V to +3.6V**
VDD,MAX = +5.25V (MAX1241)
4.7μF (MAX1240)
0.1μF (MAX1241)
VDD
AIN
SHDN
REF
SCLK
DOUT
GND
SERIAL
INTERFACE
C**
4.7μF0.1μF
REFERENCE
INPUT
(MAX1241 ONLY)
MAX1240
MAX1241
Figure 3. Operational DiagramFigure 4. Equivalent Input Circuit
