MAX1228BCEP+ ,12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal ReferenceFeaturesThe MAX1226/MAX1228/MAX1230 are serial 12-bit ana-♦ Internal Temperature Sensor (±0.7°C Acc ..
MAX1229BCEP+ ,12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal ReferenceFeaturesThe MAX1227/MAX1229/MAX1231 are serial 12-bit ana- ♦ Internal Temperature Sensor (±0.7°C Ac ..
MAX1229BEEP+ ,12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal ReferenceELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, f = 300kHz, f = 4.8MHz (50% duty cycle), V = 2.5V, T ..
MAX122ACAG+ ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceFeaturesThe MAX120/MAX122 complete, BiCMOS, sampling 12-bit ● 12-Bit Resolutionanalog-to-digital co ..
MAX122ACNG ,500ksps, 12-Bit ADCs with Track/Hold And RefrencelVI/lXI/VI
500ksps, 12-Bit ADCs
with Track/Hold and Reference
MAX122ACNG+ ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceApplicationsMAX120ENG+ -40°C to +85°C 24 PDIP ±1● Digital-Signal ProcessingMAX120EWG+ -40°C to +85° ..
MAX351ESE ,Precision, Quad, SPST Analog Switches
MAX351ESE+ ,Precision, Quad, SPST Analog Switches
MAX352CSE ,Precision, Quad, SPST Analog Switches
MAX352CSE ,Precision, Quad, SPST Analog Switches
MAX352CSE+ ,Precision, Quad, SPST Analog Switches
MAX352ESE+ ,Precision, Quad, SPST Analog Switches
MAX1226BEEE+-MAX1228BCEP+-MAX1230ACEG-MAX1230AEEG+-MAX1230BCEG+-MAX1230BCEG+T
12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference
General DescriptionThe MAX1226/MAX1228/MAX1230 are serial 12-bit ana-
log-to-digital converters (ADCs) with an internal reference
and an internal temperature sensor. These devices fea-
ture on-chip FIFO, scan mode, internal clock mode, inter-
nal averaging, and AutoShutdown™. The maximum
sampling rate is 300ksps using an external clock. The
MAX1230 has 16 input channels, the MAX1228 has 12
input channels, and the MAX1226 has 8 input channels.
All input channels are configurable for single-ended or
differential inputs in unipolar or bipolar mode. All three
devices operate from a +5V supply and contain a 10MHz
SPI™/QSPI™/MICROWIRE™-compatible serial port.
The MAX1230 is available in 28-pin 5mm x 5mm thin
QFN with exposed pad and 24-pin QSOP packages.
The MAX1226/MAX1228 are only available in QSOP
packages. All three devices are specified over the
extended -40°C to +85°C temperature range.
________________________ApplicationsSystem Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
FeaturesInternal Temperature Sensor (±0.7°C Accuracy)16-Entry First-In/First-Out (FIFO)Analog Multiplexer with True Differential
Track/Hold
16-, 12-, 8-Channel Single Ended
8-, 6-, 4-Channel True Differential
(Unipolar or Bipolar)Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing
Codes Over TemperatureScan Mode, Internal Averaging, and Internal ClockLow-Power Single +5V Operation
2.3mA at 300kspsInternal 4.096V Reference or External Differential
Reference10MHz 3-Wire SPI/QSPI/MICROWIRE-Compatible
InterfaceSpace-Saving 28-Pin 5mm x 5mm Thin QFN
Package
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Pin Configurations19-2852; Rev 5; 12/10
EVALUATION KIT
AVAILABLE
Ordering InformationAIN0EOC
DOUT
DIN
SCLK
VDD
GND
REF+
MAX1226
QSOP
TOP VIEWAIN1
AIN2
AIN5
AIN3
AIN4
REF-/AIN6
CNVST/AIN7
EOC
DOUT
DINAIN3
AIN2
AIN1
AIN0
SCLK
VDD
GND
REF+AIN7
AIN6
AIN5
AIN4
CNVST/AIN11
REF-/AIN10AIN9
AIN8
MAX1228
QSOP
PARTTEMP RANGEPIN-PACKAGE
MAX1226BCEE+0°C to +70°C16 QSOP
MAX1226BEEE+-40°C to +85°C16 QSOP
MAX1228BCEP+0°C to +70°C20 QSOP
MAX1228BEEP+-40°C to +85°C20 QSOP
Pin Configurations continued at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP= Exposed pad (TQFN only). Connect to GND.
Ordering Information continued at end of data sheet.
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V ±5%, fSAMPLE= 300kHz, fSCLK= 4.8MHz (50% duty cycle), VREF= 4.096V, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD+ 0.3V)
AIN0–AIN13, REF-/AIN_, CNVST/AIN_,
REF+ to GND.........................................-0.3V to (VDD+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
28-Pin Thin QFN 5mm x 5mm
(derate 20.8mW/°C above +70°C)........................1667mW
Operating Temperature Ranges
MAX12__C__.......................................................0°C to +70°C
MAX12__E__....................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)ResolutionRES12Bits
Integral NonlinearityINL±1.0LSB
Differential NonlinearityDNLNo missing codes over temperature±1.0LSB
Offset Error±0.5±4.0LSB
Gain Error(Note 2)±0.5±4.0LSB
Offset Error Temperature
Coefficient±2ppm/°C
FSR
Gain Temperature Coefficient±0.8ppm/°C
Channel-to-Channel Offset
Matching±0.1LSB
DYNAMIC SPECIFICATIONS (30kHz sine wave input, 4.096VP-P, 300ksps, fSCLK = 4.8MHz)Signal-to-Noise Plus DistortionSINAD73dB
Total Harmonic DistortionTHDUp to the 5th harmonic-88dBc
Spurious-Free Dynamic RangeSFDR89dBc
Intermodulation DistortionIMDfin1 = 29.9kHz, fin2 = 30.2kHz76dBc
Full-Power Bandwidth-3dB point1MHz
Full-Linear BandwidthS / (N + D) > 68dB100kHz
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±5%, fSAMPLE= 300kHz, fSCLK= 4.8MHz (50% duty cycle), VREF= 4.096V, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CONVERSION RATEExternal reference0.8Power-Up TimetPUInternal reference (Note 3)65µs
Acquisition TimetACQ0.6µs
Internally clocked3.5Conversion TimetCONVExternally clocked (Note 4)2.7µs
Externally clocked conversion0.14.8External Clock FrequencyfSCLKData I/O10MHz
Aperture Delay30ns
Aperture Jitter<50ps
ANALOG INPUTUnipolar0VREFInput Voltage RangeBipolar (Note 5)- V RE F /2V RE F /2V
Input Leakage CurrentVIN = VDD±0.01±1µA
Input CapacitanceDuring acquisition time (Note 6)24pF
INTERNAL TEMPERATURE SENSORTA = +25°C±0.7Measurement Error (Note 7)TA = TMIN to TMAX±1.2±3.0°C
Temperature Measurement Noise0.1°CRMS
Temperature Resolution1/8°C
Power-Supply Rejection0.3°C/V
INTERNAL REFERENCEREF Output Voltage4.0244.0964.168V
REF Temperature CoefficientTCREF±20ppm/°C
Output Resistance6.5kΩ
REF Output Noise200µVRMS
REF Power-Supply RejectionPSRR-70dB
EXTERNAL REFERENCE INPUTREF- Input Voltage RangeVREF-0500mV
REF+ Input Voltage RangeVREF+1.0VDD + 50mVV
VREF+ = 4.096V, fSAMPLE = 300ksps40100REF+ Input CurrentIREF+VREF+ = 4.096V, fSAMPLE = 0±0.1±5µA
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Note 1:Tested at VDD= +5V, unipolar input mode.
Note 2:Offset nulled.
Note 3:Time for reference to power up and settle to within 1 LSB.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:The operational input voltage range for each individual input of a differentially configured pair is from GND to VDD. The
operational input voltage difference is from -VREF/2 to +VREF/2.
Note 6:See Figure 3 (Input Equivalent Circuit) and the Sampling Errorvs. Source Impedancecurve in the Typical Operating
Characterisitcssection.
Note 7:Fast automated test, excludes self-heating effects.
Note 8:When CNVSTis configured as a digital input, do not apply a voltage between VILand VIH.
Note 9:Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
Temperature measurements always use the internal reference.
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±5%, fSAMPLE= 300kHz, fSCLK= 4.8MHz (50% duty cycle), VREF= 4.096V, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)Input Voltage LowVIL(Note 8)0.8V
Input Voltage HighVIH2.0V
Input HysteresisVHYST200mV
Input Leakage CurrentIINVIN = 0 or VDD±0.01±1.0µA
Input CapacitanceCIN15pF
DIGITAL OUTPUTS (DOUT, EOC)ISINK = 2mA0.4Output Voltage LowVOLISINK = 4mA0.8V
Output Voltage HighVOHISOURCE = 1.5mAVDD - 0.5V
Tri-State Leakage CurrentILCS = VDD±0.05±1µA
Tri-State Output CapacitanceCOUTCS = VDD15pF
POWER REQUIREMENTSSupply VoltageVDD4.755.25V
During temp sense28003200
fSAMPLE = 300ksps23002550
fSAMPLE = 0, REF on10501350
Internal
reference
Shutdown0.25
During temp sense18002300
fSAMPLE = 300ksps16001700
Supply Current (Note 9)IDD
External
reference
Shutdown0.25
Power-Supply RejectionPSRVDD = 4.75V to 5.25V; full-scale input±0.2±1.4mV
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSExternally clocked conversion208SCLK Clock PeriodtCPData I/O100ns
SCLK Duty CycletCH4060%
SCLK Fall to DOUT TransitiontDOTCLOAD = 30pF40ns
CS Rise to DOUT DisabletDODCLOAD = 30pF40ns
CS Fall to DOUT EnabletDOECLOAD = 30pF40ns
DIN to SCLK Rise SetuptDS40ns
SCLK Rise to DIN HoldtDH0ns
CS Fal l to S C LK Ri se S etup Ti m etCSS040ns
CS Fal l - to- S C LK H ol d Ti m etCSH00ns
CS Ri se- to- S C LK Ri se H ol d Ti m etCSH104µs
CS Ri se- to- S C LK Ri se S etup Ti m etCSS140ns
CKSEL = 00, CKSEL = 01 (temp sense)40nsCNVST Pulse WidthtCSWCKSEL = 01 (voltage conversion)1.4µs
t T S Temp sense55
Voltage conversion7CS or CNVST Rise to EOC
Low (Note 10)R P Reference power-up65
TIMING CHARACTERISTICS (Figure 1)
Note 10:This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive. The internal reference is always used for temperature measurements.
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1226/28/30 toc01
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1226/28/30 toc02
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
SINAD vs. FREQUENCYMAX1226/28/30 toc03
FREQUENCY (kHz)
SINAD AMPLITUDE (dB)
Typical Operating Characteristics
(VDD= +5V, VREF= +4.096V, fSCLK= 4.8MHz, CLOAD= 30pF, TA= +25°C, unless otherwise noted.)
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Referenceypical Operating Characteristics (continued)(VDD= +5V, VREF= +4.096V, fSCLK= 4.8MHz, CLOAD= 30pF, TA= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1226/28/30 toc10
INTERNAL REFERENCE VOLTAGE (V)
SFDR vs. FREQUENCYMAX1226/28/30 toc04
FREQUENCY (kHz)
SFDR AMPLITUDE (dB)
SUPPLY CURRENT vs. SAMPLING RATE
MAX1226/28/30 toc05
SAMPLING RATE (ksps)
SUPPLY CURRENT (
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1226/28/30 toc06
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1226/28/30 toc07
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
SUPPLY CURRENT vs. TEMPERATUREMAX1226/28/30 toc08
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
fS = 300ksps
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1226/28/30 toc09
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal ReferenceINTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1226/28/30 toc11
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1226/28/30 toc12
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
OFFSET ERROR
vs. TEMPERATURE
MAX1226/28/30 toc13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1226/28/30 toc14
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1226/28/30 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
-40-1535856010
ypical Operating Characteristics (continued)(VDD= +5V, VREF= +4.096V, fSCLK= 4.8MHz, CLOAD= 30pF, TA= +25°C, unless otherwise noted.)
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
MAX1226/28/30 toc16
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR (
°C)
GRADE B
SAMPLING ERROR
vs. SOURCE IMPEDANCE
MAX1226/28/30 toc17
SOURCE IMPEDANCE (kΩ)
SAMPLING ERROR (LSB)
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Pin Description
MAX1230
TQFN
MAX1230
QSOPMAX1228MAX1226NAMEFUNCTION1, 17,
19, 25———N.C.No Connection. Not internally connected.
2–12, 26,
27, 281–14——AIN0–13Analog Inputs—1–10—AIN0–9Analog Inputs——1–6AIN0–5Analog Inputs15——REF-/AIN14Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.—11—REF-/AIN10Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.——7REF-/AIN6Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.16——CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.—12—CNVST/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.—8CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.17139REF+Positive Reference Input. Bypass to GND with a 0.1µF capacitor.181410GNDGround191511VDDPower Input. Bypass to GND with a 0.1µF capacitor.201612SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.211713CSActive-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.221814DINSerial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.231915DOUTSerial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to VDD.242016EOCEnd of Conversion Output. Data is valid after EOC pulls low.——EP
Exposed Pad. Internally connected to GND. Connect to a large
ground plane to maximize thermal performance. Not intended as
an electrical connection point.
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Detailed DescriptionThe MAX1226/MAX1228/MAX1230 are low-power, seri-
al-output, multichannel ADCs with temperature-sensing
capability for temperature-control, process-control, and
monitoring applications. These 12-bit ADCs have inter-
nal track and hold (T/H) circuitry that supports single-
ended and fully differential inputs. Data is converted
from an internal temperature sensor or analog voltage
sources in a variety of channel and data-acquisition
configurations. Microprocessor (µP) control is made
easy through a 3-wire SPI/QSPI/MICROWIRE-compati-
ble serial interface.
Figure 2 shows a simplified functional diagram of the
MAX1226/MAX1228/MAX1230 internal architecture.
The MAX1226 has eight single-ended analog input
channels or four differential channels. The MAX1228
has 12 single-ended analog input channels or six differ-
ential channels. The MAX1230 has 16 single-ended
analog input channels or eight differential channels.
12-BIT
SAR
ADC
CONTROL
SERIAL INTERFACE
OSCILLATOR
FIFO AND
ACCUMULATORMUX
TEMP
SENSE
REF-
CNVST
SCLK
DIN
EOC
DOUT
AIN15
AIN1
AIN2
INTERNAL
REFERENCEREF+
MAX1226
MAX1228
MAX1230
Figure 2. Functional Diagram
SCLK
DIN
DOUT
tDH
tDOE
tDS
tCHtCSS0tCPtCSH1tCSH0
tCSS1
tDODtDOT
Figure 1. Detailed Serial-Interface Timing Diagram
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Converter OperationThe MAX1226/MAX1228/MAX1230 ADCs use a fully dif-
ferential, successive-approximation register (SAR) con-
version technique and an on-chip T/H block to convert
temperature and voltage signals into a 12-bit digital
result. Both single-ended and differential configurations
are supported, with a unipolar signal range for single-
ended mode and bipolar or unipolar ranges for differ-
ential mode.
Input BandwidthThe ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Analog Input Protection Internal ESD protection diodes clamp all pins to VDD
and GND, allowing the inputs to swing from (GND -
0.3V) to (VDD+ 0.3V) without damage. However, for
accurate conversions near full scale, the inputs must
not exceed VDDby more than 50mV or be lower than
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
3-Wire Serial InterfaceThe MAX1226/MAX1228/MAX1230 feature a serial
interface compatible with SPI/QSPI and MICROWIRE
devices. For SPI/QSPI, ensure the CPU serial interface
runs in master mode so it generates the serial clock
signal. Select the SCLK frequency of 10MHz or less,
and set clock polarity (CPOL) and phase (CPHA) in the
µP control registers to the same value. The MAX1226/
MAX1228/MAX1230 operate with SCLK idling high or
low, and thus operate with CPOL = CPHA = 0 or CPOL
= CPHA = 1. Set CSlow to latch input data at DIN on
the rising edge of SCLK. Output data at DOUT is
updated on the falling edge of SCLK. Bipolar true dif-
ferential results and temperature sensor results are
available in two’s complement format, while all others
are in binary.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. Use a second
byte, immediately following the setup byte, to write to
the unipolar mode or bipolar mode registers (see
Tables 1, 3, 4, and 5). A high-to-low transition on CSini-
tiates the data input operation. The input data byte and
the subsequent data bytes are clocked from DIN into
the serial interface on the rising edge of SCLK.
Tables 1–7 detail the register descriptions. Bits 5 and 4,
CKSEL1 and CKSEL0, respectively, control the clock
modes in the setup register (see Table 3). Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request the programmed inter-
nally timed conversions without tying up the serial bus.
In clock mode 01, use CNVSTto request conversions
one channel at a time, controlling the sampling speed
without tying up the serial bus. Request and start inter-
nally timed conversions through the serial interface by
writing to the conversion register in the default clock
mode, 10. Use clock mode 11 with SCLK up to 4.8MHz
for externally timed acquisitions to achieve sampling
rates up to 300ksps. Clock mode 11 disables scanning
and averaging. See Figures 4–7 for timing specifica-
tions and how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOCgoes low when the ADC completes the
last-requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). In clock mode
01, EOCgoes low after the ADC completes each
requested operation. EOCgoes high when CSor
CNVSTgoes low. EOCis always high in clock mode 11.
Single-Ended/Differential InputThe MAX1226/MAX1228/MAX1230 use a fully differen-
tial ADC for all conversions. The analog inputs can be
configured for either differential or single-ended con-
versions by writing to the setup register (see Table 3).
Single-ended conversions are internally referenced to
GND (Figure 3).
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
and AIN14/AIN15. AIN0–AIN7 are available on the
MAX1226, MAX1228, and MAX1230. AIN8–AIN11 are
only available on the MAX1228 and MAX1230.
AIN12–AIN15 are only available on the MAX1230. See
Tables 2–5 for more details on configuring the inputs.
For the inputs that can be configured as CNVSTor an
analog input, only one can be used at a time. For the
inputs that can be configured as REF- or an analog
input, the REF- configuration excludes the analog input.
Unipolar/BipolarAddress the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Referenceappropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0 to
VREF. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±VREF / 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode. (See
the transfer function graphs, Figures 8 and 9.)
In single-ended mode, the MAX1226/MAX1228/
MAX1230 always operate in unipolar mode. The analog
inputs are internally referenced to GND with a full-scale
input range from 0 to VREF.
True Differential Analog Input T/HThe equivalent circuit of Figure 3 shows the
MAX1226/MAX1228/MAX1230s’ input architecture. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode (and AIN0, AIN2,
AIN4…AIN14 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5…AIN15 in differential mode). For
external track-and-hold timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The time required for the T/H to acquire an
input signal is determined by how quickly its input
capacitance is charged. If the input signal’s source
impedance is high, the required acquisition time length-
ens. The acquisition time, tACQ, is the maximum time
needed for a signal to be acquired, plus the power-up
time. It is calculated by the following equation:
where RIN= 1.5kΩ, RSis the source impedance of the
input signal, and tPWR= 1µs, the power-up time of the
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
tACQis never less than 1.4µs, and any source imped-
ance below 300Ωdoes not significantly affect the
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening tACQor by
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
Internal FIFOThe MAX1226/MAX1228/MAX1230 contain a FIFO
buffer that can hold up to 16 ADC results plus one tem-
perature result. This allows the ADC to handle multiple
internally clocked conversions and a temperature mea-
surement, without tying up the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by 4
leading zeros. After each falling edge of CS, the oldest
available byte of data is available at DOUT, MSB first.
When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature mea-
surement always contain the temperature result preceded
by 4 leading zeros, MSB first. If another temperature mea-
surement is performed before the first temperature result
is read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement) at a resolution of 1/8 of degree. See
the Temperature Measurementssection for details on
converting the digital code to a temperature.
Internal ClockThe MAX1226/MAX1228/MAX1230 operate from an inter-
nal oscillator, which is accurate within 10% of the 4.4MHz
nominal clock rate. The internal oscillator is active in clock
modes 00, 01, and 10. Read out the data at clock speeds
up to 10MHz. See Figures 4–7 for details on timing speci-
fications and starting a conversion.
Applications Information
Register DescriptionsThe MAX1226/MAX1228/MAX1230 communicate
between the internal registers and the external circuitry
through the SPI-/QSPI-compatible serial interface.
Table 1 details the registers and the bit names. Tables
2–7 show the various functions within the conversion
register, setup register, averaging register, reset regis-
ter, unipolar register, and bipolar register.txRRxpFtAQCSINPWR =+()+924
HOLD
CIN+
REF
GNDDAC
CIN-
VDD/2
COMPARATOR
AIN0-AIN15
(SINGLE ENDED);
AIN0, AIN2,
AIN4…AIN14
(DIFFERENTIAL)
GND
(SINGLE ENDED);
AIN1, AIN3,
AIN5…AIN15
(DIFFERENTIAL)HOLD
HOLD
Figure 3. Equivalent Input Circuit
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO, emp Sensor, Internal Reference
Conversion Time CalculationsThe conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use.
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
total conversion time = tcnv ✕navg x nresult+ tTS+ tRP
where:
tcnv= tacq(max) + tconv(max)
navg= samples per result (amount of averaging)
nresult= number of FIFO results requested; determined
by number of channels being scanned by NSCAN1,
NSCAN0
tTS= time required for temperature measurement; set
to zero if temp measurement is not requested
tRP= internal reference wake-up; set to zero if internal
reference is already powered up or external reference is
being used
In clock mode 01, the total conversion time depends on
how long CNVSTis held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CSis held
high between each set of eight SCLK cycles.
Conversion RegisterSelect active analog input channels, scan modes, and
a single temperature measurement per scan by writing
to the conversion register. Table 2 details channel
selection, the four scan modes, and how to request a
temperature measurement. Request a scan by writing
to the conversion register when in clock mode 10 or 11,
or by applying a low pulse to the CNVSTpin when in
clock mode 00 or 01.
A conversion is not performed if it is requested on a
channel that has been configured as CNVSTor REF-.
Do not request conversions on channels 8–15 on the
MAX1226 and channels 12–15 on the MAX1228. Set
CHSEL3:CHSEL0 to the lower channel’s binary value. If
the last two channels are configured as a differential
pair and one of them has been reconfigured as CNVST
or REF-, the pair is ignored.
REGISTER NAMEBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0Conversion1CHSEL3CHSEL2CHSEL1CHSEL0SCAN1SCAN0TEMP
Setup01CKSEL1CKSEL0REFSEL1REFSEL0DIFFSEL1DIFFSEL0
Averaging001AVGONNAVG1NAVG0NSCAN1NSCAN0
Reset0001RESETXXX
Unipolar mode (setup)UCH0/1UCH2/3UCH4/5UCH6/7UCH8/9*UCH10/11*UCH12/13**UCH14/15**
Bipolar mode (setup)BCH0/1BCH1/2BCH4/5BCH6/7BCH8/9*BCH10/11*BCH12/13**BCH14/15**
Table 1. Input Data Byte (MSB First)*Unipolar/bipolar channels 8–15 are only valid on the MAX1228 and MAX1230.
**Unipolar/bipolar channels 12–15 are only valid on the MAX1230.
X = Don’t care.
