MAX121CWE+ ,308ksps ADC with DSP Interface and 78dB SINADApplications TRACK/HOLDAINVSS● Digital Signal Processing3kΩ● Audio and Telecom ProcessingV -5VREFDA ..
MAX121CWE+ ,308ksps ADC with DSP Interface and 78dB SINADApplications TRACK/HOLDAINVSS● Digital Signal Processing3kΩ● Audio and Telecom ProcessingV -5VREFDA ..
MAX121CWE+T ,308ksps ADC with DSP Interface and 78dB SINADFeaturesThe MAX121 is a complete, BiCMOS, serial-output, ● 14-Bit Resolutionsampling 14-bit analog- ..
MAX121EPE ,308Ksps ADC with DSP Interface and 78dB SINADApplications
Digital Signal Processing
Audio and Telecom Processing
Speech Recognition and S ..
MAX121EPE+ ,308ksps ADC with DSP Interface and 78dB SINADEVALUATION KIT AVAILABLEMAX121 308ksps ADC with DSP Interface and 78dB SINAD
MAX121EWE ,308Ksps ADC with DSP Interface and 78dB SINADFeatures
. 14-Bit Resolution
. 2.9ps Conversion Timel308ksps Throughput
. 400ns Acquisition Ti ..
MAX351CPE ,Precision, Quad, SPST Analog Switches
MAX351CPE+ ,Precision, Quad, SPST Analog Switches
MAX351CSE ,Precision, Quad, SPST Analog Switches
MAX351CSE ,Precision, Quad, SPST Analog Switches
MAX351CSE+ ,Precision, Quad, SPST Analog Switches
MAX351ESE ,Precision, Quad, SPST Analog Switches
MAX121CAP+-MAX121CWE+-MAX121CWE+T-MAX121EPE+-MAX121EWE+
308ksps ADC with DSP Interface and 78dB SINAD
General DescriptionThe MAX121 is a complete, BiCMOS, serial-output,
sampling 14-bit analog-to-digital converter (ADC) that
com bines an on-chip track/hold and a low-drift, low-
noise, buried-zener voltage reference with fast conversion
speed and low power consumption. The throughput rate
is as high as 308k samples per second (ksps). The full-
scale analog input range is ±5V.
The MAX121 utilizes the successive-approximation archi-
tecture with a high-speed DAC to achieve both fast
conversion speeds and low-power operation. Operating
with +5V and -12V or -15V power supplies, power con-
sumption is only 210mW.
The MAX121 can be directly interfaced to the serial port
of most popular digital-signal processors, and comes
in space-saving 16-pin DIP and SO and smaller 20-pin
SSOP packages. The MAX121 operates with TTL- and
CMOS-compatible clocks in the frequency range from
1.1MHz to 5.5MHz. All logic inputs and outputs are TTL -
and CMOS-compatible. This data sheet includes applica-
tion notes for easy interface to TMS320, µPD77230, and
ADSP2101 digital-signal processors, as well as µPs using
the Motorola SPI and QSPI interface standards.
Applications●Digital Signal Processing●Audio and Telecom Processing●Speech Recognition and Synthesis ●DSP Servo Control●Spectrum Analysis
Beneits and Features●14-Bit Resolution●2.9µs Conversion Time/308ksps Throughput●400ns Acquisition Time●Low Noise and Distortion 78d8 SINAD -85dB THD●±5V Bipolar Input Range, Overvoltage Tolerant to
±15V●210mW Power Dissipation●Continuous-Conversion Mode Available●30ppm/°C, -5V Internal Reference●Interfaces to DSP Processors●16-Pin DIP and SO Packages,
20-Pin SSOP Package
Ordering Information appears at end of data sheet.For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX121.related.
DAC
SAR
AIN
3kΩ
TRACK/HOLD
CONTROL LOGIC
MAX121BUFFER
7pF
REFERENCE
SAMPLING
COMPARATOR
-5V
VDD
VSS
AGND
DGND
SDATA
SCLK
FSTRT
SFRM
CONVSTCSMODEINVCLKINVFRM
3kΩ
VREF
CLIKIN
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Functional Diagram
EVALUATION KIT AVAILABLE
VDD to DGND . ........................................................-0.3V to +6V
VSS to DGND ........................................................+0.3V to -17V
AIN to AGND .......................................................................±15V
AGND to DGND .................................................................±0.3V
Digital Inputs to DGNO .............................-0.3V to (VDD + 0.3V)
(CS, CONVST, MODE, CLKIN, INVCLK, INVFRM)
Digital Outputs to DGND .........................+0.3V to (VDD + 0.3V)
(SFRM, FSTRT, SCLK, SDATA)
Continuous Power Dissipation (TA = +70°C)
16-Pin PDIP (derate 10.53mW/°C above +70°C) .........842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW
20-Pin SSOP (derate 8.00mW/°C above +70°C)..........640mW
Operating Temperature Ranges
MAX121C_ ..........................................................0°C to +70°C
MAX121E_ ......................................................-40°C to +85°C
Storage Temperature Range ...........................-65°C to + 160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = 4.75V to 5.25V, VSS = -10.8V to -15.75V, fCLK = 5.5MHz, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC PERFORMANCE (fS = 308kHz, VAIN = 10VP-P, 50kHz)Signal-to-Noise RatioSINADIncluding distortionMAX121C7578dBMAX121E7377
Total Harmonic DistortionTHDFirst ive harmonics-85-77dB
Spurious-Free Dynamic RangeSFDR7786dB
ACCURACYResolutionRES14Bits
Differential Nonlinearity (Note 1)DNL12 bits no missing codes over temperature
range±1.5LSB
Integral NonlinearityINL±2LSB
Bipolar Zero Error
Code 00..00 to 00..01 transition,
near VAIN = 0V±10mV
Temperature drift±1ppm/°C
Full-Scale Error (Notes 1, 2)Including reference; adjusted for bipolar
zero error; TA = +25°C±0.2%
Full-Scale Temperature DriftExcluding reference±1ppm/°C
Power-Supply Rejection
VDD only, 5V ±5%±1/2±2
LSBVSS only, -12V ±10%±1±2
VSS only, -15V ±5%±1±2
ANALOG INPUTInput Range-5+5V
Input CurrentVAIN = 5V (RIN approximately 6kW to REF)2.5mA
Input Capacitance (Note 3)10pF
Full-Power Bandwidth1.5MHz
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = 4.75V to 5.25V, VSS = -10.8V to -15.75V, fCLK = 5.5MHz, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REFERENCEOutput VoltageNo external load, VAIN = 5V, TA = +25°C-5.02-4.98V
External Load Regulation0mA < ISINK < 5mA, VAIN = 0V5mV
Temperature Drift (Note 4)±30ppm/°C
CONVERSION TIMESynchronoustCONV16 tCLK2.91µs
Clock FrequencyfCLK0.15.5MHz
DIGITAL INPUTS (CLKIN, CONVST, CS)Input High VoltageVIH2.4V
Input Low VoltageVIL0.8V
Input Capacitance (Note 3)10pF
Input CurrentVDD = 0V or VDD±5µA
DIGITAL OUTPUTS (SCLK, SDATA, FSTRT, SFRM)Output Low VoltageVOLISINK = 1.6mA0.4V
Output High VoltageVOHISOURCE = 1mAVDD - 0.5V
Leakage CurrentILKGVOUT = 0V or VDD±5µA
Output Capacitance (Note 3)10pF
POWER REQUIREMENTSPositive Supply Voltage VDDBy supply rejection test4.755.25V
Negative Supply VoltageVSSBy supply rejection test-10.8-15.75V
Positive Supply CurrentIDDVDD = 15.25V, VSS = -15.75V, VAIN = 0V,
VCS = VCONVST = VMODE = 5V915mA
Negative Supply CurrentISSVDD = 15.25V, VSS = -15.75V, VAIN = 0V,
VCS = VCONVST = VMODE = 5V1420mA
Power DissipationVDD = 15.25V, VSS = 12V, VAIN = 0V,
VCS = VCONVST = VMODE = 5V213315mW
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Electrical Characteristics (continued)
(VDD = 5V, VSS = -12V or -15V, TA = TMIN to TMAX, unless otherwise noted.) (Note 5)
Note 1: These tests are performed at VDD = +5V. VSS = -15V. Operation over supply is guaranteed by supply-rejection tests.
Note 2: Ideal full-scale transition is at +5V - 3/2 LSB = +4.9991V adjusted for offset error.
Note 3: Guaranteed, not tested.
Note 4: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as
TC = (ΔVREF/VREF)/ΔT.
Note 5: Control inputs specified with tr = tf = 5ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For a data-hold time, a change of 0.5V is measured. See Figures 4
and 5 for load circuits.
Note 6: Guaranteed, not tested.
PARAMETERSYMBOLCONDITIONS
TA = +25°C MAX121C/EMAX121M
UNITSMINTYPMAXMINTYPMAXMINTYPMAXCONVST Pulse
Width (Note 6)tCW203035ns
Data-Access TimetDACL = 50pF25506580ns
Data-Hold TimetDH25506580ns
CLKIN to SCLKtCDCL = 50pF406585105ns
SCLK to SDATA
SkewtSCCL = 50pF±65±80±100ns
SCLK to SFRM or
FSTRT SkewtSCCL = 50pF±25±35±40ns
Acquisition Time
(Note 6)tAQ400400400ns
Aperture DelaytAP10ns
Aperture Jitter30ns
Clock Setup/Hold
TimetCK105010501050ns
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Timing Characteristics
PINNAMEFUNCTION
PDIP/SOSSOP1VSSNegative Power Supply, -12V or -15V. Bypass to AGND with 10µF and 0.1µF capacitors.2VDDPositive Power Supply, +5V. Bypass to AGND with 10µF and 0.1µF capacitors.3AINSampling Analog Input, ±5V Bipolar Input Range4VREF-5V Reference Output. Bypass to AGND with 22µF || 0.1µF capacitors.7AGNDAnalog Ground8INVCLKInvert Serial Clock. Connect to DGND to invert the SCLK output (relative to CLKIN).9INVFRM
Invert Serial Frame. This input sets the polarity of the SFRM output as follows:
If INVFRM = DGND, SFRM is high during a conversion.
If INVFRM = VDD, SFRM is low during a conversion.10DGNDDigital Ground11SFRMSerial Frame Output. Normally high (INVFRM = VDD), falls at the beginning of the
conversion and rises at the end (after 16 tCLK) signaling the end of a 16-bit frame.12FSTRTFrame Start Output. High pulse that lasts one clock cycle, falling edge indicates that a valid
MSB is available.13SDATASerial Data Output. MSB irst, two’s-complement binary output code.14SCLKSerial Clock Output. Same polarity as CLKIN if INVCLK = VDD, inverted CLKIN if
INVCLK = DGND. Note that SCLK runs whenever CLKIN is active.17CONVSTActive-Low Convert Start Input. Conversions are initiated on falling edges.18CLKINClock Input. Supply at TTL-/CMOS-compatible clock from 0.1MHz to 5.5MHz, 40% to 60%
duty cycle.19CSActive-Low Chip Select Input. CS = DGND enables the three-state outputs. Also, if
CONVST is low, initiates a conversion on the falling edge of CS.20MODEHardwire to set operational mode. VDD (single conversions),
DGND (continuous conversions).
AIN
VREFCONVST
VSS
VDDCS
CLKIN
MODE
PDIP/SOTOP VIEW
INVFRM
DGNDSFRM
AGND
INVCLKSDATA
FSTRT
SCLK
MAX12120
MODE
CLKIN
CONVSTVREF
AIN
VDD
VSS
N.C.
N.C.
SDATAINVCLK
N.C.7SCLKAGND10SFRMDGND9FSTRTINVFRM
N.C.
SSOP
MAX121MAX121308ksps ADC with DSP Interface and 78dB SINAD
Pin Description
Pin Conigurations
Detailed Description
ADC OperationThe MAX121 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog signal to a
14-bit serial digital output code. The control logic interfac-
es easily to most microprocessors (µPs) and digital signal
processors (DSPs), requiring only a few passive com-
ponents for most applications. The T/H does not require
an external capacitor. Figure 1 shows the MAX121 in its
simplest operational configuration.
Analog Input Track/HoldThe Equivalent Input Circuit (Figure 2) illustrates the sampling architecture of the ADC’s analog comparator.
An internal buffer charges the hold capacitor to minimize
the required acquisition time between conversions. The analog input appears as a 6kΩ resistor in parallel with a
10pF capacitor.
Between conversions, the buffer input is connected to AIN
through the input resistance. When a conversion starts,
the buffer input is disconnected from AIN, thus sampling
the input. At the end of the conversion, the buffer input
is reconnected to AIN, and the hold capacitor tracks the
input voltage.
The T/H is in its tracking mode whenever a conversion is
a conversion is initiated (aperture delay). The variation in
this delay from one conversion to the next (aperture jitter)
is typically 30ps. Figures 7–9 detail the track/hold mode
and interface timing for the three different interface modes.
lntemal ReferenceThe MAX121 -5.00V buried-zener reference biases the
internal DAC. The reference output is available at the
VREF pin and must be bypassed to the AGND pin with a
0.1µF ceramic capacitor in parallel with a 22µF or greater electrolytic capacitor. The electrolytic capacitor’s equiva-lent series resistance (ESR) must be 100mΩ or less to properly compensate the reference output buffer. Sanyo’s
organic semiconductor capacitors work well; telephone
and FAX numbers are provided below.
Sanyo Video Components (USA) Phone: (619) 661-6835FAX: (619) 661-1055
Sanyo Electric Company, LTD. (Japan) Phone: 0720-70-1005FAX: 0720-70-1174
Sanyo Fisher Vertriebs GmbH (Germany) Phone: 06102-27041, ext. 44
Figure 1. MAX121 in the Simplest Operational Mode
(Continuous-Conversion Mode)
Figure 2. Equivalent Input Circuit
AIN
VREFCONVST
VSS
VDDCS
CLKIN
MODE
INVFRM
DGND
AGND
SERIAL
PORT
DGND
DGND
10µF
10µF
22µF
0.1µF
0.1µF
0.1µF
AGND
AGND
AGND
DGND
-12V/-15V
+5V
ANALOG
INPUT
VDD
CLOCK
INPUT
INVCLKSDATA
FSTRT
SCLK
MAX121DAC
SAR
AIN
VREF
VREF
(-5V)
CPACKAGE
10pF
CSWITCH
2pF
CHOLD
7pF
SAMPLING
COMPARATOR
3kΩ
3kΩ
HOLD
TRACKBUFFER
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Proper bypassing minimizes reference noise and main-
tains a low impedance at high frequencies. The internal-
reference output buffer can sink up to 5mA from an
external load.
An external reference voltage can be used to overdrive the MAX121’s internal reference, if the external reference
lies within the range from -5.05V to -5.10V. The external
reference must be capable of sinking a minimum of 5mA.
The external VREF bypass capacitors are still required.
External ClockThe MAX121 requires a TTL-/CMOS-compatible clock
for proper operation. The MAX121 accepts clocks in the
frequency range from 0.1MHz to 5.5MHz when operating
in mode 1 or mode 2 (see the Operating Modes section).
To satisfy the 400ns acquisition-time requirement with 2
clock cycles, the maximum clock frequency is limited to
5MHz when operating in mode 3 (continuous-conversion
mode). The minimum clock frequency in all modes is lim-
ited to 0.1MHz due to the droop rate of the internal T/H.
Output Data FormatThe conversion result is output as a 16-bit serial data
stream, starting with the 14 data bits (MSB first) followed by 2 trailing zeros. The format of the output data is two’s-
complement binary. Data is clocked out of the SDATA pin
on the rising edge of CLKIN.
The output data can be framed using either the FSTRT or
the SFRM output. FSTRT (normally low) goes high for 1
clock cycle preceding the MSB. A falling edge on FSTRT
indicates that the MSB is available on the SDATA output.
The SFRM output (normally high when INVFRM = VDD)
goes low coincident with the MSB appearing at the
SDATA pin. SFRM returns high 16 clock cycles later. The
polarity of SFRM can be inverted by tying the INVFRM
input to DGND. A minimum of 18 clock cycles per conver-
sion is required to obtain a valid SFRM output.
See Figure 3 for the data-access and data-hold timing
diagram if several devices share the serial bus. The
equivalent load circuits for data-access and data-hold tim-
ing are shown in Figures 4 and 5.
Digital InterfaceThe MAX121 serial interface is compatible with SPI and
QSPI serial interfaces. In addition, two framing signals
(FSTRT and SFRM) are provided to allow the MAX121
to easily interface to most digital-signal processors (DSP)
with no external glue logic. The INVCLK input inverts the
phase of SCLK relative to CLKIN, and the INVFRM input
inverts the phase of the SFRM output. These control
signals allow the MAX121 to directly interface to devices
with many different serial-interface standards. Specific
information for interfacing the MAX121 with SPI, QSPI,
and several DSP devices is included in the Applications
Information section.
Figure 3. Data-Access + Data-Hold Timing
Figure 5. Load Circuits for Data-Hold Time
SDATA, SCLK,
SFRM + FSTRTHIGH
IMPEDEANCE
HIGH
IMPEDEANCEOUTPUTS ENABLED
tDAtDH
SERIAL
OUTPUTS
SERIAL
OUTPUTS
3kΩ
3kΩCL
+5V
DGND
b. HIGH-Z TO VOL (tDA)a. HIGH-Z TO VOH (tDA)
DGND
SERIAL
OUTPUTS
SERIAL
OUTPUTS
3kΩ
3kΩ
10pF10pF
+5V
DGND
b. VOL TO HIGH-Z (tDH)a. VOH TO HIGH-Z (tDH)
DGND
CONVSTADC
BUSY
START
CONVERSION
ENABLE
DIGITAL
OUTPUTS
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Timing and ControlThe MAX121 has three possible modes of operation, as
outlined in the timing diagrams of Figures 7–9 and dis-
cussed in the Operating Modes section.
In Mode 1, the CONVST input is used to control the start
of the conversion. Mode 1 is intended for DSP and other
applications where the analog input must be sampled at
a precise instant in time.
In Mode 2, the CS input controls the start of the conver-
sion. This mode is useful when several devices are mul-
tiplexed on the same serial data bus, since the MAX121
outputs are placed in a high-impedance state when CS is
pulled high.
Mode 3 is the continuous-conversion mode. This mode
is intended for data logging and similiar applications
where the MAX121 is directly linked to memory through
a first-in/first-out (FIFO) buffer or a direct memory access
(OMA) port.
In all three operating modes, the start of conversion is
controlled by either the CS or the CONVST input. Both of
these inputs must be low for a conversion to take place.
Figure 6 shows the logic equivalent for the conversion
circuitry. Once the conversion is in progress, it cannot be
restarted.
Operating Modes
Mode 1: CONVST Controls Conversion Starts (MODE = VDD, CS = DGND)Figure 7 shows the timing diagram for mode 1. In this
mode, conversion start operations are controlled by the
CONVST input.
A falling edge on the CONVST input places the T/H into
the hold mode and starts a conversion in the successive
approximation register (SAR). The FSTRT (normally
low) output goes high on the next rising clock edge and
remains high for one clock cycle. On the next rising clock
edge, FSTRT goes low and the SFRM output goes low
(INVFRM = VDD), indicating that the MSB is ready to be
latched. SFRM remains high for 16 clock cycles ( 4 data
bits plus 2 trailing zeros).
The T/H amplifier returns to the track mode when the 14th
bit (D0) is clocked out of the SDATA pin. A new conver-
sion can be initiated by the CONVST input after the 400ns
minimum acquisition time has been satisfied.
CS must be low to start a conversion. In applications
where the MAX121 interfaces with a dedicated serial port,
CS can be hardwired to DGND. To interface the MAX121
to a multiplexed serial bus, CS can be externally driven
low to enable conversions, or driven high to place the
serial outputs into a high-impedance state.
CONVST
CLKIN1
MSB
* THESE CLOCK CYCLES MAY BE OMITTED IF THE SFRM SIGNAL IS NOT NEEDEDLSB1516*17*1516*
SFRM
(INVFRM = VDD)
SCLK
(INVCRM = VDD)
FSTRT
SDATA
HOLD
TRACK
T/H
tAP
tCD
tCW
tAQ
17*
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Mode 2: CS Controls Conversion Starts (MODE = VDD, CONVST = DGND)Figure 8 shows the timing diagram for mode 2. In mode
2, CS controls the conversion start and enables the serial
output pins. Mode 2 is useful in applications where the
MAX121 shares the output data bus with other devices.
When CS is driven high, the MAX121 is disabled and its
serial outputs (SCLK, SDATA, SFRM, and FSTRT) are
placed into a high-impedance state.
A falling edge on the CS input places the T/H into the hold
mode and starts a conversion in the SAR. The FSTRT
and SFRM outputs can be used to frame the output data
as described in the mode 1 section. CS must remain low
for the duration of the conversion.
The T/H amplifier returns to the track mode when the 14th
bit (D0) is clocked out of the SDATA pin. A new conversion
can be initiated by the CS input after the 400ns acquisition
time has been satisfied.
Mode 3: Continuous-Conversion Mode (CONVST = CS = MODE = DGND)For applications that do not require precise control of
sampling in time, such as data logging, the MAX121 can
operate in continuous-conversion mode, directly linked to
memory through DMA ports or a FIFO buffer.
In this mode, conversions are performed continuously
at the rate of one conversion for every 16 clock cycles,
which includes 2 clock cycles for the T/H acquisition time.
To satisfy the 400ns minimum acquisition-time require-
ment within 2 clock cycles, the MAX121 ‘s maximum clock
frequency is limited to 5MHz when operating in mode 3.
The FSTRT output is used to frame data, as described
in the mode 1 section and the mode 3 timing diagram
(Figure 9). The SFRM output is meaningless in mode 3,
since it will not change state.
The MODE input should be hardwired to DGND, since
this input must be low when the MAX121 powers up
for proper operation of mode 3. To disable conversions,
drive CONVST high. To put the serial outputs into a high-
impedance state, drive CS high.
Figure 8. CS Controls Conversion Starts (Mode 2)
CLKIN
SFRM
(INVFRM = VDC)
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
HIGH
IMPENDANCE
SCLK
(INVCLK = VDC)
FSTRT
SDATA
HOLD
tAP
tCD13141516*17*
17*16*1514131
MSBD2D1LSB
T/H
* THESE CLOCK CYCLES MAY BE OMITTED IF THE SFRM SIGNAL IS NOT NEEDED
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Applications Information
Initialization After Power-UpUpon power-up, the first conversion of the MAX121 will be
valid if the following conditions are met:
1) Allow 16 clock cycles for the internal T/H to enter the
track mode, plus a minimum of 400ns in the track
mode for the data-acquisition time.
2) Make sure the reference voltage has settled. Allow
0.5ms for each 1µF of reference bypass capacitance
11ms for a 22µF capacitor.
Clock and Control SynchronizationIf the clock and conversion start inputs (CONVST or CS—
see the Operating Modes section) are not synchronized,
the conversion time can vary from 15 to 16 clock cycles.
The SAR always changes state on the rising edge of
the CLKIN input. To ensure a fixed conversion time, see
Figure 10 and the following guidelines.
For a conversion time of 15 clock cycles, the conversion
start input(s) should go low at least 50ns before the next
rising edge of CLKIN. For a conversion time of 16 clock
cycles, the conversion start input(s) should go low within
10ns of the next rising edge of CLKIN. If the conversion
start input(s) go low from 10ns of the next rising edge of
CLKIN. If the conversion start input(s) go low from 10ns
to 50ns before the next rising edge of CLKIN, the number
of clock cycles required is undefined and can be either 15
or 16. For best analog performance, the conversion start
inputs must be synchronized with CLKIN.
Figure 10. Clock and Control Synchronization
Figure 9. Continuous-Conversion Mode (Mode 3)
ICK
CONVST OR CS
CLKIN
THE TIMING RELATIONSHIP BETWEEN CLKIN AND CONVST OR CS DETERMINES IF A
CLOCK CYCLE SLIPS OR NOT. USE THE FOLLOWING:IF tCK < 10ns, CONVERSION TIME = 16 CLOCK EDGESIF tCK > 50ns, CONVERSION TIME = 15 CLOCK EDGESIF 10ns < tCK < 50ns, CONVERSION TIME IS INDETERMINATE (15 OR 16)
CLKIN
FSTRT
SDATA
T/H
LSB161131415161
tAQ1131415161
MSBD2D1LSB
HOLD
TRACK
SCLK
(INVCLK = VCD)
MSB
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Maximum Clock Rate tor Serial InterfaceThe maximum serial clock rate depends upon the mini-mum setup time required by the receiving processor’s serial data input and the ADC’s maximum clock-to-data
delay. The MAX121 allows two fundamentally different
methods of clocking data into the processor. In the first
clocking method, CLKIN is both the input clock to the
MAX121 and the serial clock for the processor. With the
second method, CLKIN is the input clock for the MAX121
while SCLK is the serial clock for shifting data into the
processor (see Figure 11).
The first method would generally be used with simple
serial-interface standards (such as SPI) where the pro-
cessor does not support asynchronous data transfers.
The maximum clock-to-data delay would be tCD + tSC.
For this case, calculate the maximum serial clock rate
with the following formula:
fCLKIN = (1/2) x 1/(tSU + tCD + tSC)
where tSU is the minimum data setup time required at the
processor serial data input, tCD is the maximum CLKIN
to-SCLK delay of the MAX121, and tSC is the maximum
SCLK-to-SDATA delay for the MAX121.
The second type of interface is intended for applications
where the processor supports asynchronous data trans-
fers. The SCLK output of the MAX121 drives the serial
clock of the processor, eliminating the tCD term from the
above equation and allowing the use of faster clocks. For
this case, calculate the maximum serial clock rate with the
following formula:
fCLKIN = (1/2) x 1/(tSU + tSC)
where the variables are as defined above.
Motorola SPI Serial Interface (CPOL = 0, CPHA = 1)Figure 13 shows the MAX121 and processor interface
connections required to support the SPl standard. Figure
12 shows the SPI interface timing diagram. For SPI inter-
faces, the processor SS input should be pulled high, to
configure the processor as the master. An I/O port from
the processor drives the MAX121 CONVST (mode 1) or
CS (mode 2) low to control the conversion starts. The
SCK output of the processor will drive the CLKIN of the
MAX121. The MISO I/O of the processor is driven by the
SDATA output of the MAX121.
The SPI standard requires that all data transfers occur
in blocks of 8 bits, but the MAX121 outputs data in
16-bit blocks. Therefore, two 1-byte read operations are
required to receive the full 14 data bits from the MAX121.
A conversion is initiated by driving the processor I/O port
low. Next, a write operation must be performed by the
processor to activate the serial clock and read the first 8
bits of data from the MAX121.
The MAX121 output data transitions on the rising edge of
the clock. The processor reads data on the falling edge of
the clock (CPHA = 1). This provides one half clock cycle
to satisfy the minimum setup and hold time requirement
of the processor data input. The maximum clock rate for
SPI interfaces is 2MHz.
The first byte of data read by the processor will consist of
a leading zero followed by the 7 MSBs of data. A second
write operation should then be initiated to read the second
byte of data, which contains the 7 LSBs of conversion
data followed by a trailing zero. To minimize errors due to
the droop of the MAX121 internal T/H, limit the maximum
time delay between the conversion start and the end of
the second read operation to no more than 160µs.
CLKIN
SCLK
(INVCLK = VDD)
SDATA FSTRT
SFRM
* tSS CAN BE POSITIVE OR NEGATIVE
tSC*
tCDtCD
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Motorola QSPI Serial Interlace(CPOL = 0, CPHA = 1)Figure 14 shows the connections required to implement a
QSPI interface with the MAX121. The timing diagram for
this interface is shown in Figure 15. The QSPI standard
is similiar to SPI, with the primary differences as follows:
1) QSPI allows arbitrary length data transfers from 8
to 16 bits, so only one read operation is required to
receive the 14 bits of output data from the MAX121.
2) QSPI allows clock rates up to 4MHz, compared to
2MHz with SPI.
ADSP2101 Serial InterlaceFigure 16 shows the connections required to interface the MAX121 to Analog Devices’ ADSP2101 DSP. Figure 17
is a plot of the timing diagram. The ADSP2101 has a high-
speed serial interface with a minimum serial data setup
time of 10ns (tSCS) and a minimum data-hold time of 10ns
(tSCH). This interface permits operation of the MAX121 at
its maximum clock rate of 5.5MHz.
An output port of the ADSP2101 drives the MAX121
CONVST input low to initiate a conversion. The SFRM
output of the MAX121 drives the RFS (Receive Frame
Synchronization) input to the DSP low to indicate that the
MSB has been shifted out of the MAX121 SDATA pin. On
the next falling edge on SCLK, the MSB is shifted into the
ADSP2101 serial input. Note that the MAX121 INVFRM
input is grounded to provide the proper phase for the
SFRM output.
The SCLK terminal of the ADSP2101 is configured as an
input and is driven by the MAX121 SCLK output to clock
data into the DSP. The SFRM output remains low for 16
clock cycles, allowing the 14 data bits to be shifted into
the ADSP2101, followed by 2 trailing zeros.
Figure 12. SPI Interface Timing Diagram
Figure 13. SPI Interface CircuitFigure 14. QSPI Interface Circuit
CLKIN
1ST BYTE READ2
MSBD12D11D10D9D8D7D6D5D4D3D2D1D04567812345678
2ND BYTE READ
CONVST
SDATA
LEADING
ZERO
TRAILING
ZERO
CLKIN12345678910111213141516
MSBD12D11D10D9D8D7D6D5D4D3D2D1LSB
CONVST
SDATA
TRAILING
ZERO
LEADING
ZERO
I/OCONVST
CPOL = 0
CPHA = 1
PROCESSORMAX121SCK
INVFRM
INVCLKCLKIN
+5V
MISOSDATACS
DGND
I/OCONVST
CPOL = 0
CPHA = 1
PROCESSORMAX121SCK
INVFRM
INVCLKCLKIN
+5V
MISOSDATACS
DGND
MAX121308ksps ADC with DSP Interface and 78dB SINAD
Figure 17. ADSP2101 Interface Timing Diagram
Figure 18. NEC µP077230 Interlace Circuit
Figure 16. ADSP2101 to MAX121 Interface
CLKIN1214151617
LSBMSB
tSCStSCH
CONVST
SCLK
(INVCLK = VCC)12
D12D1151617
SFRM
(INVFRM = GND)
SDATACONVST
µPD77230MAX121SCLKSCLK
SIEN
SFRM
CONVST
CLKIN
OSC
INVFRM
INVCLK
DGND
+5V
DMS OR PMSCONVST
ADSP2101MAX121SCLKSCLK
RFSINVFRM
SFRM
SDATA
CLKIN
OSC0.1MHz ≤ f ≤ 5.5MHz
INVCLK
DGND
+5V
MAX121308ksps ADC with DSP Interface and 78dB SINAD
