MAX1215EGK+D ,1.8V, 12-Bit, 250Msps ADC for Broadband ApplicationsELECTRICAL CHARACTERISTICS(AV = OV = 1.8V, AGND = OGND = 0, f = 250MHz, differential sine-wave cloc ..
MAX121CAP ,308Ksps ADC with DSP Interface and 78dB SINADELECTRICAL CHARACTERISTICS
(an = 4.75V to S25V, vss = -10 EVto -1575V,MAX121C/EfcLN = 5.5MHz, MAX1 ..
MAX121CAP ,308Ksps ADC with DSP Interface and 78dB SINADGeneral Description
The MAX121 is a complete, BiCMOS, serial-output, sam-
pling 14-bit analog-t ..
MAX121CAP+ ,308ksps ADC with DSP Interface and 78dB SINADElectrical Characteristics(V = 4.75V to 5.25V, V = -10.8V to -15.75V, f = 5.5MHz, T = T to T , unle ..
MAX121CPE ,308Ksps ADC with DSP Interface and 78dB SINADELECTRICAL CHARACTERISTICS
(an = 4.75V to S25V, vss = -10 EVto -1575V,MAX121C/EfcLN = 5.5MHz, MAX1 ..
MAX121CPE ,308Ksps ADC with DSP Interface and 78dB SINADFeatures
. 14-Bit Resolution
. 2.9ps Conversion Timel308ksps Throughput
. 400ns Acquisition Ti ..
MAX351CPE ,Precision, Quad, SPST Analog Switches
MAX351CPE+ ,Precision, Quad, SPST Analog Switches
MAX351CSE ,Precision, Quad, SPST Analog Switches
MAX351CSE ,Precision, Quad, SPST Analog Switches
MAX351CSE+ ,Precision, Quad, SPST Analog Switches
MAX351ESE ,Precision, Quad, SPST Analog Switches
MAX1215EGK+D
1.8V, 12-Bit, 250Msps ADC for Broadband Applications
General DescriptionThe MAX1215 is a monolithic, 12-bit, 250Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies up to
300MHz. The product operates with conversion rates
up to 250Msps while consuming only 975mW.
At 250Msps and an input frequency up to 250MHz, the
MAX1215 achieves a spurious-free dynamic range
(SFDR) of 72.4dBc. Its excellent signal-to-noise ratio
(SNR) of 66dB at 10MHz remains flat (within 2dB) for
input tones up to 300MHz. This ADC yields an excellent
low noise floor of -67.5dBFS, which makes it ideal for
wideband applications such as cable-head end
receivers and power-amplifier predistortion in cellular
base-station transceivers.
The MAX1215 requires a single 1.8V supply. The analog
input is designed for either differential or single-ended
operation and can be AC- or DC-coupled. The ADC also
features a selectable on-chip divide-by-2 clock circuit,
which allows the user to apply clock frequencies as high
as 340MHz. This helps to reduce the phase noise of the
input clock source. A low-voltage differential signal
(LVDS) sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible and the data format can be selected to be either
two’s complement or offset binary.
The MAX1215 is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versionstable for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family (with or without input buffers).
ApplicationsBase-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
Features250Msps Conversion RateLow Noise Floor of -67.5dBFSExcellent Low-Noise Characteristics
SNR = 65.5dB at fIN= 100MHz
SNR = 65dB at fIN= 250MHzExcellent Dynamic Range
SFDR = 70.7dBc at fIN= 100MHz
SFDR = 72.4dBc at fIN= 250MHz65.4dB NPR for fNOTCH= 28.8MHz and a Noise
Bandwidth of 50MHzSingle 1.8V Supply1006mW Power Dissipation at fSAMPLE= 250MHz
and fIN= 100MHzOn-Chip Track-and-Hold AmplifierInternal 1.24V-Bandgap ReferenceOn-Chip Selectable Divide-by-2 Clock InputLVDS Digital Outputs with Data Clock OutputMAX1215 EV Kit Available
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
PARTTEMP RANGEPIN-PACKAGEMAX1215EGK-D-40°C to +85°C68 QFN-EP*
MAX1215EGK+D-40°C to +85°C68 QFN-EP*
Pin-Compatible Versions
Ordering Information
PARTRESOLUTION
(BITS)
SPEED GRADE
(Msps)
ON-CHIP
BUFFERMAX11218250Yes
MAX112210170Yes
MAX112310210Yes
MAX112410250Yes
MAX121312170Yes
MAX121412210Yes
MAX121512250Yes
MAX1213N12170No
MAX1214N12210No
MAX1215N12250No
19-3653; Rev 1; 9/06
*EP = Exposed paddle.
+Denotes lead-free package.= Dry pack.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND.....................................................-0.3V to +2.1V
OVCCto OGND....................................................-0.3V to +2.1V
AVCCto OVCC......................................................-0.3V to +2.1V
AGND to OGND...................................................-0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AVCC + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V)
REFIO, REFADJ to AGND........................-0.3V to (AVCC + 0.3V)
All Digital Outputs to OGND....................-0.3V to (OVCC + 0.3V)
Continuous Power Dissipation (TA= +70°C, multilayer board)
68-Pin QFN-EP (derate 41.7mW/°C
above +70°C)...........................................................3333mW/°C
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Maximum Current into Any Pin............................................50mA
Lead Temperature (soldering,10s)..................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution12Bits
Integral Nonlinearity (Note 2)INLfIN = 10MHz, TA = +25°C-2±0.85+2LSB
Differential Nonlinearity (Note 2)DNLTA = +25°C, no missing codes-1±0.5+1LSB
Transfer Curve OffsetVOSTA = +25°C (Note 2)-3.5+3.5mV
Offset Temperature Drift40µV/°C
ANALOG INPUTS (INP, INN)Full-Scale Input Voltage RangeVFSTA = +25°C (Note 2)132014541590mVP-P
Full-Scale Range Temperature
Drift130ppm/°C
Common-Mode Input RangeVCMInternally self-biased1.365 ±0.15V
Input CapacitanceCIN2.5pF
Differential Input ResistanceRIN3.04.26.3kΩ
Full-Power Analog BandwidthFPBW700MHz
REFERENCE (REFIO, REFADJ)Reference Output VoltageVREFIOTA = +25°C, REFADJ = AGND1.181.231.30V
Reference Temperature Drift90ppm/°C
REFADJ Input High VoltageVREFADJUsed to disable the internal referenceAVCC - 0.3V
SAMPLING CHARACTERISTICSMaximum Sampling RatefSAMPLE250MHz
Minimum Sampling RatefSAMPLE20MHz
Clock Duty CycleSet by clock-management circuit40 to 60%
Aperture DelaytADFigures 4, 11620ps
Aperture JittertAJFigure 110.2psRMS
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CLOCK INPUTS (CLKP, CLKN)Differential Clock Input Amplitude(Note 3)200500mVP-P
Clock Input Common-Mode
Voltage RangeInternally self-biased1.15 ±0.25V
Clock Differential Input
ResistanceRCLK11
±25%kΩ
Clock Differential Input
CapacitanceCCLK5pF
DYNAMIC CHARACTERISTICS (at -1dBFS)fIN = 10MHz, TA ≥ +25°C63.566
fIN = 100MHz, TA ≥ +25°C63.465.5
fIN = 200MHz 65.5
Signal-to-Noise
RatioSNR
fIN = 250MHz65
fIN = 10MHz, TA ≥ +25°C63.565.8
fIN = 100MHz, TA ≥ +25°C6264.3
fIN = 200MHz 63.2
Signal-to-Noise
and DistortionSINAD
fIN = 250MHz 64.2
fIN = 10MHz, TA ≥ +25°C7084
fIN = 100MHz, TA ≥ +25°C6770.7
fIN = 200MHz67.1
Spurious-Free
Dynamic RangeSFDR
fIN = 250MHz72.4
dBc
fIN = 10MHz, TA ≥ +25°C-87-70
fIN = 100MHz, TA ≥ +25°C-70.7-67
fIN = 200MHz-67.1
Worst Harmonics
(HD2 or HD3)
fIN = 250MHz-72.4
dBc
Two-Tone Intermodulation
DistortionTTIMDfIN1 = 99MHz at -7dBFS,
fIN2 = 101MHz at -7dBFS -79dBc
Noise-Power RatioNPRfNOTCH = 28.8MHz ±1MHz,
noise BW = 50MHz, AIN = -9.1dBFS 65.4dB
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)Differential Output Voltage|VOD|RL = 100Ω ±1%250400mV
Output Offset VoltageOVOSRL = 100Ω ±1%1.1251.310V
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)Digital Input-Voltage LowVIL0.2 x AVCCV
Digital Input-Voltage HighVIH0.8 x AVCCV
TIMING CHARACTERISTICSCLK-to-Data Propagation DelaytPDLFigure 41.75ns
CLK-to-DCLK Propagation DelaytCPDLFigure 43.87ns
DCLK-to-Data Propagation DelaytPDL - tCPDLFigure 4 (Note 3)1.662.122.48ns
LVDS Output Rise TimetRISE20% to 80%, CL = 5pF460ps
LVDS Output Fall TimetFALL20% to 80%, CL = 5pF460ps
Output Data Pipeline DelaytLATENCYFigure 411Clock
cycles
POWER REQUIREMENTSAnalog Supply Voltage RangeAVCC1.701.801.90V
Digital Supply Voltage RangeOVCC1.701.801.90V
Analog Supply CurrentIAVCCfIN = 100MHz495555mA
Digital Supply CurrentIOVCCfIN = 100MHz6475mA
Analog Power DissipationPDISSfIN = 100MHz10061134mW
Offset1.8mV/VPower-Supply Rejection Ratio
(Note 3)PSRRGain1.5%FS/V
Note 1:≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2:Static linearity and offset parameters are based on the end-point fit method. The full-scale range (FSR) is defined as 4095 x
slope of the line.
Note 3:Parameter guaranteed by design and characterization: TA= TMINto TMAX.
Note 4:PSRR is measured with both analog and digital supplies connected to the same potential.
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband ApplicationsFFT PLOT
(8192-POINT DATA RECORD)
MAX1215toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)HD3
fSAMPLE =
249.99936MHz
fIN = 12.78683MHz
AIN = -1.008dBFS
SNR = 66.5dB
SINAD = 66.2dB
THD = -80.4dBc
SFDR = 83.3dBc
HD2 = -83.3dBc
HD3 = -88.4dBcHD2
FFT PLOT
(8192-POINT DATA RECORD)
MAX1215toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fSAMPLE =
249.99936MHz
fIN = 65.03279MHz
AIN = -1.083dBFS
SNR = 66.7dB
SINAD = 65.6dB
THD = -72dBc
SFDR = 73.7dBc
HD2 = -82dBc
HD3 = -73.7dBc
HD3
HD2
FFT PLOT
(8192-POINT DATA RECORD)
MAX1215toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fSAMPLE =
249.99936MHz
fIN = 199.24876MHz
AIN = -1.018dBFS
SNR = 65.5dB
SINAD = 63.2dB
THD = -67dBc
SFDR = 67.1dBc
HD2 = -89.1dBc
HD3 = -67.1dBc
HD3
HD2
FFT PLOT
(8192-POINT DATA RECORD)
MAX1215toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
HD3
fSAMPLE =
249.99936MHz
fIN = 248.62607MHz
AIN = -1.059dBFS
SNR = 65dB
SINAD = 64.2dB
THD = -71.5dBc
SFDR = 72.4dBc
HD2 = -82.1dBc
HD3 = -72.4dBc
HD2
fIN
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
MAX1215toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN1
2fIN2 - fIN1
2fIN1 - fIN2
fIN2
fSAMPLE = 249.99936MHz
fIN1 = 99.21239MHz
fIN2 = 101.1044775MHz
AIN1 = AIN2 = -7dBFS
IMD = -79dBc
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)MAX1215 toc06
fIN (MHz)
SNR/SINAD (dB)
SNR
SINAD
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)MAX1215 toc07
fIN (MHz)
SFDR (dBc)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)
MAX1215 toc08
fIN (MHz)
HD2/HD3 (dBc)
HD3
HD2
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 249.99936MHz, fIN = 65.03279MHz)MAX1215 toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR/SINAD (dB)-15-25-35-45-10-20-30-40-50
SNR
SINAD
Typical Operating Characteristics(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
Typical Operating Characteristics (continued)(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 249.99936MHz, fIN = 65.03279MHz)MAX1215 toc10
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)-15-25-35-45-10-20-30-40-50
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 249.99936MHz, fIN = 65.03279MHz)
MAX1215 toc11
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)-15-25-35-45-10-20-30-40-50
HD3
HD2
SNR/SINAD vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)MAX1215 toc12
fSAMPLE (MHz)
SNR/SINAD (dB)
SNR
SINAD
SFDR vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)MAX1215 toc13
fSAMPLE (MHz)
SFDR (dBc)
HD2/HD3 vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)
MAX1215 toc14
fSAMPLE (MHz)
HD2/HD3 (dBc)
HD3
HD2
TOTAL POWER DISSIPATION vs. SAMPLE
FREQUENCY(fIN = 65MHz, AIN = -1dBFS)MAX1215 toc15
fSAMPLE (MHz)
DISS
(mW)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1215 toc16
INL (LSB)
fIN = 13MHz
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1215 toc17
DNL (LSB)
fIN = 13MHz1001000
GAIN BANDWIDTH PLOT
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)MAX1215 toc18
GAIN (dB)
DIFFERENTIAL TRANSFORMER COUPLING
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
SNR/SINAD, SFDR vs. SUPPLY VOLTAGE
(fIN = 65.03279MHz, AIN = -1dBFS)MAX1215toc22
SUPPLY VOLTAGE (V)
SNR/SINAD, SFDR (dB, dBc)
SNR
SINAD
SFDR
AVCC = OVCC
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
MAX1215toc23
SUPPLY VOLTAGE (V)
REFIO
(V)
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
PROPAGATION DELAY TIMES
vs. TEMPERATURE
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
MAX1215toc24
tPDL
tCPDL
Typical Operating Characteristics (continued)(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
NOISE-POWER RATIO vs. ANALOG INPUT
POWER (fNOTCH = 28.8MHz ± 1MHz)
MAX1215toc25
NPR (dB)
WIDE NOISE BANDWIDTH = 50MHz
NOISE-POWER RATIO PLOT
(WIDE NOISE BANDWIDTH: 50MHz)
MAX1215toc26
NPR (dB)
fNOTCH = 28.8MHz
NPR = 65.4dB
SNR/SINAD vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
TEMPERATURE (°C)
SNR/SINAD (dB)
MAX1215toc19
SNR
SINAD
SFDR vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
TEMPERATURE (°C)
SFDR (dBc)
MAX1215toc20
HD2/HD3 vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
TEMPERATURE (°C)
HD2/HD3 (dBc)
MAX1215toc21
HD2
HD3
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
Pin Description
PINNAMEFUNCTION1, 6, 11–14, 20,
25, 62, 63, 65AVCCAnalog Supply Voltage. Bypass each pin with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGNDAnalog Converter GroundREFIO
Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference
source to be connected to the MAX1215. With REFADJ pulled low, the internal 1.23V bandgap
reference is active.REFADJ
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). If REFADJ is connected to AVCC, the internal reference can be overdriven with an
external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is
used to determine the FSR of the data converter.INPPositive Analog Input Terminal. Internally self-biased to 1.365V.INNNegative Analog Input Terminal. Internally self-biased to 1.365V.CLKDIV
Clock Divider Input. This LVCMOS-compatible input controls with which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at input clock rate.CLKPTrue Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance. Internally self-biased to 1.15V.CLKNComplementary Clock Input. This input ideally requires an LVPECL-compatible input level to
maintain the converter’s excellent performance. Internally self-biased to 1.15V.
26, 45, 61OGNDDigital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60OVCCDigital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.D0NComplementary Output Bit 0 (LSB)D0PTrue Output Bit 0 (LSB)D1NComplementary Output Bit 1D1PTrue Output Bit 1D2NComplementary Output Bit 2D2PTrue Output Bit 2D3NComplementary Output Bit 3D3PTrue Output Bit 3
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
Pin Description (continued)
PINNAMEFUNCTIOND4NComplementary Output Bit 4D4PTrue Output Bit 4D5NComplementary Output Bit 5D5PTrue Output Bit 5DCLKNComplementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.DCLKPTrue Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.D6NComplementary Output Bit 6D6PTrue Output Bit 6D7NComplementary Output Bit 7D7PTrue Output Bit 7D8NComplementary Output Bit 8D8PTrue Output Bit 8D9NComplementary Output Bit 9D9PTrue Output Bit 9D10NComplementary Output Bit 10D10PTrue Output Bit 10D11NComplementary Output Bit 11 (MSB)D11PTrue Output Bit 11 (MSB)ORNComplementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.ORPTrue Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input controls
the digital output format of the MAX1215. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format.
T/B = 1: Binary output format.
—EPExposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to analog ground for optimum performance.
MAX1215
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
Detailed Description—
Theory of OperationThe MAX1215 uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary ana-
log input terminals (INN) are centered around a 1.365V
common-mode voltage, and accept a differential ana-
log input voltage swing of ±VFS/ 4V each, resulting in a
typical 1.454VP-P differential full-scale signal swing.
Inputs INP and INN are buffered prior to entering each
T/H stage and are sampled when the differential sam-
pling clock signal transitions high.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure1 for a more detailed view of
the MAX1215 architecture.
Analog Inputs (INP, INN)INP and INN are the fully differential inputs of the
MAX1215. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for
enhanced AC performance as the signals are progress-
ing through the analog stages. The MAX1215 analog
inputs are self-biased at a 1.365V common-mode volt-
age and allow a 1.454VP-P differential input voltage
2kΩresistors, resulting in a typical differential input
resistance of 4kΩ. It is recommended to drive the ana-
log inputs of the MAX1215 in AC-coupled configuration
to achieve best dynamic performance. See the
Transformer-Coupled, Differential Analog Input Drive
section for a detailed discussion of this configuration.
MAX1215
CLOCK-
DIVIDER
CONTROL
CLKDIV
CLOCK
MANAGEMENT
INPUT
BUFFER
DCLKP
D0P/N–D11P/N
DCLKN
ORP
ORN
2.2kΩ2.2kΩ
CLKP
CLKN
INP
INN
COMMON-MODE
BUFFER
REFIOREFADJ
LVDS
DATA PORT
REFERENCE
T/H12-BIT PIPELINE
QUANTIZER
CORE
2.2kΩ
INP
2.2kΩ
AGND
COMMON-MODE
VOLTAGE (1.365V)
COMMON-MODE
VOLTAGE (1.365V)
INN
TO COMMON MODETO COMMON MODE
1.454V
P-P
DIFFERENTIAL FSR
INP
INN
AVCC
/ 4
/ 4
/ 4
/ 4
/ 2
/ 2
Figure1. MAX1215 Block Diagram
Figure2. Simplified Analog Input Architecture and Allowable
Input Voltage Range
