MAX1202BCAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interfacefeatures an internal 4.096V reference, PIN- INL while the MAX1203 requires an external reference. B ..
MAX1202BEAP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEFeaturesThe MAX1202/MAX1203 are 12-bit data-acquisition ' 8-Channel Single-Ended or 4-Channel syste ..
MAX1202BEAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceElectrical Characteristics(V = +5V ±5%, V = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external c ..
MAX1203ACAP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEMAX1202/MAX120319-1173; Rev 2; 5/985V, 8-Channel, Serial, 12-Bit ADCswith 3V Digital Interface
MAX1203ACAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceFeaturesThe MAX1202/MAX1203 are 12-bit data-acquisition sys- ● 8-Channel Single-Ended or 4-Channel ..
MAX1203AEAP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEELECTRICAL CHARACTERISTICS(V = +5V ±5%, VL = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external ..
MAX350CAP ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX350CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX350EAP+T ,Serially Controlled, Low-Voltage, 8-Channel Dual 4-Channel Multiplexers
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX3510EEP ,Upstream CATV Amplifier
MAX1202ACAP+-MAX1202ACPP+-MAX1202AEPP+-MAX1202BCAP+-MAX1202BEAP+-MAX1203ACAP+-MAX1203AEAP+
5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface
General DescriptionThe MAX1202/MAX1203 are 12-bit data-acquisition sys-
tems specifically designed for use in applications with
mixed +5V (analog) and +3V (digital) supply voltages.
They operate with a single +5V analog supply or dual ±5V
analog supplies, and combine an 8-channel multiplexer,
high-bandwidth track/hold, and serial interface with high
conversion speed and low power consumption.
A 4-wire serial interface connects directly to SPI/
MICROWIRE® devices without external logic, and a serial
strobe output allows direct connection to TMS320-family
digital signal processors. The MAX1202/MAX1203 use
either the internal clock or an external serial-interface clock
to perform successive approximation analog-to-digital con-
versions. The serial interface operates at up to 2MHz.
The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies gain
trim. They also have a VL pin that is the power supply for
the digital outputs. Output logic levels (3V, 3.3V, or 5V) are
determined by the value of the voltage applied to this pin.
These devices provide a hard-wired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power-down
between conversions, supply current can drop below 10μA at reduced sampling rates.
The MAX1202/MAX1203 are available in 20-pin SSOP
and PDIP packages, and are specified for the commercial
and extended temperature ranges.
Applications●5V/3V Mixed-Supply Systems●Data Acquisition●High-Accuracy Process Control●Battery-Powered Instruments●Medical Instruments
Features●8-Channel Single-Ended or 4-Channel Differential
Inputs●Operates from Single +5V or Dual ±5V Supplies●User-Adjustable Output Logic Levels
(2.7V to 5.25V)●Low Power: 1.5mA (Operating Mode) 2μA (Power-Down Mode)●Internal Track/Hold, 133kHz Sampling Rate●Internal 4.096V Reference (MAX1202)●SPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface●Software-Configurable Unipolar/Bipolar Inputs●20-Pin PDIP/SSOP
Typical Operating Circuit appears at end of data sheet. MICROWIRE is a registered trademark of National
Semiconductor Corp.
Ordering Information continued at end of data sheet. +Denotes a lead(Pb)-free/RoHS-compliant package.
PARTTEMP RANGEPIN-
PACKAGE
INL
(LSB)
MAX1202ACPP+0ºC to +70ºC20 PDIP±1/2
MAX1202BCPP+0ºC to +70ºC20 PDIP±1
MAX1202ACAP+0ºC to +70ºC20 SSOP±1/2
MAX1202BCAP+0ºC to +70ºC20 SSOP±1
TOP VIEW
PDIP/SSOPVDD
SCLK
DIN
SSTRB
DOUT
GND
REFADJ
REFSHDN
VSS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1202
MAX1203
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Pin Coniguration
Ordering Information
EVALUATION KIT AVAILABLE
VDD to GND ............................................................-0.3V to +6V
VL .............................................................-0.3V to (VDD + 0.3V)
VSS to GND .............................................................+0.3V to -6V
VDD to VSS ............................................................-0.3V to +12V
CH0–CH7 to GND .........................(VSS - 0.3V) to (VDD + 0.3V)
CH0–CH7 Total Input Current ..........................................±20mA
REF to GND .............................................-0.3V to (VDD + 0.3V)
REFADJ to GND .......................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND ...............................-0.3V to (VDD + 0.3V)
Digital Outputs to GND ................................-0.3V to (VL + 0.3V)
Digital Output Sink Current ................................................25mA
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 11.11mW/°C above +70°C) ....................889mW
SSOP (derate 8.00mW/°C above +70°C) ....................640mW
Operating Temperature Ranges
MAX1202_C_P/MAX1203_C_P ..........................0°C to +70°C
MAX1202_E_P/MAX1203_E_P ......................-40°C to +85°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)ResolutionRES12Bits
Relative Accuracy (Note 2)INLMAX1202A/MAX1203A±0.5LSBMAX1202B/MAX1203B±1.0
Differential NonlinearityDNLno missing codes over temperature±1.0LSB
Offset Error±3.0LSB
Gain Error (Note 3)
MAX1202 (all grades)±3
LSBExternal reference,
4.096V
MAX1203A±1.5
MAX1203B±3
Gain Temperature CoeficientExternal reference, 4.096V±0.8ppm/°C
Channel-to-Channel Offset Matching±0.1LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar-input mode)Signal-to-Noise Plus Distortion RatioSINAD70dB
Total Harmonic Distortion (up to the
5th Harmonic)THD-80dB
Spurious-Free Dynamic RangeSFDR80dB
Channel-to-Channel CrosstalkVIN = 4.096VP-P, 65kHz (Note 4)-85dB
Small-Signal Bandwidth-3dB rolloff4.5MHz
Full-Power Bandwidth800kHz
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CONVERSION RATEConversion Time (Note 5)tCONVInternal clock5.510µsExternal clock, 2MHz, 12 clocks/conversion6
Track/Hold Acquisition TimetACQ1.5µs
Aperture Delay10ns
Aperture Jitter< 50ps
Internal Clock Frequency1.7MHz
External Clock Frequency Range
External compensation mode, 4.7µF0.12.0
MHzInternal compensation mode (Note 6)0.10.4
Used for data transfer only02.0
ANALOG INPUTInput Voltage Range, Single-Ended
and Differential (Note 7)
Unipolar, VSS = 0VVREFVBipolar, VSS = -5V±VREF/2
Multiplexer Leakage CurrentOn/off-leakage current, VCH_ = ±5V±0.01±1µA
Input Capacitance(Note 6)16pF
INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)REF Output VoltageTA = +25°C4.0764.0964.116V
REF Short-Circuit Current30mA
VREF Temperature Coeficien
MAX1202AC±30±50
ppm/°CMAX1202AE±30±60
MAX1202B±30
Load Regulation (Note 8)0 to 0.5mA output load2.5mV
Capacitive Bypass at REFInternal compensation mode0µFExternal compensation mode4.7
Capacitive Bypass at REFADJ0.01µF
REFADJ Adjustment Range±1.5%
EXTERNAL REFERENCE AT REF (Reference buffer disabled, VREF = 4.096V)Input Voltage Range2.50VDD +
50mVV
Input Current200350µA
Input Resistance1220kΩ
REF Input Current in ShutdownVSHDN = 0V1.510µA
REFADJ Buffer Disable ThresholdVDD -
50mVV
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCE AT REFADJCapacitive Bypass at REFInternal compensation mode0µFExternal compensation mode4.7
Reference-Buffer GainMAX12021.68V/VMAX12031.64
REFADJ Input CurrentMAX1202±50µAMAX1203±5
POWER REQUIREMENTSPositive Supply VoltageVDD5 ±5%V
Negative Supply VoltageVSS0 or 5
±5%V
Positive Supply CurrentIDD
Operating mode1.52.5mA
Fast power-down (Note 9)3070µAFull power-down (Note 9)210
Negative Supply CurrentISSOperating mode and fast power-down50µAFull power-down10
Logic Supply VoltageVL2.705.25V
Logic Supply Current (Notes 6, 10)ILVL = VDD = 5V10µA
Positive Supply Rejection (Note 11)PSRVDD = 5V ±5%; external reference, 4.096V;
full-scale input±0.06±0.5mV
Negative Supply Rejection (Note 11)PSRVSS = -5V ±5%; external reference, 4.096V;
full-scale input±0.01±0.5mV
Logic Supply Rejection (Note 12)PSRExternal reference, 4.096V; full-scale input±0.06±0.5mV
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
(VDD = +5V ±5%, VL = 2.7V to 3.6V; VSS = 0V or -5V ±5%; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS—DIN, SCLK, CS, SHDNDIN, SCLK, CS Input High VoltageVIH2.0V
DIN, SCLK, CS Input Low VoltageVIL0.8V
DIN, SCLK, CS Input HysteresisVHYST0.15V
DIN, SCLK, CS Input LeakageIINVIN = 0V or VDD±1µA
DIN, SCLK, CS Input Capacitance CIN(Note 6)15pF
SHDN Input High VoltageVSHVDD - 0.5V
SHDN Input Mid VoltageVSM1.5VDD - 1.5V
SHDN Voltage, UnconnectedVFLTSHDN = open2.75V
SHDN Input Low VoltageVSL0.5V
SHDN Input Current, HighISHSHDN = VDD4.0µA
SHDN Input Current, LowISLVSHDN = 0V-4.0µA
SHDN Maximum Allowed Leakage,
Mid-InputSHDN = open-100+100nA
DIGITAL OUTPUTS—DOUT, SSTR (VL = 2.7V to 3.6V)Output Voltage Low VOLISINK = 3mA0.4VISINK = 6mA0.3
Output Voltage HighVOHISOURCE = 1mAVL - 0.5V
Three-State Leakage CurrentILEAKCS = VL±10µA
Three-State Output Capacitance COUTCS = VL (Note 6)15pF
DIGITAL OUTPUTS—DOUT, SSTR (VL = 4.75V to 5.25V)Output Voltage Low VOLISINK = 5mA0.4VISINK = 8mA0.3
Output Voltage HighVOHISOURCE = 1mA4V
Three-State Leakage CurrentILEAKVCS = 5V±10µA
Three-State Output Capacitance COUTVCS = 5V (Note 6)15pF
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Electrical Characteristics (continued)
Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar-input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is cali-
brated.
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (VREF = 4.096V), offset nulled.
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not production tested.
Note 7: Common-mode range for analog inputs is from VSS to VDD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on VIH (Figure 12c).
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.5µs
DIN to SCLK SetuptDS100ns
DIN to SCLK HoldtDH0ns
SCLK Fall to Output Data ValidtDOCLOAD = 100pF20240ns
CS Fall to Output EnabletDVCLOAD = 100pF240ns
CS Rise to Output DisabletTRCLOAD = 100pF240ns
CS to SCLK Rise SetuptCSS100ns
CS to SCLK Rise HoldtCSH0ns
SCLK Pulse Width HightCH200ns
SCLK Pulse Width LowtCLCLOAD = 100pF200ns
SCLK Fall to SSTRBtSSTRB240ns
CS Fall to SSTRB Output Enable
(Note 6)tSDVExternal-clock mode only, CLOAD = 100pF240ns
CS Rise to SSTRB Output Disable
(Note 6)tSTR240ns
SSTRB Rise to SCLK Rise
(Note 6)tSCK0ns
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TIMING CHARACTERISTICS
(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C, unless other-
wise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX1202 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1202
MAX1203
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1202 toc03
TEMPERATURE (ºC)
SHUTDOWN SUPPLY CURRENT (mA)
REFADJ = GND
FULL POWER-DOWN
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1202 toc04
TEMPERATURE (ºC)
INL (LSB)
OFFSET ERROR
vs. TEMPERATURE
MAX1202 toc05
TEMPERATURE (ºC)
OFFSET ERROR (LSB)
GAIN ERROR
vs. TEMPERATURE
MAX1202 toc06
TEMPERATURE (ºC)
GAIN ERROR (LSB)
DIFFERENTIAL
SINGLE-ENDED
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
MAX1202 TOC07
OFFSET-ERROR MATCHING (LSB)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1202 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX1202
MAX1203
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
MAX1202 toc08
GAIN-ERROR MATCHING (LSB)
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics
(VDD = 5V ±5%; VL = 2.7V to 3.6V; VSS = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, VREF = 4.096V applied to REF pin; TA = +25°C, unless other-
wise noted.)
PINNAMEFUNCTION1–8CH0–CH7Sampling Analog InputsVSSNegative Supply Voltage. Tie VSS to -5V ±5% or to GND.SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to VDD puts the reference-buffer ampliier in internal compensation mode. Leaving SHDN unconnected puts the reference-buffer ampliier in external compensation mode.REF
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the
reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external
reference mode, disable the internal buffer by pulling REFADJ to VDD.REFADJInput to the Reference-Buffer Ampliier. Tie REFADJ to VDD to disable the reference-buffer ampliier.GNDGround; IN- Input for Single-Ended ConversionsVLSupply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.DOUTSerial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin the analog-to-digital conversion, and goes high when the conversion is inished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is
high (external clock mode).DINSerial-Data Input. Data is clocked in at SCLK’s rising edge.CSActive-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.SCLKSerial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed (Duty cycle must be 40% to 60% in external clock mode).
INTEGRAL NONLINEARITY
vs. DIGITAL
MAX1202 toc09
DIGITAL CODE
INL (LSB)
FFT PLOT
MAX1202 toc10
FREQUENCY (kHz)
AMPLITUDE (dB)
VSS = -5V
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Typical Operating Characteristics (continued)
Pin Description
Detailed DescriptionThe MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to 3V microprocessors (μPs). Figure 3 is the MAX1202/MAX1203 block diagram.
Pseudo-Differential InputFigure 4 shows the ADC’s analog comparator’s sampling
architecture. In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to GND. In
differential mode, IN+ and IN- are selected from pairs of
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels using Tables 3 and 4.
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential such that only the signal at IN+ is sampled.
The return side (IN-) must remain stable (typically within
±0.5 LSB, within ±0.1 LSB for best results) with respect
to GND during a conversion. To do this, connect a 0.1μF
capacitor from IN- (of the selected analog input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends on
the falling SCLK edge after the input control word’s last bit
is entered. The T/H switch opens at the end of the acquisi-
tion interval, retaining charge on CHOLD as a sample of
the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input (IN+) to the nega-
tive input (IN-). In single-ended mode, IN- is simply GND.
This unbalances node ZERO at the comparator’s input.
The capacitive DAC adjusts during the remainder of the
conversion cycle to restore node ZERO to 0V within the
limits of 12-bit resolution. This action is equivalent to trans-
ferring a charge of 16pF x [(VIN+) - (VIN-)] from CHOLD to
the binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal.
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable TimeFigure 3. Block Diagram
+3.3V
3kΩ
CLOAD
GND
DOUT
CLOAD
GND
3kΩ
DOUT
a. High-Z to VOH and VOL to VOHb. High-Z to VOL and VOH to VOL
+3.3V
3kΩ
CLOAD
GND
DOUT
CLOAD
GND
3kΩ
DOUT
a. VOH to High-Zb. VOL to High-Z
INPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.44V
REFERENCE
(MAX1202)
T/HANALOG
INPUT
MUX
12-BIT
SAR
ADC
DOUT
SSTRB
VDD
VSS
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
GND
REFADJ
REF
OUT
REF
CLOCK
+4.096V
20k٪ 1.68
MAX1202
MAX1203SHDN
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Track/HoldThe T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connected
to GND if the converter is set up for single-ended inputs,
and the converter samples the “+” input. IN- connects to
the “-” input if the converter is set up for differential inputs,
and the difference of |N+ - IN-| is sampled. The positive
input connects back to IN+, at the end of the conversion,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, acquisition
time increases and more time must be allowed between
conversions. The acquisition time, tACQ, is the maximum
time the device takes to acquire the signal, and is also the
minimum time needed for the signal to be acquired. It is
calculated by the following:
tACQ = 9 x (RS + RIN) x 16pF
where RIN = 9kΩ, RS = the source impedance of the input
signal, and tACQ is never less than 1.5μs. Source imped-ances below 1kΩ do not significantly affect the ADC’s AC
performance. Higher source impedances can be used if
an input capacitor is connected to the analog inputs, as
shown in Figure 5. Note that the input capacitor forms
an RC filter with the input source impedance, limiting the
ADC’s signal bandwidth.
Figure 4. Equivalent Input Circuit
0.1µF4.7µF
VDD
GND
VSS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.***
0.01µF
CH7
REFADJ
+2.5V
REFERENCE
REF
0.01µF
4.7µF
+2.5V**
0 TO
4.096V
ANALOG
INPUT
0.1µF
+3VOSCILLOSCOPE
CH1CH2CH3CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX).
**REQUIRED FOR MAX1203 ONLY.
***NO CONNECTION
MAX1202
MAX1203+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
CSWITCH
TRACK
T/H
SWITCH
9kΩ
RIN
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE:
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Input BandwidthThe ADC’s input tracking circuitry has a 4.5MHz small-
signal bandwidth. Therefore it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Input ProtectionInternal protection diodes, which clamp the analog inputs
to VDD and VSS, allow the analog input pins to swing from
(VSS - 0.3V) to (VDD + 0.3V) without damage. However,
for accurate conversions near full scale, the inputs must
not exceed VDD by more than 50mV, or be lower than
VSS by 50mV.
If the analog input exceeds 50mV beyond the sup-plies, do not forward bias the protection diodes of off-channels more than 2mA.The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick LookUse the circuit of Figure 5 to quickly evaluate the MAX1202/
MAX1203’s analog performance. The MAX1202/MAX1203
require a control byte to be written to DIN before each con-
version. Tying DIN to +3V feeds in control byte $FF hex,
which triggers single-ended unipolar conversions on CH7
in external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for one clock period before the most signifi-
cant bit of the 12-bit conversion result shifts out of DOUT.
Varying the analog input to CH7 alters the sequence of
bits from DOUT. A total of 15 clock cycles per conversion
is required. All SSTRB and DOUT output transitions occur
on SCLK’s falling edge.
How to Start a ConversionClocking a control byte into DIN starts conversion on the
MAX1202/MAX1203. With CS low, each rising edge on
SCLK clocks a bit from DIN into the MAX1202/MAX1203’s
internal shift register. After CS falls, the first logic “1” bit
defines the control byte’s MSB. Until this first “start” bit
arrives, any number of logic “0” bits can be clocked into
DIN with no effect. Table 2 shows the control-byte format.
The MAX1202/MAX1203 are fully compatible with SPI/
MICROWIRE devices. For SPI, select the correct clock
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE and SPI both
transmit and receive a byte at the same time. Using the
Typical Operating Circuit, the simplest software interface
requires only three 8-bit transfers to perform a conversion
(one 8-bit transfer to configure the ADC, and two more
8-bit transfers to clock out the 12-bit conversion result).
Table 1a. Unipolar Full Scale and Zero
Scale
Table 1b. Bipolar Full Scale, Zero Scale, and Negative Full Scale*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
REFERENCEZERO
SCALEFULL SCALEInternal0V+4.096V
Externalat REFADJ0VVREFADJ x A*
at REF0VVREF
REFERENCENEGATIVE
FULL SCALE
ZERO
SCALEFULL SCALEInternal+4.096V/20V+4.096V/2
External
REFADJ
-1/2 VREFADJ
x A*0V+1/2 VREFADJ
x A*
at REF+1/2 VREF0V+1/2 VREF
MAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Table 2. Control-Byte Format
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7GND00+-
00+-
01+-
01+-
10+-
10+-
11+-
11+-
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH700+-
01+-
10+-
11+-
00-+
01-+
10-+
BIT 7
(MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT1BIT 0 (LSB)STARTSEL 2SEL 1SEL 0UNI/BIPSGL/DIFPD1PD0
BITNAMEDESCRIPTION7 (MSB)STARTThe irst logic 1 bit after CS goes low deines the beginning of the control byte.
SEL2
SEL1
SEL0
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2
to +VREF/2.SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referred to GND. In differential mode, the voltage difference
between two channels is measured. (Tables 3 and 4).
0 (LSB)
PD1
PD0
Selects clock and power-down modes.
PD1 PD0 Mode
0 0 Full power-down (IDD = 2µA, internal reference)
0 1 Fast power-down (IDD = 30µA, internal reference)
1 0 Internal clock mode
1 1 External clock modeMAX1202/MAX12035V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
