MAX120 Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX120
500ksps, Sampling, 12-Bit ADC with Track/Hold and Reference
General Description
The MAX120/MAX122 complete, BiCMOS, sampling 12-bit
analog-to-digital converters (ADCs) combine an on-chip
track/hold (T/H) and a low-drift voltage reference with fast
conversion speeds and low-power consumption. The T/H’s
350ns acquisition time combined with the MAX120’s 1.6µs
conversion time results in throughput rates as high as 500k
samples per second (ksps). Throughput rates of 333ksps
are possible with the 2.6µs conversion time of the MAX122.
The MAX120/MAX122 accept analog input voltages from
-5V to +5V. The only external components needed are
decoupling capacitors for the power-supply and refer-
ence voltages. The MAX120 operates with clocks in the
0.1MHz to 8MHz frequency range. The MAX122 accepts
0.1MHz to 5MHz clock frequencies.
The MAX120/MAX122 employ a standard microprocessor
(µP) interface. Three-state data outputs are configured
to operate with 12-bit data buses. Data-access and bus-
release timing specifications are compatible with most
popular µPs without resorting to wait states. In addition,
the MAX120/MAX122 can interface directly to a first-in,
first-out (FIFO) buffer, virtually eliminating µP interrupt
overhead. All logic inputs and outputs are TTL/CMOS
compatible. For applications requiring a serial interface,
refer to the MAX121.
Applications●Digital-Signal Processing●Audio and Telecom Processing ●Speech Recognition and Synthesis ●High-Speed Data Acquisition ●Spectrum Analysis●Data Logging Systems
Features●12-Bit Resolution●No Missing Codes Over Temperature●20ppm/°C -5V Internal Reference●1.6µs Conversion Time/500ksps Throughput
(MAX120)●2.6µs Conversion Time/333ksps Throughput
(MAX122)●Low Noise and Distortion: 70dB (min) SINAD -77dB (max) THD (MAX122)●Low Power Dissipation: 210mW●Separate Track/Hold Control Input●Continuous-Conversion Mode Available●±5V Input Range, Overvoltage Tolerant to ±15V●24-Pin Narrow DIP, Wide SO, and SSOP Packages
+Denotes a lead(Pb)-free/RoHS-compliant package.
PARTTEMP RANGEPIN-
PACKAGE
INL
(LSB)
MAX120CNG+0°C to +70°C24 PDIP±1
MAX120CWG+0°C to +70°C24 Wide SO±1
MAX120CAG+0°C to +70°C24 SSOP±1
MAX120ENG+-40°C to +85°C24 PDIP±1
MAX120EWG+-40°C to +85°C24 Wide SO±1
VDD
AINCLKIN
MODE
VSSCS
INT/BUSY
PDIP/SO/SSOP
TOP VIEW
D11
D10D2
VREF
AGNDD0
CONVSTD3916D41015D51114
DGNDD61213
MAX120
MAX122
MAX120/MAX122500ksps, 12-Bit ADCs with Track/Hold
and Reference
Pin Coniguration
Functional Diagram
Ordering Information
VDD to DGND ..........................................................-0.3V to +6V
VSS to DGND ........................................................+0.3V to -17V
AIN to AGND .......................................................................±15V
AGND to DGND .................................................................±0.3V
Digital Inputs/Outputs to DGND ....................-0.3V to (V + 0.3V)
Continuous Power Dissipation (TA = +70°C)Narrow PDIP (derate 13.33mW/°C above +70°C) ....1067mWSO (derate 11.76mW/°C above +70°C) ......................941mWSSOP (derate 8.00mW/°C above +70°C) ...................640mWNarrow CDIP (derate 12.50mW/°C above +70°C) ....1000mW
Operating Temperature Ranges
MAX12_C ...........................................................0°C to +70°C
MAX12_E_ ....................................................-40°C to +85°C
MAX12_MRG ..............................................-55°C to +125°C
Storage Temperature Range ..............................-65°C to+160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = +4.75V to +5.25V, VSS = -10.8V to -15.75V, fCLK = 8MHz for MAX120 and 5MHz for MAX122, TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ACCURACY
ResolutionRES12Bits
Differential Nonlinearity (Note 1)DNL
12-bit no missing
codes over
temperature range
MAX122AC/AE±3/4
LSB
MAX120C/E,
MAX122BC/BE±1
11-bit no missing
codes over
temperature range
MAX120M±2
Integral Nonlinearity
(Note 1)INL
MAX122AC/AE±3/4
LSBMAX120C/E,
MAX122BC/BE±1
Bipolar Zero Error (Note 1)
Code 00..00 to 00..01 transition,
near VAIN = 0V±3LSB
Temperature drift±0.005LSB/”C
Full-Scale Error (Notes 1, 2)Including reference; adjusted for bipolar
zero error; TA = +25°C±8LSB
Full-Scale Temperature DriftExcluding reference±1ppm/”C
Power-Supply Rejection Ratio
(Change in FS)
(Note 3)
PSRR
VDD only, 5V ±5%±1/4±3/4
LSBVSS only, -12V ±10%±1/4±1
VSS only, -15V ±5%±1/4±1
ANALOG INPUT
Input Range-5+5V
Input CurrentVAIN = +5V (approximately 6kΩ to REF)2.5mA
Input Capacitance (Note 4)10pF
Full-Power Input Bandwidth1.5MHz
REFERENCE
Output VoltageNo external load, VAIN = 5V, TA = +25°C-5 02-4.98V
External Load Regulation0mA < ISINK < 5mA, VAIN = 0V5mV
MAX120/MAX122500ksps, 12-Bit ADCs with Track/Hold
and Reference
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +4.75V to +5.25V, VSS = -10.8V to -15.75V, fCLK = 8MHz for MAX120 and 5MHz for MAX122, TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC PERFORMANCE (MAX120: fS = 500kHz, VAIN = ±5VP-P, 100kHz: MAX122: fS = 333kHz, VAIN = ±5VP-P, 50kHz
Signal-to-Noise Plus DistortionSINADTA = +25°C
MAX120, MAX1227072MAX122AC/AE70
MAX122BC/BE69
Total Harmonic Distortion
(First Five Harmonics)THD
TA = +25°C
MAX120-82-77
MAX122-85-78
MAX122AC/AE-77
MAX122BC/BE-75
Spurious-Free Dynamic RangeSFDR
TA = +25°C
MAX1207782
MAX1227885
MAX122AC/AE77
MAX122BC/BE75
CONVERSION TIME
SynchronoustCONV13tCLK
MAX1201.63
MAX1222.60
Clock FrequencyfCLK
MAX1200.18
MHz
MAX1220.15
DIGITAL INPUTS (CLKIN, CONVST, RD, CS)
Input High VoltageVIH2.4V
Input Low VoltageVIL0.8V
Input Capacitance (Note 4)10pF
Input CurrentVIN = 0V or VDD±5µA
DIGITAL OUTPUTS (INT/BUSY, D11–D0)
Output Low VoltageVOLISINK = 1.6mA0.4V
Output High VoltageVOHISOURCE = 1mAVDD - 0.5V
Leakage CurrentILKGVIN = 0V or VDD, D11–D0±5µA
Output Capacitance (Note 4)10pF
POWER REQUIREMENTS
Positive Supply VoltageVDDGuaranteed by supply rejection test4.755.25V
Negative Supply VoltageVSSGuaranteed by supply rejection test-10.80-15.75V
Positive Supply Current (Note 6)IDDVDD = 5.25V, VSS = -15.75V, VAIN = 0V915mA
Negative Supply Current (Note 6)ISSVDD = 5.25V, VSS = -15.75V, VAIN = 0V1420mA
MAX120/MAX122500ksps, 12-Bit ADCs with Track/Hold
and Reference
Electrical Characteristics (continued)
Note 1: These tests are performed at VDD = 5V, VSS = -15V. Operation over supply is guaranteed by supply rejection tests.
Note 2: Ideal full-scale transition is at +5V - 3/2 LSB = +4.9963V, adjusted for offset error.
Note 3: Supply rejection defined as change in full-scale transition voltage with the specified change in supply voltage = (FS at nomi-
nal supply)- (FS at nominal supply ± tolerance), expressed in LSBs.
Note 4: For design guidance only, not tested.
Note 5: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as TC = ΔVREF/
VREF/(ΔT).
Note 6: VCS = VRD = VCONVST = 0V, VMODE = 5V.
Note 7: Control inputs specified with tr = tf = 5ns ( 10% to 90% of +5V) and timed from a 1.6V voltage level. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For bus-relinquish time, a change of 0.5V is measured. See Figures
1 and 2 for load circuits.
Note 8: For design guidance only, not tested.
(VDD = +5V, VSS = -12V to -15V, 100% tested, TA = TMIN to TMAX, unless otherwise noted.) (Note 7)
PARAMETERSYMBOLCONDITIONS
TA = +25°CMAX12_C/E
UNITSMINTYPMAXMINTYPMAX
CS to RD Setup Time tCS00ns
CS to RD Hold Time tCH00ns
CONVST Pulse WidthtCW3030ns
RD Pulse WidthtRWtDAtDAns
Data-Access Time tDACL = 100pF4075100ns
Bus-Relinquish Time tDH305065ns
RD or CONVST to BUSYtB0CL = 50pF3075100ns
CLKIN to BUSY or INTtB1CL = 50pF70110150ns
CLKIN to BUSY LowtB2In mode 54590120ns
RD to INT HightIHCL = 50pF305075ns
BUSY or INT to Data ValidtBDCL (Data) = 100pF,
CL (INT, BUSY) = 50pF2030ns
Acquisition Time (Note 8)tACQ350350ns
Aperture Delay (Note 8)tAP10ns
Aperture Jitter (Note 8)30ps
PINNAMEFUNCTIONMODE
Mode Input. Hardwire to set operational mode.
VDD: Single conversion, INT Output
OPEN: Single conversion, BUSY Output
DGND: Continuous conversions, BUSY OutputVSSNegative Power Supply, -12V or -15VVDDPositive Power Supply, +5VAINSampling Analog Input, ±5V bipolar input rangeVREF-5V Reference Output. Bypass to AGND with 22µF || 0.1µF.
MAX120/MAX122500ksps, 12-Bit ADCs with Track/Hold
and Reference
Timing Characteristics
Pin Description
Detailed Description
ADC Operation
The MAX120/MAX122 use successive approximation and
input T/H circuitry to convert an analog signal to a series
of 12-bit digital-output codes. The control logic interfaces
easily to most µPs, requiring only a few passive compo-
nents tor most applications. The T/H does not require an
external capacitor. Figure 3 shows the MAX120/MAX122
in the simplest operational configuration.
Analog Input Track/Hold
Figure 4 shows the equivalent input circuit, illustrating the
sampling architecture of the ADC’s analog comparator.
An internal buffer charges the hold capacitor to minimize
the required acquisition time between conversions. The analog input appears as a 6kΩ resistor in parallel with a
10pF capacitor.
Between conversions, the buffer input is connected to AIN
through the input resistance. When a conversion starts,
the buffer input disconnects from AIN, thus sampling the
input. At the end of the conversion, the buffer input recon-
nects to AIN, and the hold capacitor once again charges
to the input voltage.
The T/H is in tracking mode whenever a conversion is
NOT in progress. Hold mode starts approximately 10ns
after a conversion is initiated. Variation in this delay from
one conversion to the next (aperture jitter) is typically
30ps. Figures 7 through 11 detail the T/H mode and inter-
face timing for the various interface modes.
Figure 1. Load Circuits for Access Time
Figure 2. Load Circuits for Bus-Relinquish Time
PINNAMEFUNCTIONAGNDAnalog Ground
7–11, 13–19D11–D0Three-State Data Outputs D11 (MSB) to D0 (LSB)DGNDDigital GroundCONVSTConvert Start Input. Initiates conversions on its falling edge.CLKINClock Input. Drive with TTL-compatible clock from 0.1MHz to 8MHz (MAX120), 0.1MHz to 5MHz
(MAX122)INT/BUSY
Interrupt or Busy Output. Indicates converter status. If MODE is connected to VDD, conigure
for an INT output. If MODE is open or connected to DGND, conigure for a BUSY output. See
operational diagrams.CSChip-Select Input, Active-Low. When RD is low, enables the three-state outputs. If CONVST and
RD are low, a conversion is initiated on the falling edge of CS.RDRead Input, Active-Low. When CS is low, RD enables the three-state outputs. If CONVST and CS
are low, conversion is initiated on the falling egde of RD.
MAX120/MAX122500ksps, 12-Bit ADCs with Track/Hold
and Reference
Pin Description (continued)

Partno	Mfg	Dc	Qty	Available	Descript
MAX120	MAXI	N/a	20	avai	500ksps, Sampling, 12-Bit ADC with Track/Hold and Reference