MAX1198ECM-D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = 3.3V, OV = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM ..
MAX120 ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceFeaturesThe MAX120/MAX122 complete, BiCMOS, sampling 12-bit ● 12-Bit Resolutionanalog-to-digital co ..
MAX1202ACAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceFeaturesThe MAX1202/MAX1203 are 12-bit data-acquisition sys- ● 8-Channel Single-Ended or 4-Channel ..
MAX1202ACPP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceEVALUATION KIT AVAILABLEMAX1202/MAX1203 5V, 8-Channel, Serial, 12-Bit ADCswith 3V Digital Interface
MAX1202AEAP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEfeatures an internal 4.096V reference,while the MAX1203 requires an external reference. Both Orderi ..
MAX1202AEPP ,5v / 8-cHANNEL / sERIAL / 12-bIT adcS WITH 3v dIGITAL iNTERFACEApplications2CH1 19 SCLK5V/3V Mixed-Supply Systems CH2 3 18 CSCH3 4 MAX1202Data Acquisition 17 DINM ..
MAX3491ESD+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX349CAP+ ,Serially Controlled, Low-Voltage, 8-Channel Dual 4-Channel Multiplexers
MAX349CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX349CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX349CWN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX350CAP ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX1198ECM+D-MAX1198ECM-D
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
General DescriptionThe MAX1198 is a 3.3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1198
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
264mW, while delivering a typical signal-to-noise and
distortion (SINAD) of 48.1dB at an input frequency of
50MHz and a sampling rate of 100Msps. The T/H-driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1198 features a 3.2mA sleep mode, as well as a
0.15µA power-down mode to conserve power during
idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1198 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1198 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1198
are also available. Refer to the MAX1195 data sheet for
40Msps and the MAX1197 data sheet for 60Msps. In
addition to these speed grades, this family includes a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1180 data sheet. With the N.C. pins of the
MAX1198 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1180.
Applications
FeaturesSingle 2.7V to 3.6V OperationExcellent Dynamic Performance
48.1dB/47.6dB SINAD at fIN= 50MHz/200MHz
66dBc/61.5dBc SFDR at fIN= 50MHz/200MHz-72dB Interchannel Crosstalk at fIN= 50MHzLow Power
264mW (Normal Operation)
10.6mW (Sleep Mode)
0.5µW (Shutdown Mode)0.05dB Gain and ±0.1°Phase MatchingWide ±1VP-PDifferential Analog Input Voltage
Range400MHz -3dB Input BandwidthOn-Chip 2.048V Precision Bandgap ReferenceUser-Selectable Output Format—Two’s
Complement or Offset BinaryPin-Compatible 8-Bit and 10-Bit Upgrades
Available
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel OutputsN.C.
N.C.
OGND
OVDD
OVDD
OGND
N.C.
N.C.
D0B
D1B
D2B
D3B
COM
VDD
GND
INA+
INA-
VDD
GND
INB-
INB+
GND
VDD
CLK
TQFP-EPGND
GND
T/B
SLEEPOE
D7BD6BD5BD4B14151617181920212223244746454443424140393837
REFNREFPREFINREFOUTD7AD6AD5AD4AD3AD2AD1AD0A
MAX1198
Pin Configuration
Ordering Information19-2412; Rev 0; 4/02
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.*EP = Exposed paddle
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical
Imaging
Battery-Powered
Instrumentation
WLAN, WWAN, WLL,
MMDS Modems
Set-Top Boxes
VSAT Terminals
PARTTEMP RANGEPIN-PACKAGEMAX1198ECM-40°C to +85°C48 TQFP-EP*
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.3V, OVDD= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 100MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND.................................-0.3V to (VDD+ 0.3V)
OE, PD, SLEEP, T/B, D7A–D0A,
D7B–D0B to OGND.............................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITS
DC ACCURACYResolution8Bits
Integral NonlinearityINLfIN = 7.5MHz (Note 1)±0.3±1LSB
Differential NonlinearityDNLfIN = 7.5MHz, no missing codes guaranteed
(Note 1)±0.2±1LSB
Offset Error±4%FS
Gain Error±4%FS
Gain Temperature Coefficient±100ppm/°C
ANALOG INPUTDifferential Input Voltage RangeVDIFFDifferential or single-ended inputs±1.0V
Common-Mode Input Voltage
RangeVCMV D D / 2
±0.2V
Input ResistanceRINSwitched capacitor load57kΩ
Input CapacitanceCIN5pF
CONVERSION RATEMaximum Clock FrequencyfCLK100MHz
Data Latency5Clock
Cycles
DYNAMIC CHARACTERISTICS (fCLK = 100MHz, 4096-point FFT)fINA or B = 7.5MHz at -1dB FS48.5
fINA or B = 20MHz at -1dB FS47.048.3
fINA or B = 50MHz at -1dB FS48.3Signal-to-Noise RatioSNR
fINA or B = 115.1MHz at -1dB FS48.1
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 100MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at= +25°C.)
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITSfINA or B = 7.5MHz at -1dB FS48.3
fINA or B = 20MHz at -1dB FS46.548.2
fINA or B = 50MHz at -1dB FS48.1Signal-to-Noise and DistortionSINAD
fINA or B = 115.1MHz at -1dB FS48
fINA or B = 7.5MHz at -1dB FS67
fINA or B = 20MHz at -1dB FS6067
fINA or B = 50MHz at -1dB FS66Spurious-Free Dynamic RangeSFDR
fINA or B = 115.1MHz at -1dB FS65
dBc
fINA or B = 7.5MHz at -1dB FS- 67
fINA or B = 20MHz at -1dB FS- 67
fINA or B = 50MHz at -1dB FS- 67Third-Harmonic DistortionHD3
fINA or B = 115.1MHz at -1dB FS- 66
dBc
Intermodulation Distortion
(First Five Odd-Order IMDs)IMD
fIN1(A or B) = 1.989MHz at -7dB FS
fIN2(A or B) = 2.038MHz at -7dB FS
(Note 2)69.5dBc
Third-Order Intermodulation
DistortionIM3
fIN1(A or B) = 1.989MHz at -7dB FS
fIN2(A or B) = 2.038MHz at -7dB FS
(Note 2)80dBc
fINA or B = 7.5MHz at -1dB FS- 66
fINA or B = 20MHz at -1dB FS- 67- 57
fINA or B = 50MHz at -1dB FS- 64
Total Harmonic Distortion
(First Four Harmonics)THD
fINA or B = 115.1MHz at -1dB FS- 58
dBc
Small-Signal BandwidthInput at -20dB FS, differential inputs500MHz
Full-Power BandwidthFPBWInput at -1dB FS, differential inputs400MHz
Gain Flatness
(12MHz Spacing)
fIN1(A or B) = 106MHz at -1dB FS
fIN2(A or B) = 118MHz at -1dB FS
(Note 3)
0.05dB
Aperture DelaytAD1ns
Aperture JittertAJ1dB SNR degradation at Nyquist2psRMS
Overdrive Recovery TimeFor 1.5 × full-scale input2ns
IN T ER N A L REF ER EN C E ( RE FIN = RE FOU T thr oug h 10kΩ r esi stor ; RE FP , RE FN , and C OM l evel s ar e g ener ated i nter nal l y.)
Reference Output VoltageVREFOUT(Note 4)2.0483% V
Positive Reference Output
VoltageVREFP(Note 5)2.162V
Negative Reference Output
VoltageVREFN(Note 5)1.138V
Common-Mode LevelVCOM(Note 5)V D D / 2
±0.1V
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITSDifferential Reference Output
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.0243% V
Reference Temperature
CoefficientTCREF±100ppm/°C
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)Positive Reference Output
VoltageVREFP(Note 5)2.162V
Negative Reference Output
VoltageVREFN(Note 5)1.138V
Common-Mode LevelVCOM(Note 5)V D D / 20.1V
Differential Reference Output
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.0242% V
REFIN ResistanceRREFIN> 50MΩ
Maximum REFP, COM Source
CurrentISOURCE5mA
Maximum REFP, COM Sink
CurrentISINK- 250µA
Maximum REFN Source CurrentISOURCE250µA
Maximum REFN Sink CurrentISINK- 5mA
N B U F F ER ED EXT ER N A L R EF ER EN C E ( V RE F IN = AGN D , r efer ence vol tag e ap p l i ed to RE FP , RE FN , and C OM )
REFP, REFN Input ResistanceRREFP,
RREFN
Measured between REFP, COM, REFN,
and COM4kΩ
REFP, REFN, COM Input
CapacitanceCIN15pF
Differential Reference Input
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.024
±10% V
COM Input Voltage RangeVCOMV D D / 2±5%V
REFP Input VoltageVREFPV C OM +
ΔV RE F / 2V
REFN Input VoltageVREFNV C OM -
ΔV RE F / 2V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)CLK0.8 ×
VDD
Input High ThresholdVIH
PD, OE, SLEEP, T/B0.8 ×
OVDD
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 100MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at= +25°C.)
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITSCLK0.2 ×
VDD
Input Low ThresholdVIL
PD, OE, SLEEP, T/B0.2 ×
OVDD
Input HysteresisVHYST0.15V
IIHVIH = VDD = OVDD±20Input LeakageIILVIL = 0±20µA
Input CapacitanceCIN5pF
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)Output Voltage LowVOLISINK = -200µA0.2V
Output Voltage HighVOHISOURCE = 200µAOVDD -
0.2V
Three-State Leakage CurrentILEAKOE = OVDD±10µA
Three-State Output CapacitanceCOUTOE = OVDD5pF
POWER REQUIREMENTSAnalog Supply Voltage RangeVDD2.73.33.6V
Output Supply Voltage RangeOVDDCL = 15pF1.72.53.6V
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels8095
Sleep mode3.2Analog Supply CurrentIVDD
Shutdown, clock idle, PD = OE = OVDD0.1520µA
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels (Note 6)11.5mA
Sleep mode2Output Supply CurrentIOVDD
Shutdown, clock idle, PD = OE = OVDD210µA
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels264314
Sleep mode10.6Analog Power DissipationPDISS
Shutdown, clock idle, PD = OE = OVDD0.566µW
Offset, VDD ±5%±3Power-Supply RejectionPSRRGain, VDD ±5%±3mV/V
TIMING CHARACTERISTICSCLK Rise to Output Data Valid
TimetDOCL = 20pF (Notes 1, 7)68.25ns
OE Fall to Output Enable TimetENABLE5ns
OE Rise to Output Disable TimetDISABLE5ns
CLK Pulse Width HightCHClock period: 10ns (Note 7)5 ± 0.5ns
CLK Pulse Width LowtCLClock period: 10ns (Note 7)5 ± 0.5ns
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 100MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at= +25°C.)
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Note 1:Guaranteed by design. Not subject to production testing.
Note 2:Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3:Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at fIN1and fIN2.
Note 4:REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5:REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6:Typical analog output current at fINA & B= 20MHz. For digital output currents vs. analog input frequency,
see Typical Operating Characteristics.
Note 7:See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock
level to 50% of the data output level.
Note 8:Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.
Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 9:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 10:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental
of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 11:SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
PARAMETERSYMBOLCONDITIONSMINT YPMAXUNITSWake up from sleep mode1Wake-Up TimetWAKEWake up from shutdown mode (Note 11)20µs
CHANNEL-TO-CHANNEL MATCHINGCrosstalkfINA or B = 20MHz at -1dB FS (Note 8)- 72dB
Gain MatchingfINA or B = 20MHz at -1dB FS (Note 9)0.05dB
Phase MatchingfINA or B = 20MHz at -1dB FS (Note 10)± 0.1Degrees
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 100MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at= +25°C.)
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics(VDD= 3.3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 100MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
SFDR (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYMAX1198 toc09
ANALOG INPUT FREQUENCY (MHz)
CHB
CHA
THD (dBc)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1198 toc08
ANALOG INPUT FREQUENCY (MHz)
CHB
CHA
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1198 toc07
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
CHB
CHA
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYMAX1198 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
CHA
CHB
MAX1198 toc05111098713
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 100.007936MHz
fIN1 = 10.022768MHz
fIN2 = 10.047184MHz
AIN = -7dB FS
COHERENT SAMPLING
fIN1fIN2
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)MAX1198 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 100.007936MHz
fIN1 = 1.989904MHz
fIN2 = 2.038736MHz
AIN = -7dB FS
COHERENT SAMPLING
fIN1fIN2
MAX1198 toc03
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)403035101520255
fCLK = 100.050607MHz
fINA = 114.9629350MHz
fINB = 99.5010126MHz
AIN = -1dB FS
COHERENT SAMPLING
fINB
fINA
HD2
HD3
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)MAX1198 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)403035101520255
fCLK = 100.050607MHz
fINA = 49.7443997MHz
fINB = 19.8708908MHz
AIN = -1dB FS
COHERENT SAMPLING
fINB
fINA
HD2
HD3
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)MAX1198 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)403035101520255
fCLK = 100.050607MHz
fINA = 19.8708908MHz
fINB = 7.5355498MHz
AIN = -1dB FS
COHERENT SAMPLING
fINB
fINA
HD2HD3
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 100MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
DIFFERENTIAL NONLINEARITY
(262144-POINT DATA RECORD)MAX1198 toc18
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
(262144-POINT DATA RECORD)
MAX1198 toc17
DIGITAL OUTPUT CODE
INL (LSB)
MAX1198 toc16
INPUT POWER (dB FS)
SFDR (dBc)-8-12-16
SPURIOUS-FREE DYNAMIC RANGE vs.
INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc15
INPUT POWER (dB FS)
THD (dBc)-8-12-16
TOTAL HARMONIC DISTORTION vs.
INPUT POWER (fIN = 19.87089082MHz)
SIGNAL-TO-NOISE + DISTORTION vs.
INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc14
INPUT POWER (dB FS)
SINAD (dB)-8-12-16
SIGNAL-TO-NOISE RATIO vs.
INPUT POWER (fIN = 19.87089082MHz)
MAX1198 toc13
INPUT POWER (dB FS)
SNR (dB)-8-12-16
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, DIFFERENTIAL
MAX1198 toc12
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
VIN = 100mVP-P
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, DIFFERENTIALMAX1198 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
SNR/SINAD, THD/SFDR vs. TEMPERATURE
MAX1198 toc10
TEMPERATURE (°C)
SNR/SINAD, THD/SFDR (dB, dBc)3510-15
SNR
SINAD
SFDR
THD
fIN = 19.87089082MHz
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 100MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATUREMAX1198 toc26
TEMPERATURE (°C)
REFOUT
(V)3510-15
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1198 toc25
VDD (V)
REFOUT
(V)
SNR/SINAD, THD/SFDR
vs. CLOCK DUTY CYCLE
MAX1198 toc24
CLOCK DUTY CYCLE (%)
SNR/SINAD, THD/SFDR (dB, dBc)524844
SFDR
THD
SINAD
SNR60
fIN = 19.87089082MHz
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCYMAX1198 toc23
ANALOG INPUT FREQUENCY (MHz)
IOVDD
(mA)302010
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1198 toc22
TEMPERATURE (°C)
IVDD
(mA)3510-15
SNR/SINAD, THD/SFDR
vs. SAMPLING SPEED
MAX1198 toc21
SAMPLING SPEED (Msps)
SNR/SINAD, THD/SFDR (dB, dBc)
SFDR
SNR
SINAD
THD
fIN = 19.87089082MHz
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE VREFIN = 2.048VMAX1198 toc20
TEMPERATURE (°C)
OFFSET ERROR (%FS)3510-15
CHA
CHB
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE VREFIN = 2.048VMAX1198 toc19
TEMPERATURE (°C)
GAIN ERROR (%FS)3510-15
CHB
CHA
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description
PINNAMEFUNCTIONCOMCommon-Mode Voltage I/O. Bypass to GND with a ≥0.1µF capacitor.
2, 6, 11, 14, 15VDDAnalog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
3, 7, 10, 13, 16GNDAnalog GroundINA+Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.INA-Channel A Negative Analog Input. For single-ended operation connect INA- to COM.INB-Channel B Negative Analog Input. For single-ended operation connect INB- to COM.INB+Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.CLKConverter Clock InputT/B
T/B Selects the ADC Digital Output Format
High: Two’s complement
Low: Straight offset binarySLEEP
Sleep Mode Input
High: Disables both quantizers, but leaves the reference bias circuit active
Low: Normal operationPD
Active-High Power-Down Input
High: Power-down mode
Low: Normal operationOE
Active-Low Output Enable Input
High: Digital outputs disabled
Low: Digital outputs enabledD7BThree-State Digital Output, Bit 7 (MSB), Channel BD6BThree-State Digital Output, Bit 6, Channel BD5BThree-State Digital Output, Bit 5, Channel BD4BThree-State Digital Output, Bit 4, Channel BD3BThree-State Digital Output, Bit 3, Channel BD2BThree-State Digital Output, Bit 2, Channel BD1BThree-State Digital Output, Bit 1, Channel BD0BThree-State Digital Output, Bit 0, Channel B
29, 30, 35, 36N.C.No Connection
31, 34OGNDOutput Driver Ground
32, 33OVDDOutput Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel
with 0.1µF.D0AThree-State Digital Output, Bit 0, Channel AD1AThree-State Digital Output, Bit 1, Channel AD2AThree-State Digital Output, Bit 2, Channel AD3AThree-State Digital Output, Bit 3, Channel AD4AThree-State Digital Output, Bit 4, Channel A
Detailed DescriptionThe MAX1198 uses a seven-stage, fully differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals.The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been processed
by all seven stages.
Input Track-and-Hold (T/H) CircuitsFigure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description (continued)
PINNAMEFUNCTIOND5AThree-State Digital Output, Bit 5, Channel AD6AThree-State Digital Output, Bit 6, Channel AD7AThree-State Digital Output, Bit 7 (MSB), Channel AREFOUTInternal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-
divider.REFINReference Input. VREFIN = 2 x (VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.REFPPositive Reference I/O. Conversion range is ±(VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.REFNNegative Reference I/O. Conversion range is ±(VREFP - VREFN).
Bypass to GND with a >0.1µF capacitor.
VINA
STAGE 1STAGE 2
D7A–D0A
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL ALIGNMENT LOGIC
STAGE 6STAGE 7
2-BIT FLASH
ADC
T/H8
VINB
STAGE 1STAGE 2
D7B–D0B
DIGITAL ALIGNMENT LOGIC
STAGE 6STAGE 7
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks
