MAX1196ECM+D ,Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel OutputsApplications DDV 6 31 OGNDDDMAX1196Baseband I/Q SamplingGND 7 30 A/BINB- N.C.8 29Multichannel IF Sa ..
MAX1198ECM+D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputsfeatures parallel, CMOS-compatible three-state outputs. The digital output format can be set to two ..
MAX1198ECM-D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = 3.3V, OV = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM ..
MAX120 ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceFeaturesThe MAX120/MAX122 complete, BiCMOS, sampling 12-bit ● 12-Bit Resolutionanalog-to-digital co ..
MAX1202ACAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceFeaturesThe MAX1202/MAX1203 are 12-bit data-acquisition sys- ● 8-Channel Single-Ended or 4-Channel ..
MAX1202ACPP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceEVALUATION KIT AVAILABLEMAX1202/MAX1203 5V, 8-Channel, Serial, 12-Bit ADCswith 3V Digital Interface
MAX3491EESD-T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD ,3.3V-Powered, 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX349CAP+ ,Serially Controlled, Low-Voltage, 8-Channel Dual 4-Channel Multiplexers
MAX349CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX349CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX1196ECM+D
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
General DescriptionThe MAX1196 is a 3V, dual 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1196
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
87mW while delivering a typical signal-to-noise and dis-
tortion (SINAD) of 48.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters can also be operated with single-
ended inputs. In addition to low operating power, the
MAX1196 features a 3mA sleep mode as well as a
0.1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1196 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output format
can be set to two’s complement or straight offset binary
through a single control pin. The device provides for a
separate output power supply of 1.7V to 3.6V for flexible
interfacing. The MAX1196 is available in a 7mm ×7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible, nonmultiplexed higher speed versions of
the MAX1196 are also available. Refer to the MAX1198
data sheet for 100Msps, the MAX1197 data sheet for
60Msps, and the MAX1195 data sheet for 40Msps.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1186 data sheet. With the N.C. pins of the
MAX1196 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1186.
ApplicationsBaseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
FeaturesSingle 2.7V to 3.6V OperationExcellent Dynamic Performance
48.4dB/44.7dB SINAD at fIN= 20MHz/200MHz
68.9dB/53dBc SFDR at fIN= 20MHz/200MHz-72dB Interchannel Crosstalk at fIN= 20MHzLow Power
87mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)0.05dB Gain and ±0.05°Phase MatchingWide ±1VP-PDifferential Analog Input Voltage
Range400MHz -3dB Input BandwidthOn-Chip 2.048V Precision Bandgap ReferenceUser-Selectable Output Format—Two’s
Complement or Offset BinaryPin-Compatible 8-Bit and 10-Bit Upgrades
Available
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel OutputsN.C.
N.C.
OGND
OVDD
OVDD
OGND
A/B
N.C.
N.C.
N.C.
N.C.
N.C.
COM
VDD
GND
INA+
INA-
VDD
GND
INB-
INB+
GND
VDD
CLK
TQFP-EPMAX1196
GND
GND
T/B
SLEEPOE
N.C.N.C.N.C.N.C.14151617181920212223244746454443424140393837
REFNREFPREFINREFOUTD7A/B D6A/BD5A/BD4A/BD3A/BD2A/BD1A/BD0A/B
PARTTEMP RANGEPIN-PACKAGEMAX1196ECM-40°C to +85°C48 TQFP-EP*
Pin Configuration
Ordering Information19-2600; Rev 0; 9/02
*EP = Exposed pad.
Functional Diagram appears at end of data sheet.
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs (Note 5), fCLK= 40MHz, TA= TMINto TMAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND..............................................-0.3V to +3.6V
OGND to GND......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (VDD+ 0.3V)
OE, PD, SLEEP, T/B,
D7A/B–D0A/B, A/B to OGND...............-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution8Bits
Integral NonlinearityINLfIN = 7.51MHz (Note 1)±0.3±1LSB
Differential NonlinearityDNLfIN = 7.51MHz, no missing codes
guaranteed (Note 1)±0.15±1LSB
Offset Error±4%FS
Gain Error±4%FS
Gain Temperature Coefficient±100ppm/°C
ANALOG INPUTDifferential Input Voltage RangeVDIFFDifferential or single-ended inputs±1.0V
Common-Mode Input Voltage
RangeVCMVDD / 2± 0.2V
Input ResistanceRINSwitched capacitor load140kΩ
Input CapacitanceCIN5pF
CONVERSION RATEMaximum Clock FrequencyfCLK40MHz
CHA5Data LatencyCHB5.5
Clock
Cycles
DYNAMIC CHARACTERISTICS (fCLK = 40MHz)fINA or B = 2MHz at -1dB FS48.7
fINA or B = 7.5MHz at -1dB FS48.7
fINA or B = 20MHz at -1dB FS47.548.5Signal-to-Noise RatioSNR
fINA or B = 101MHz at -1dB FS48
fINA or B = 2MHz at -1dB FS48.6
fINA or B = 7.5MHz at -1dB FS48.7
fINA or B = 20MHz at -1dB FS4748.4Signal-to-Noise and DistortionSINAD
fINA or B = 101MHz at -1dB FS48
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs (Note 5), fCLK= 40MHz, TA= TMINto TMAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfINA or B = 2MHz at -1dB FS69
fINA or B = 7.5MHz at -1dB FS70
fINA or B = 20MHz at -1dB FS6068.9Spurious-Free Dynamic RangeSFDR
fINA or B = 101MHz at -1dB FS65
dBc
fINA or B = 2MHz at -1dB FS-72
fINA or B = 7.5MHz at -1dB FS-73.7
fINA or B = 20MHz at -1dB FS-75Third-Harmonic DistortionHD3
fINA or B = 101MHz at -1dB FS-67
dBc
fIN1(A or B) = 1.997MHz at -7dB FS,Intermodulation DistortionFir st Fi ve Od d- Or der IM D s) ( N ote 2) IMDfIN2(A or B) = 2.046MHz at -7dB FS-68dBc
fIN1(A or B) = 1.997MHz at -7dB FS,Third-Order Intermodulation
Distortion (Note 2)IM3fIN2(A or B) = 2.046MHz at -7dB FS-73.2dBc
fINA or B = 2MHz at -1dB FS-70
fINA or B = 7.5MHz at -1dB FS-69
fINA or B = 20MHz at -1dB FS-69-57
Total Harmonic Distortion
(First Four Harmonics)THD
fINA or B = 101MHz at -1dB FS-63
dBc
Small-Signal BandwidthInput at -20dB FS, differential inputs500MHz
Full-Power BandwidthFPBWInput at -1dB FS, differential inputs400MHz
fIN1(A or B) = 106MHz at -1dB FS,Gain Flatness (12MHz Spacing)
(Note 3)fIN2(A or B) = 118MHz at -1dB FS0.05dB
Aperture DelaytAD1ns
Aperture JittertAJ1dB SNR degradation at Nyquist2psRMS
Overdrive Recovery TimeFor 1.5 × full-scale input2ns
INTERNAL REFERENCE (REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)Reference Output VoltageVREFOUT(Note 4)2.048
±3%V
Positive Reference Output
VoltageVREFP(Note 5)2.012V
Negative Reference Output
VoltageVREFN(Note 5)0.988V
Common-Mode LevelVCOM(Note 5)VDD / 2
± 0.1V
Differential Reference Output
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.024
±3%V
Reference Temperature
CoefficientTCREF±100ppm/°C
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs (Note 5), fCLK= 40MHz, TA= TMINto TMAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)Positive Reference Output
VoltageVREFP(Note 5)2.012V
Negative Reference Output
VoltageVREFN(Note 5)0.988V
Common-Mode LevelVCOM(Note 5)VDD / 2
±0.1V
Differential Reference Output
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.024
±2%V
REFIN ResistanceRREFIN>50MΩ
Maximum REFP, COM Source
CurrentISOURCE5mA
Maximum REFP, C OM S i nk C ur r entISINK-250µA
Maximum REFN Source CurrentISOURCE250µA
Maximum REFN Sink CurrentISINK-5mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)REFP, REFN Input ResistanceRREFP,
RREFNMeasured between REFP and REFN4kΩ
REFP, REFN, COM Input
CapacitanceCIN15pF
Differential Reference Input
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.024
±10%V
COM Input Voltage RangeVCOMVDD / 2±5%V
REFP Input VoltageVREFPV C OM + ΔV RE F / 2V
REFN Input VoltageVREFNVCOM -
ΔVREF / 2V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)CLK0.8 ×
VDD
Input High ThresholdVIH
PD, OE, SLEEP, T/B0.8 ×
OVDD
CLK0.2 ×
VDD
Input Low ThresholdVIL
PD, OE, SLEEP, T/B0.2 ×
OVDD
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs (Note 5), fCLK= 40MHz, TA= TMINto TMAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput HysteresisVHYST0.15V
IIHVIH = VDD = OVDD±20Input LeakageIILVIL = 0±20µA
Input CapacitanceCIN5pF
DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)Output Voltage LowVOLISINK = -200µA0.2V
Output Voltage HighVOHISOURCE = 200µAOVDD -
0.2V
Three-State Leakage CurrentILEAKOE = OVDD±10µA
Three-State Output CapacitanceCOUTOE = OVDD5pF
POWER REQUIREMENTSAnalog Supply Voltage RangeVDD2.733.6V
Output Supply Voltage RangeOVDD1.733.6V
Operating, fINA&B = 20MHz at -1dB FS
applied to both channels2936
Sleep mode3Analog Supply CurrentIVDD
Shutdown, clock idle, PD = OE = OVDD0.120µA
Operating, fINA&B = 20MHz at -1dB FS
applied to both channels (Note 6)8mA
Sleep mode3Output Supply CurrentIOVDD
Shutdown, clock idle, PD = OE = OVDD310µA
Operating, fINA&B = 20MHz at -1dB FS
applied to both channels87108
Sleep mode9Analog Power DissipationPDISS
Shutdown, clock idle, PD = OE = OVDD0.360µW
Offset, VDD ±5%±3Power-Supply RejectionPSRRGain, VDD ±5%±3mV/V
TIMING CHARACTERISTICSCLK Rise to CHA Output Data
ValidtDOACL = 20pF (Notes 1, 7)68.25ns
CLK Fall to CHB Output Data
ValidtDOBCL = 20pF (Notes 1, 7)68.25ns
Clock Rise/Fall to A/B Rise/Fall
TimetDA/B6ns
OE Fall to Output Enable TimetENABLE5ns
OE Rise to Output Disable TimetDISABLE5ns
CLK Pulse Width HightCHClock period: 25ns (Note 7)12.5±1.5ns
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Note 1:Guaranteed by design. Not subject to production testing.
Note 2:Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3:Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at fIN1and fIN2.
Note 4:REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5:REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6:Typical digital output current at fINA&B = 20MHz. For digital output currents vs. analog input frequency, see the Typical
Operating Characteristics.
Note 7:See Figure3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to
50% of the data output level.
Note 8:SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
Note 9:Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is
measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-mental of the calculated FFT.
Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental ofthe calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs (Note 5), fCLK= 40MHz, TA= TMINto TMAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCLK Pulse Width LowtCLClock period: 25ns (Note 7)12.5
±1.5ns
Wake-up from sleep mode1Wake-Up TimetWAKEWake-up from shutdown mode (Note 8)20µs
CHANNEL-TO-CHANNEL MATCHINGCrosstalkfINA or B = 20MHz at -1dB FS (Note 9)-72dB
Gain MatchingfINA or B = 20MHz at -1dB FS (Note 10)0.05dB
Phase MatchingfINA or B = 20MHz at -1dB FS (Note 11)±0.05D eg r ees
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics(VDD= OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 1.958036MHz
fINB = 7.534287MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 1.958036MHz
fINB = 7.534287MHz
AINA = AINB = -1dB FS
COHERENT SAMPLINGfINB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 7.534287MHz
fINB = 1.958036MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINBHD2HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 7.534287MHz
fINB = 1.958036MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 19.88798MHz
fINB = 40.49374MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2
HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 19.88798MHz
fINB = 40.49374MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-07
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 40.49374MHz
fINB = 19.88798MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-08
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
fINA
fCLK = 40.0005678MHz
fINA = 40.49374MHz
fINB = 19.88798MHz
AINA = AINB = -1dB FS
COHERENT SAMPLING
fINB
HD2
HD3
TWO-TONE IMD PLOT
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-09
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 40.001536MHz
fINA = 1.997147MHz
fINB = 2.045977MHz
AIN = -7dB FS
COHERENT SAMPLING
fIN2fIN1
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)(VDD= OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
TWO-TONE IMD PLOT
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)MAX1196-10
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)111098
fCLK = 40.001536MHz
fIN1 = 9.95643MHz
fIN2 = 10.024799MHz
AIN = -7dB FS
COHERENT SAMPLING
fIN1fIN2
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYMAX1196-11
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
CHA
CHB
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1196-12
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
CHA
CHB
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1196-13
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
CHB
CHA
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYMAX1196-14
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
CHA
CHB101001000
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, DIFFERENTIALMAX1196-15
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)101001000
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, DIFFERENTIALMAX1196-16
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
VIN = 100mVP-P
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (fIN = 19.88798MHz)MAX1196-17
INPUT POWER (dB FS)
SNR (dB)-8-12-16
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-18
INPUT POWER (dB FS)
SINAD (dB)-8-12-16
-200
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)(VDD= OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE VREFIN = 2.048VMAX1196-24
TEMPERATURE (°C)
GAIN ERROR (%FS)3510-15
CHA
CHB
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (fIN = 19.88798MHz)MAX1196-19
INPUT POWER (dB FS)
SINAD (dBc)-8-12-16
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (fIN = 19.88798MHz)
MAX1196-20
INPUT POWER (dB FS)
SFDR (dBc)-8-12-16
SNR/SINAD, THD/SFDR
vs. CLOCK DUTY CYCLE
MAX1196-21
CLOCK DUTY CYCLE (%)
SNR/SINAD, THD/SFDR (dB, dBc)52484460
THD
SINAD
SNR
SFDRfINA/B = 7.534287MHz
INTEGRAL NONLINEARITY
(131,072-POINT DATA RECORD)MAX1196-22
DIGITAL OUTPUT CODE
INL (LSB)
fIN = 7.534287MHz
DIFFERENTIAL NONLINEARITY
(131,072-POINT DATA RECORD)MAX1196-23
DIGITAL OUTPUT CODE
DNL (LSB)
fIN = 7.534287MHz
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE VREFIN = 2.048VMAX1196-25
TEMPERATURE (°C)
OFFSET ERROR (%FS)3510-15
CHB
CHA
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)(VDD= OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
Pin Description
PINNAMEFUNCTIONCOMCommon-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.
2, 6, 11, 14, 15VDDAnalog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.
3, 7, 10, 13, 16GNDAnalog GroundINA+Channel ‘A’ Positive Analog Input. For single-ended operation, connect signal source to INA+.INA-Channel ‘A’ Negative Analog Input. For single-ended operation, connect INA- to COM.INB-Channel ‘B’ Negative Analog Input. For single-ended operation, connect INB- to COM.INB+Channel ‘B’ Positive Analog Input. For single-ended operation, connect signal source to INB+.CLKConverter Clock Input
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGEMAX1196-28
VDD (V)
REFOUT
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1196-29
TEMPERATURE (°C)
REFOUT
(V)3510-15
SNR/SINAD, THD/SFDR
vs. SAMPLING SPEED
MAX1196-30
SAMPLING SPEED (Msps)
SNR/SINAD, THD/SFDR (dB, dBc)40302010
THD
SINAD
SNRSFDRfIN = 20MHz
ANALOG SUPPLY CURRENT
vs. TEMPERATUREMAX1196-26
TEMPERATURE (°C)
IVDD
(mA)35-1510
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCY
MAX1196-27
ANALOG INPUT FREQUENCY (MHz)
IOVDD
(mA)1284
020
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PINNAMEFUNCTIONT/B
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.SLEEP
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.PD
High-Active Power-Down Input.
High: Power-down mode
Low: Normal operationOE
Low-Active Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled
21–29, 35, 36N.C.No Connection. Do not connect.A/BA/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be
present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34OGNDOutput-Driver Ground
32, 33OVDDOutput-Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with
0.1µF.D0A/BThree-State Digital Output, Bit 0. Depending on status of A/B, output data reflects channel A or
channel B data.D1A/BThree-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or
channel B data.D2A/BThree-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or
channel B data.D3A/BThree-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or
channel B data.D4A/BThree-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or
channel B data.D5A/BThree-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or
channel B data.D6A/BThree-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or
channel B data.D7A/BThree-State Digital Output, Bit 7 (MSB). Depending on status of A/B, output data reflects channel A or
channel B data.REFOUTInternal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.REFINReference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a ≥0.1µF capacitor.REFPPositive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a ≥0.1µF capacitor.REFNNegative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a ≥0.1µF
capacitor.
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Detailed DescriptionThe MAX1196 uses a 7-stage, fully differential, pipelined
architecture (Figure1) that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for CHA and 5.5 clock cycles
for CHB.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all 7 stages.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.
Input Track-and-Hold (T/H) CircuitsFigure2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a, and S5b are closed. The fully differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a, S4b, S5a, and S5b are then
opened before switches S3a and S3b connect capaci-
tors C1a and C1b to the output of the amplifier and
switch S4c is closed. The resulting differential voltages
are held on capacitors C2a and C2b. The amplifiers are
used to charge capacitors C1a and C1b to the same
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1196
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference
ConfigurationsThe full-scale range of the MAX1196 is determined by
the internally generated voltage difference between
REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4).
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
VINA
STAGE 1STAGE 2
DIGITAL ALIGNMENT LOGIC
STAGE 6STAGE 7
2-BIT FLASH
ADC
T/H8
VINB
STAGE 1STAGE 2
DIGITAL ALIGNMENT LOGIC
STAGE 6STAGE 7
2-BIT FLASH
ADC
T/H
OUTPUT MULTIPLEXER
D0A/B–D7A/B
Figure1. Pipelined Architecture—Stage Blocks
