MAX1193ETI+ ,Ultra-Low-Power, 45Msps, Dual 8-Bit ADCApplications INA- 1 21 D0Ultrasound and Medical Imaging INA+ 2 20 D1IQ Baseband SamplingGND 3 19 D2 ..
MAX1195ECM ,Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel OutputsApplications DDMAX1195GND N.C.7 30Baseband I/Q Sampling WLAN, WWAN, WLL,INB- 8 29 N.C.MMDS ModemsIN ..
MAX1196ECM+D ,Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel OutputsApplications DDV 6 31 OGNDDDMAX1196Baseband I/Q SamplingGND 7 30 A/BINB- N.C.8 29Multichannel IF Sa ..
MAX1198ECM+D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputsfeatures parallel, CMOS-compatible three-state outputs. The digital output format can be set to two ..
MAX1198ECM-D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = 3.3V, OV = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM ..
MAX120 ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceFeaturesThe MAX120/MAX122 complete, BiCMOS, sampling 12-bit ● 12-Bit Resolutionanalog-to-digital co ..
MAX3491EESD+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491EESD+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491EESD-T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD ,3.3V-Powered, 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX349CAP+ ,Serially Controlled, Low-Voltage, 8-Channel Dual 4-Channel Multiplexers
MAX1193ETI+
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
General DescriptionThe MAX1193 is an ultra-low-power, dual, 8-bit,
45Msps analog-to-digital converter (ADC). The device
features two fully differential wideband track-and-hold
(T/H) inputs. These inputs have a 440MHz bandwidth
and accept fully differential or single-ended signals.
The MAX1193 delivers a typical signal-to-noise and dis-
tortion (SINAD) of 48.5dB at an input frequency of
5.5MHz and a sampling rate of 45Msps while consum-
ing only 57mW. This ADC operates from a 2.7V to 3.6V
analog power supply. A separate 1.8V to 3.6V supply
powers the digital output driver. In addition to ultra-low
operating power, the MAX1193 features three power-
down modes to conserve power during idle periods.
Excellent dynamic performance, ultra-low power, and
small size make the MAX1193 ideal for applications in
imaging, instrumentation, and digital communications.
An internal 1.024V precision bandgap reference sets
the full-scale range of the ADC to ±0.512V. A flexible
reference structure allows the MAX1193 to use its inter-
nal reference or accept an externally applied reference
for applications requiring increased accuracy.
The MAX1193 features parallel, multiplexed, CMOS-
compatible tri-state outputs. The digital output format is
offset binary. A separate digital power input accepts a
voltage from 1.8V to 3.6V for flexible interfacing to dif-
ferent logic levels. The MAX1193 is available in a 5mm×5mm, 28-pin thin QFN package, and is specified for
the extended industrial (-40°C to +85°C) temperature
range.
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible
versions of the MAX1193 are also available. Refer to the
MAX1191 data sheet for 7.5Msps, and the MAX1192
data sheet for 22Msps.
ApplicationsUltrasound and Medical Imaging
IQ Baseband Sampling
Battery-Powered Portable Instruments
Low-Power Video
WLAN, Mobile DSL, WLL Receiver
FeaturesUltra-Low Power
57mW (Normal Operation: 45Msps)
0.3µW (Shutdown Mode)Excellent Dynamic Performance
48.5dB/48.3dB SNR at fIN= 5.5MHz/100MHz
70dBc/68dBc SFDR at fIN= 5.5MHz/100MHz2.7V to 3.6V Single Analog Supply1.8V to 3.6V TTL/CMOS-Compatible Digital
OutputsFully Differential or Single-Ended Analog InputsInternal/External Reference OptionMultiplexed CMOS-Compatible Tri-State Outputs28-Pin Thin QFN PackageEvaluation Kit Available (Order MAX1193EVKIT)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC272625242322911121314
MAX1193
5mm x 5mm THIN QFNTOP VIEW
INA+
EXPOSED PADDLE
INA-
GND
CLK
GND
INB+
INB-
REFPREFNCOMREFINPD0PD1
A/BD7
OGND
GND
Pin Configuration
Ordering Information19-2794; Rev 1; 9/03
PARTTEMP RANGEPIN-PACKAGEMAX1193ETI-T-40°C to +85°C28 Thin QFN-EP*
(5mm x 5mm)
*EP = Exposed paddle.
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, fCLK= 45MHz, CREFP= CREFN= CCOM=
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND.................-0.3V to (VDD+ 0.3V)
CLK, REFIN, REFP, REFN, COM to GND...-0.3V to (VDD+ 0.3V)
PD0, PD1 to OGND.................................-0.3V to (OVDD+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
28-Pin Thin QFN (derated 20.8mW/°C above +70°C)..1667mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution8Bits
Integral NonlinearityINL±0.16±1.00LSB
Differential NonlinearityDNLNo missing codes over temperature±0.15±1.00LSB
≥ +25°C±4Offset Error< +25°C±6%FS
Gain ErrorExcludes REFP - REFN error±2%FS
DC Gain Matching±0.01±0.2dB
Gain Temperature Coefficient±30p p m /°C
Offset (VDD ±5%)±0.2Power-Supply RejectionGain (VDD ±5%)±0.05LSB
ANALOG INPUTDifferential Input Voltage RangeVDIFFDifferential or single-ended inputs±0.512V
Common-Mode Input Voltage
RangeVCOMVDD / 2V
Input ResistanceRINSwitched capacitor load120kΩ
Input CapacitanceCIN5pF
CONVERSION RATEMaximum Clock FrequencyfCLK45MHz
Channel A5.0Data LatencyChannel B5.5
Clock
cycles
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)fIN = 3.75MHz48.5
fIN = 5.5MHz4748.5Signal-to-Noise Ratio
(Note 2)SNR
fIN = 22.5MHz48.4
fIN = 3.75MHz48.5
fIN = 5.5MHz4748.5Signal-to-Noise and Distortion
(Note 2)SINAD
fIN = 22.5MHz48.4
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, fCLK= 45MHz, CREFP= CREFN= CCOM=
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfIN = 3.75MHz70.7
fIN = 5.5MHz60.070.0Spurious-Free Dynamic Range
(Note 2)SFDR
fIN = 22.5MHz71.5
dBc
fIN = 3.75MHz-79.6
fIN = 5.5MHz-79.0Thi r d - H ar m oni c D i stor ti onN ote 2) HD3
fIN = 22.5MHz76.1
dBc
Intermodulation DistortionIMDfIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz
at -7dB FS-66dBc
Third-Order IntermodulationIM3fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz
at -7dB FS-70dBc
fIN = 3.75MHz-70.8
fIN = 5.5MHz-70.0-57.0Total Harmonic Distortion
(Note 2)THD
fIN = 22.5MHz-70.1
dBc
Small-Signal BandwidthSSBWInput at -20dB FS440MHz
Full-Power BandwidthFPBWInput at -0.5dB FS440MHz
Aperture DelaytAD1.5ns
Aperture JittertAJ2psRMS
Overdrive Recovery Time1.5 × full-scale input2ns
INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally)REFP Output VoltageVREFP - VCOM0.256V
REFN Output VoltageVREFN - VCOM-0.256V
COM Output VoltageVCOMVDD / 2
- 0.15VDD / 2VDD / 2
+ 0.15V
Differential Reference OutputVREFVREFP - VREFN0.512V
Differential Reference Output
Temperature CoefficientVREFTC±30ppm/°C
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM Sink
CurrentISINK2mA
U F FERED EXT ER N A L R EF ER EN C E ( V R E F IN = 1.024V , V R E F P , V R E F N , and V C OM ar e g ener ated i nter nal l y)
REFIN Input VoltageVREFIN1.024V
COM Output VoltageVCOMVDD / 2
- 0.15VDD / 2VDD / 2
+ 0.15V
Differential Reference OutputVREFVREFP - VREFN0.512V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMaximum REFP/REFN/COM Sink
CurrentISINK2mA
REFIN Input Resistance>500kΩ
REFIN Input Current-0.7µA
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally)REFP Input VoltageVREFP - VCOM0.256V
REFN Input VoltageVREFN - VCOM-0.256V
COM Input VoltageVCOMVDD / 2V
Differential Reference Input
VoltageVREFVREFP - VREFN0.512V
REFP Input ResistanceRREFPMeasured between REFP and COM4kΩ
REFN Input ResistanceRREFNMeasured between REFN and COM4kΩ
DIGITAL INPUTS (CLK, PD0, PD1)CLK0.7 x
VDDInput High ThresholdVIH
PD0, PD10.7 x
OVDD
CLK0.3 x
VDDInput Low ThresholdVIL
PD0, PD10.3 x
OVDD
Input HysteresisVHYST0.1V
CLK at GND or VDD±5Digital Input Leakage CurrentDIINPD0 and PD1 at OGND or OVDD±5µA
Digital Input CapacitanceDCIN5pF
DIGITAL OUTPUTS (D7–D0, A/B)Output Voltage LowVOLISINK = 200µA0.2 x
OVDDV
Output Voltage HighVOHISOURCE = 200µA0.8 x
OVDDV
Tri-State Leakage CurrentILEAK±5µA
Tri-State Output CapacitanceCOUT5pF
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.03.6V
Digital Output Supply VoltageOVDD1.8VDDV
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, fCLK= 45MHz, CREFP= CREFN= CCOM=
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNormal operating mode, fIN = 5.5MHz at
-0.5dB FS, CLK input from GND to VDD1922.5
Idle mode (tri-state), fIN = 5.5MHz at
-0.5dB FS, CLK input from GND to VDD19
Standby mode, CLK input from
GND to VDD8.5
Analog Supply CurrentIDD
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND0.15.0µA
Normal operating mode,
fIN = 5.5MHz at -0.5dB FS, CL ≈ 10pF5mA
Idle mode (tri-state), DC input, CLK =
GND or VDD, PD0 = OVDD, PD1 = OGND0.15.0
Standby mode, DC input, CLK = GND or
VDD, PD0 = OGND, PD1 = OVDD0.1
Digital Output Supply Current
(Note 3)IODD
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND0.15.0
TIMING CHARACTERISTICSCLK Rise to CHA Output Data
ValidtDOA50% of C LK to 50% of d ata) ,
Fi g ur e 5 ( N ote 4) 168.5ns
CLK Fall to CHB Output Data
ValidtDOB50% of C LK to 50% of d ata,
Fi g ur e 5 ( N ote 4) 168.5ns
CLK Rise/Fall to A/B Rise/Fall
TimetDA/B50% of C LK to 50% of A/B,
Fi g ur e 5 ( N ote 4) 168.5ns
PD1 Rise to Output EnabletENPD0 = OVDD5ns
PD1 Fall to Output DisabletDISPD0 = OVDD5ns
CLK Duty Cycle50%
CLK Duty-Cycle Variation±10%
Wake-Up Time from Shutdown
ModetWAKE, SD(Note 5)20µs
Wake-Up Time from Standby
ModetWAKE, ST(Note 5)2.6µs
Digital Output Rise/Fall Time20% to 80%2ns
INTERCHANNEL CHARACTERISTICSCrosstalk RejectionfIN,X = 11MHz at -0.5dB FS,
fIN,Y = 0.3MHz at -0.5dB FS (Note 6)-75dB
Amplitude MatchingfIN = 11MHz at -0.5dB FS (Note 7)±0.05dB
Phase MatchingfIN = 11MHz at -0.5dB FS (Note 7)±0.2D egr ees
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, fCLK= 45MHz, CREFP= CREFN= CCOM=
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
FFT PLOT CHANNEL A (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)MAX1193 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)15510
fCLK = 45.005678MHz
fINA = 12.531448MHz
fINB = 21.005678MHz
AINA = AINB = -0.5dB FS
HD3HD2
fINB
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)MAX1193 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)15510
fCLK = 45.005678MHz
fINA = 12.531448MHz
fINB = 21.005678MHz
AINA = AINB = -0.5dB FS
HD3
HD2fINA
FFT PLOT CHANNEL A (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)MAX1193 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)15510
fCLK = 45.005678MHz
fINA = 21.005678MHz
fINB = 12.531448MHz
AINA = AINB = -0.5dB FS
HD3
HD2fINB
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)MAX1193 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)15510
fCLK = 45.005678MHz
fINA = 21.005678MHz
fINB = 12.531448MHz
AINA = AINB = -0.5dB FS
HD2
HD3fINA
TWO-TONE IMD PLOT (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)MAX1193 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)15510
fCLK = 45.005678MHz
fIN1 = 1.8MHz
fIN2 = 2.3MHz
AIN = 7dB FSfIN2
fIN1
Typical Operating Characteristics(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, fCLK= 45MHz, CREFP= CREFN= CCOM=
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA=+25°C.) (Note 1)
Note 1:Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2:SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the
amplitude of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3:The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4:Guaranteed by design and characterization. Not production tested.
Note 5:SINAD settles to within 0.5dB of its typical value.
Note 6:Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the
second channel. FFTs are performed on each channel. The parameter is specified as power ratio of the first and second
channel FFT test tone bins.
Note 7:Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYMAX1193 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
CHANNEL B
CHANNEL A
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1193 toc07
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
CHANNEL B
CHANNEL A
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1193 toc08
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
CHANNEL B
CHANNEL A
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYMAX1193 toc09
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
CHANNEL B
CHANNEL A
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWERMAX1193 toc10
ANALOG INPUT POWER (dB FS)
SNR (dB)
fIN = 11.531606MHz
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWERMAX1193 toc11
ANALOG INPUT POWER (dB FS)
SINAD (dB)
fIN = 11.531606MHz
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWERMAX1193 toc12
ANALOG INPUT POWER (dB FS)
THD (dBc)
fIN = 11.531606MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWERMAX1193 toc13
ANALOG INPUT POWER (dB FS)
SFDR (dBc)
fIN = 11.531606MHz
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATEMAX1193 toc14
fCLK (MHz)
SNR (dB)302010
fIN = 11.531606MHz
SIGNAL-TO-NOISE PLUS DISTORTION
vs. SAMPLING RATEMAX1193 toc15
fCLK (MHz)
SINAD (dB)302010
fIN = 11.531606MHz
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATEMAX1193 toc16
fCLK (MHz)
THD (dBc)302010
fIN = 11.531606MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATEMAX1193 toc17
fCLK (MHz)
SFDR (dBc)302010
fIN = 11.531606MHz
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLEMAX1193 toc18
CLOCK DUTY CYCLE (%)
SNR (dB)484256504458524660
fIN = 11.531606MHz
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK DUTY CYCLEMAX1193 toc19
CLOCK DUTY CYCLE (%)
SINAD (dB)504560
fIN = 11.531606MHz
TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLEMAX1193 toc20
CLOCK DUTY CYCLE (%)
THD (dBc)5045
fIN = 11.531606MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLEMAX1193 toc21
CLOCK DUTY CYCLE (%)
SFDR (dBc)504560
fIN = 11.531606MHz
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
INTEGRAL NONLINEARITYMAX1193 toc22
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX1193 toc23
DIGITAL OUTPUT CODE
DNL (LSB)
OFFSET ERROR
vs. TEMPERATURE
MAX1193 toc24
TEMPERATURE (°C)
OFFSET ERROR (% FS)3510-15
VREFIN = 1.024V
CHANNEL B
CHANNEL A
GAIN ERROR
vs. TEMPERATURE
MAX1193 toc25
TEMPERATURE (°C)
GAIN ERROR (% FS)3510-15-4085
VREFIN = 1.024V
CHANNEL B
CHANNEL A
INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCYMAX1193 toc26
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
SMALL-SIGNAL
BANDWIDTH
-20dB FS
FULL-POWER
BANDWIDTH
-0.5dB FS
VDD (V)
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1193 toc27
REFP
- V
REFN
(V)
VDD = VREFIN
TEMPERATURE (°C)3510-15-4085
REFERENCE VOLTAGE
vs. TEMPERATUREMAX1193 toc28
REFP
- V
REFN
(V)
VDD = VREFIN
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
SUPPLY CURRENT
vs. INPUT FREQUENCYMAX1193 toc29
fIN (MHz)
DIGITAL SUPPLY CURRENT (mA)ANALOG SUPPLY CURRENT (mA)15105
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT
SUPPLY CURRENT
vs. SAMPLING RATEMAX1193 toc30
fCLK (MHz)
SUPPLY CURRENT (mA)302010
A: ANALOG SUPPLY CURRENT (IDD) - INTERNAL AND BUFFERED EXTERNAL
REFERENCE MODES
B: ANALOG SUPPLY CURRENT (IDD) - UNBUFFERED EXTERNAL REFERENCE MODE
C: DIGITAL SUPPLY CURRENT (IODD) - ALL REFERENCE MODES
fIN = 11.531606MHz
Pin Description
PINNAMEFUNCTIONINA-Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.INA+Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
3, 5, 10GNDAnalog Ground. Connect all GND pins together.CLKConverter Clock InputINB+Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.INB-Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
8, 9, 28VDDConverter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.OGNDOutput Driver GroundOVDDOutput Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.D7Tri-State Digital Output. D7 is the most significant bit (MSB).D6Tri-State Digital OutputD5Tri-State Digital OutputD4Tri-State Digital OutputA/BChannel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data
(A/B = 0) is present on the output.D3Tri-State Digital OutputD2Tri-State Digital OutputD1Tri-State Digital OutputD0Tri-State Digital Output. D0 is the least significant bit (LSB).PD1Power-Down Digital Input 1. See Table 3.
Typical Operating Characteristics (continued)(VDD= 3.0V, OVDD= 1.8V, VREFIN= VDD(internal reference), CL≈10pF at digital outputs, differential input at -0.5dB FS, fCLK=
45.005678MHz at 50% duty cycle, TA= +25°C, unless otherwise noted.)
Detailed DescriptionThe MAX1193 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
originally held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated
until the signal has been processed by all stages. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes. Figure 2 shows the MAX1193 functional diagram.
MAX1193
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
Pin Description (continued)
PINNAMEFUNCTIONPD0Power-Down Digital Input 0. See Table 3.REFINReference Input. Internally pulled up to VDD.COMCommon-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.REFNNegative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF
capacitor.REFPPositive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33µF
capacitor.EPExposed Paddle. Internally connected to pin 3. Externally connect EP to GND.
INA+
INA-
T/H
DIGITAL ERROR CORRECTIOND0–D7
FLASH
ADC
T/H
DAC
1.5 BITS
STAGE 1STAGE 2STAGE 7
Figure 1. Pipeline Architecture—Stage Blocks
INA+
INA-
DEC/T/H
INB+
INB-
DEC/T/H
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
PIPELINE
ADC
COM
REFIN
REFN
REFP
CLKTIMING
OVDD
OGND
MULTIPLEXEROUTPUT
DRIVERS
POWER
CONTROL
D0–D7
VDD
GND
A/B
PD0
PD1
PIPELINE
ADC
MAX1193
Figure 2. MAX1193 Functional Diagram
