MAX1185ECM+TD ,Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel OutputsApplicationsINB- 8 29 N.C.INB+ 9 28 N.C.High Resolution ImagingGND 10 27 N.C.I/Q Channel Digitizati ..
MAX1187AEUI+ ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeMAX1179/MAX1187/MAX118919-2675; Rev 1; 1/0316-Bit, 135ksps, Single-Supply ADCs withBipolar Analog I ..
MAX1187AEUI+ ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeFeaturesThe MAX1179/MAX1187/MAX1189 16-bit, low-power,♦ Analog Input Voltage Range: ±10V, ±5V, or 0 ..
MAX1187BCUI ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeApplicationsD14 7 22 D1D15 8 21 D0Temperature Sensing and MonitoringR/C 9 20 DVDDIndustrial Process ..
MAX1187BCUI+ ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, external reference = +4.096V, C = 10µF, C = 0.1µF, V ..
MAX1187BEUI+ ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeFeaturesThe MAX1179/MAX1187/MAX1189 16-bit, low-power,♦ Analog Input Voltage Range: ±10V, ±5V, or 0 ..
MAX3490ECSA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490ECSA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EEPA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EESA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EESA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EESA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1185ECM+TD
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
General DescriptionThe MAX1185 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1185 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.5dB at an input frequency of
7.5MHz and a sampling rate of 20Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1185 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1185 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1185 is available in a 7mm
x 7mm, 48-pin TQFP package, and is specified for the
extended industrial (-40°C to +85°C) temperature
range.
Pin-compatible, nonmultiplexed. high-speed versions of
the MAX1185 are also available. Refer to the MAX1180
data sheet for 105Msps, the MAX1181 data sheet for
80Msps, the MAX1182 data sheet for 65Msps, the
MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps.
ApplicationsHigh Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
FeaturesSingle 3V OperationExcellent Dynamic Performance:
59.5dB SNR at fIN= 7.5MHz
74dB SFDR at fIN= 7.5MHz Low Power:35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)0.02dB Gain and 0.25°Phase MatchingWide ±1Vp-p Differential Analog Input Voltage
Range400MHz, -3dB Input BandwidthOn-Chip 2.048V Precision Bandgap ReferenceSingle 10-Bit Bus for Multiplexed, Digital OutputsUser-Selectable Output Format—Two’s
Complement or Offset Binary48-Pin TQFP Package with Exposed Pad forImproved Thermal Dissipation
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel OutputsD1A/B
D0A/B
OGND
OVDD
OVDD
OGND
A/B
N.C.
N.C.
N.C.
N.C.
N.C.
COM
VDD
GND
INA+
INA-
VDD
GND
INB-
INB+
GND
VDD
CLK
48 TQFP-EP14151617181920212223244746454443424140393837
REFNREFPREFINREFOUTD9A/BD8A/BD7A/BD6A/BD5A/BD4A/BD3A/BD2A/B
MAX1185
GND
GND
T/B
SLEEP
N.C.N.C.N.C.N.C.
Pin Configuration19-2175; Rev 3; 5/11
Ordering Information
PARTTEMP
RANGEPIN-PACKAGEMAX1185ECM-40°C to +85°C48 TQFP-EP*
MAX1185ECM+-40°C to +85°C48 TQFP-EP*
MAX1185ECM/V+-40°C to +85°C48 TQFP-EP*
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.denotes an automotive qualified part.
Pin-Compatible Versions table at end of data sheet.
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), fCLK= 20MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (VDD + 0.3V)
OE, PD, SLEEP, T/B, D9A/B–D0A/B,
A/B to OGND.......................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C
above +70°C)............................................................2430mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)
Lead(Pb)-free..............................................................+260°C
Containing lead(Pb)....................................................+240°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution10Bits
Integral NonlinearityINLfIN = 7.5MHz±0.5±1.5LSB
Differential NonlinearityDNLfIN = 7.5MHz, no missing codes guaranteed±0.25±1.0LSB
Offset Error< ±1±1.9% FS
Gain Error0±2% FS
ANALOG INPUTDifferential Input Voltage
RangeVDIFFDifferential or single-ended inputs±1.0V
Common-Mode Input Voltage
RangeVCMVDD/2
± 0.5V
Input ResistanceRINSwitched capacitor load100kΩ
Input CapacitanceCIN5pF
CONVERSION RATEMaximum Clock FrequencyfCLK20MHz
CHA5Data LatencyCHB5.5
Clock
cycles
DYNAMIC CHARACTERISTICSfINA or B = 7.5MHz, TA = +25°C57.359.5Signal-to-Noise Ratio
(Note 3)SNRfINA or B = 12MHz59.4dB
fINA or B = 7.5MHz, TA = +25°C5759.4Signal-to-Noise and Distortion
(Note 3)SINADfINA or B = 12MHz59.2dB
fINA or B = 7.5MHz, TA = +25°C6474Spurious-Free Dynamic Range
(Note 3)SFDRfINA or B = 12MHz72dBc
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), fCLK= 20MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfINA or B = 7.5MHz, TA = +25°C-72-64Total Harmonic Distortion
(First 4 Harmonics) (Note 3)THDfINA or B = 12MHz-71dBc
fINA or B = 7.5MHz-74Third-Harmonic Distortion
(Note 3)HD3fINA or B = 12MHz-72dBc
Intermodulation DistortionIMDfINA or B = 11.9852MHz at -6.5dBFS,
fI N A o r B = 12.8934M H z at - 6.5d BFS ( N ote 4) -76dBc
Small-Signal BandwidthInput at -20dBFS, differential inputs500MHz
Full-Power BandwidthFPBWInput at -0.5dBFS, differential inputs400MHz
Aperture DelaytAD1ns
Aperture JittertAJ2psRMS
Overdrive Recovery TimeFor 1.5x full-scale input2ns
Differential Gain±1%
Differential Phase±0.25D egr ees
Output NoiseINA+ = INA- = INB+ = INB- = COM0.2LSBRMS
INTERNAL REFERENCEReference Output VoltageREFOUT2.048
±3%V
Reference Temperature
CoefficientTCREF60ppm/°C
Load Regulation1.25mV/mA
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)REFIN Input VoltageVREFIN2.048V
Positive Reference Output
VoltageVREFP2.012V
Negative Reference Output
VoltageVREFN0.988V
Differential Reference Output
Voltage RangeΔVREFΔVREF = VREFP - VREFN0.951.0241.10V
REFIN ResistanceRREFIN> 50MΩ
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), fCLK= 20MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMaximum REFP, COM Source
CurrentISOURCE5mA
Maximum REFP, COM Sink
CurrentISINK-250µA
Maximum REFN Source CurrentISOURCE250µA
Maximum REFN Sink CurrentISINK-5mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)REFP, REFN Input ResistanceRREFP,
RREFN
Measured between REFP and COM, and
REFN and COM4kΩ
Differential Reference Input
VoltageΔVREFΔVREF = VREFP - VREFN1.024
±10%V
COM Input VoltageVCOMVDD/2
±10%V
REFP Input VoltageVREFPVCOM +
ΔVREF/2V
REFN Input VoltageVREFNVCOM -
ΔVREF/2V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)CLK0.8
x VDD
Input High ThresholdVIH
PD, OE, SLEEP, T/B0.8
x OVDD
CLK0.2
x VDD
Input Low ThresholdVIL
PD, OE, SLEEP, T/B0.2
x OVDD
Input HysteresisVHYST0.1V
IIHVIH = OVDD or VDD (CLK)±5Input LeakageIILVIL = 0±5µA
Input CapacitanceCIN5pF
DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)Output-Voltage LowVOLISINK = -200µA0.2V
Output-Voltage HighVOHISOURCE = 200µAOVDD
- 0.2V
Three-State Leakage CurrentILEAKOE = OVDD±10µA
Three-State Output CapacitanceCOUTOE = OVDD5pF
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), fCLK= 20MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply Voltage RangeVDD2.73.03.6V
Output Supply Voltage RangeOVDD1.72.53.6V
Operating, fINA or B = 7.5MHz at -0.5dBFS3550
Sleep mode2.8mAAnalog Supply CurrentIVDD
Shutdown, clock idle, PD = OE = OVDD115µA
Operating, CL = 15pF,
fINA or B = 7.5MHz at -0.5dBFS9mA
Sleep mode100Output Supply CurrentIOVDD
Shutdown, clock idle, PD = OE = OVDD210µA
Operating, fINA or B = 7.5MHz at -0.5dBFS105150
Sleep mode8.4mWPower DissipationPDISS
Shutdown, clock idle, PD = OE = OVDD345µW
Offset±0.2mV/VPower-Supply Rejection RatioPSRRGain±0.1%/V
TIMING CHARACTERISTICSCLK Rise to CHA Output Data
ValidtDOAFigure 3 (Note 5)58ns
CLK Fall to CHB Output Data
ValidtDOBFigure 3 (Note 5)58ns
Clock Rise/Fall to A/B Rise/Fall
TimetDA/B6ns
Output Enable TimetENABLEFigure 410ns
Output Disable TimetDISABLEFigure 41.5ns
CLK Pulse Width HightCHFigure 3, clock period: 50ns25 ± 7.5ns
CLK Pulse Width LowtCLFigure 3, clock period: 50ns25 ± 7.5ns
Wake-up from sleep mode (Note 6)0.51Wake-Up TimetWAKEWake-up from shutdown (Note 6)1.5µs
CHANNEL-TO-CHANNEL MATCHINGCrosstalkfINA or B = 7.5MHz at -0.5dBFS-70dB
Gain MatchingfINA or B = 7.5MHz at -0.5dBFS0.02±0.2dB
Phase MatchingfINA or B = 7.5MHz at -0.5dBFS0.25D eg r ees
Note 1:Equivalent dynamic performance is obtainable over full OVDDrange with reduced CL.
Note 2:Specifications at ≥+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3:SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
input voltage range.
Note 4:Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5:Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6:With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics(VDD= 3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -0.5dBFS, fCLK= 20MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1185 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
CHAfCLK = 20.0005678MHz
fINA = 5.9742906MHz
fINB = 7.5343935MHz
AINA = -0.525dBFS
HD3
HD2
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1185 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
CHBfCLK = 20.0005678MHz
fINA = 5.9742906MHz
fINB = 7.5243935MHz
AINA = -0.462dBFS
HD3
HD2
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1185 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
CHAfCLK = 20.0005678MHz
fINA = 7.5343935MHz
fINB = 11.9852035MHz
AINA = -0.489dBFS
HD3
HD2
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1185 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
CHBfCLK = 20.0005678MHz
fINA = 7.5343935MHz
fINB = 11.9852035MHz
AINA = -0.471dBFS
HD3
HD2
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1185 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
IM2IM3
IM3
fCLK = 20.0005678MHz
fIN1 = 11.9852035MHz
fIN2 = 12.8934324MHz
AIN = -6.5dBFS
fIN2
fIN151015202530354045
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYMAX1185 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)CHA
CHB51015202530354045
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCYMAX1185 toc07
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
CHB
CHA-72
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1185 toc08
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)51015202530354045
CHA
CHB
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYMAX1185 toc09
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)51015202530354045
CHA
CHB
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputsypical Operating Characteristics (continued)(VDD= 3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -0.5dBFS, fCLK= 20MHz, CL≈10pF, TA= +25°C, unless otherwise noted101001000
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDEDMAX1185 toc10
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)101001000
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDEDMAX1185 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
VIN = 100mVP-P
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc12
ANALOG INPUT POWER (dBFS)
SNR (dB)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc13
ANALOG INPUT POWER (dBFS)
SINAD (dB)
-20-12-16-8-4 0
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (fIN = 7.53MHz)MAX1185 toc14
ANALOG INPUT POWER (dBFS)
THD (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (fIN = 7.53MHz)
MAX1185 toc15
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
INTEGRAL NONLINEARITY
(BEST END-POINT FIT)
MAX1185 toc16
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX1185 toc17
DIGITAL OUTPUT CODE
DNL (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1185 toc18
TEMPERATURE (°C)
GAIN ERROR (%FS)-153560
CHB
CHA
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel OutputsOFFSET ERROR vs. TEMPERATURE
MAX1185 toc19
TEMPERATURE (°C)
OFFSET ERROR (%FS)-153560
CHB
CHA
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc20
VDD (V)
IVDD
(mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1185 toc21
TEMPERATURE (°C)
IVDD
(mA)
ANALOG POWER-DOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc22
VDD (V)
IVDD
OE = PD = OVDD40455055606570
SNR/SINAD, -THD/SFDR
vs. CLOCK DUTY CYCLEMAX1185 toc23
CLOCK DUTY CYCLE (%)
SNR/SINAD, -THD/SFDR (dB, dBc)
SFDR
fINA/B = 7.53MHz
SNR
SINAD
THD
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1185 toc24
VDD (V)
REFOUT
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1185 toc25
REOUT
(V)-153560
21,000
14,000
7,000
28,000
35,000
42,000
49,000
56,000
63,000
70,000
OUTPUT NOISE HISTOGRAM (DC INPUT)MAX1185 toc26
COUNTS
64,515
N-1
N+1
N+2
N-2
ypical Operating Characteristics (continued)(VDD= 3V, OVDD= 2.5V, VREFIN= 2.048V, differential input at -0.5dBFS, fCLK= 20MHz, CL≈10pF, TA= +25°C, unless otherwise noted.)
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description
PINNAMEFUNCTIONCOMCommon-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.
2, 6, 11, 14, 15VDDAnalog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog
supply accepts a 2.7V to 3.6V input range.
3, 7, 10, 13, 16GNDAnalog GroundINA+Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.INA-Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.INB-Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.INB+Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.CLKConverter Clock InputT/B
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.SLEEP
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.PD
Power-Down Input.
High: Power-down mode.
Low: Normal operation.OE
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
21–29N.C.Do not connect.A/BA/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0)
to be present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34OGNDOutput Driver Ground
32, 33OVDDOutput Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output
driver supply accepts a 1.7V to 3.6V input range.D0A/BThree-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.D1A/BThree-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A
or channel B data.D2A/BThree-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A
or channel B data.D3A/BThree-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A
or channel B data.D4A/BThree-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A
or channel B data.D5A/BThree-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A
or channel B data.
Detailed DescriptionThe MAX1185 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con-
verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (five
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.
Input Track-and-Hold (T/H) CircuitsFigure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out-
put of the amplifier and switch S4c is closed. The result-
ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang-
ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1185 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA- as
well as INB+ and INB- and set the common-mode volt-
age to midsupply (VDD/2) for optimum performance.
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PINNAMEFUNCTIOND6A/BThree-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A
or channel B data.D7A/BThree-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A
or channel B data.D8A/BThree-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A
or channel B data.D9A/BThree-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects
channel A or channel B data.REFOUTInternal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.REFINReference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor.REFPPositive Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with
a > 0.1µF capacitor.REFNNegative Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with
a > 0.1µF capacitor.EPExposed Pad. Connect to analog ground.
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel OutputsT/HVOUTx2Σ
FLASH
ADCDAC
1.5 BITS
VINA
VIN
STAGE 1STAGE 2
DIGITAL CORRECTION LOGIC
STAGE 8STAGE 9
2-BIT FLASH
ADC
T/H
T/HVOUTx2Σ
FLASH
ADCDAC
1.5 BITS
VINB
VIN
STAGE 1STAGE 2
DIGITAL CORRECTION LOGIC
STAGE 8STAGE 9
2-BIT FLASH
ADC
T/H
OUTPUT
MULTIPLEXER
D0A/B–D9A/B
Figure 1. Pipelined Architecture—Stage Blocks
S3b
S3a
COM
S5b
S5a
INB+
INB-
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL BIAS
INTERNAL BIAS
COM
HOLDHOLDCLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACKTRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
INA+
INA-
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL BIAS
INTERNAL BIAS
COM
S2a
S2b
MAX1185
