MAX1168BEEG+ ,Multichannel, 16-Bit, 200ksps Analog-to-Digital ConvertersApplicationsPIN- INL PART TEMP RANGEMotor ControlPACKAGE (LSB)Industrial Process ControlMAX1167BCEE ..
MAX1169AEUD ,58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOPfeatures automatic power-down, an on-chip1.7MHz High-Speed Mode4MHz clock, a +4.096V internal refer ..
MAX1169BCUD ,58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOPApplicationsMAX1169AEUD* -40°C to +85°C 14 TSSOP ±2Medical Instruments MAX1169BEUD* -40°C to +85°C ..
MAX1169BCUD+ ,58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOPApplicationsMedical InstrumentsPin ConfigurationBattery-Powered Test EquipmentSolar-Powered Remote ..
MAX1169CCUD+ ,58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOPELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.7V to +5.5V, f = 1.7MHz (33% duty cycle), f ..
MAX1174BCUP ,14-Bit / 135ksps / Single-Supply ADCs with Bipolar Analog Input RangeApplications Typical Operating CircuitTemperature Sensing and Monitoring+5V ANALOG +5V DIGITALIndus ..
MAX3486ESA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ESA-T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3488CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3488CSA+ ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3488ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3488ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1167BCEE+-MAX1168BEEG+
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
General DescriptionThe MAX1167/MAX1168 low-power, multichannel, 16-
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1167/MAX1168 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
The MAX1167/MAX1168 consume only 3.6mA (AVDD=
DVDD= +5V) at 200ksps when using an external reference.
AutoShutdown™ reduces the supply current to 185µA at
10ksps and to less than 10µA at reduced sampling rates.
The MAX1167 includes a 4-channel input multiplexer, and
the MAX1168 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con-
versions are simplified with the DSP frame-sync input and
output featured in the MAX1168. The MAX1168 includes
a data-bit transfer input to select between 8-bit-wide or
16-bit-wide data-transfer modes. Both devices feature a
scan mode that converts each channel sequentially or
one channel continuously.
Excellent dynamic performance and low power, com-
bined with ease of use and an integrated reference, make
the MAX1167/MAX1168 ideal for control and data-acqui-
sition operations or for other applications with demanding
power consumption and space requirements. The
MAX1167 is available in a 16-pin QSOP package and the
MAX1168 is available in a 24-pin QSOP package. Both
devices are guaranteed over the commercial (0°C to
+70°C) and extended (-40°C to +85°C) temperature
ranges. Use the MAX1168 evaluation kit to evaluate the
MAX1168.
ApplicationsMotor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Features16-Bit Resolution, No Missing Codes+5V Single-Supply OperationAdjustable Logic Level (+2.7V to +5.25V)Input Voltage Range: 0 to VREFInternal (+4.096V) or External (+3.8V to AVDD)
ReferenceInternal Track/Hold, 4MHz Input BandwidthInternal or External ClockSPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1168 Performs DSP-Initiated
Conversions8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
(MAX1168 Only)4-Channel (MAX1167) or 8-Channel (MAX1168)
Input Mux
Scan Mode Sequentially Converts Multiple
Channels or One Channel ContinuouslyLow Power
3.6mA at 200ksps
1.85mA at 100ksps
185µA at 10ksps
0.6µA in Full Power-Down ModeSmall Package Size
16-Pin QSOP (MAX1167)
24-Pin QSOP (MAX1168)
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Ordering Information19-2956; Rev 1; 10/09
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
INL
(LSB)
MAX1167BCEE 0°C to +70°C 16 QSOP ±3
MAX1167BEEE -40°C to +85°C 16 QSOP ±3
MAX1168BCEG 0°C to +70°C 24 QSOP ±3
MAX1168BEEG -40°C to +85°C 24 QSOP ±3
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +6V
DVDDto DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD+ 0.3V)
SCLK, CS, DSEL, DSPR, DIN to DGND...................-0.3V to +6V
DOUT, DSPX, EOCto DGND...................-0.3V to (DVDD+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Operating Temperature Ranges
MAX116_ _ CE_..................................................0°C to +70°C
MAX116_ _ EE_...............................................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1) Resolution 16 Bits
Relative Accuracy (Note 2) INL MAX116_B ±1.8±3LSB
Differential Nonlinearity DNL MAX116_B
(16 bit, no missing codes over temperature)
16-bit
NMC +0.7 +1.75 LSB
External reference 0.7 Transition Noise RMS
noise Internal reference 0.8 LSBRMS
Offset Error ±0.1 ±10 mV
Gain Error (Note 3) ±0.01 ±0.2 %FSR
Offset Drift 1 ppm/°C
Gain Drift (Note 3) ±1.2 ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P)(Note 1)
Signal-to-Noise Plus Distortion SINAD 85 88.5 dB
Signal-to-Noise Ratio SNR 86 88.5 dB
Total Harmonic Distortion THD -100 -88 dB
Spurious-Free Dynamic Range SFDR 88 101 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 85dB 10 kHz
Channel-to-Channel Isolation (Note 4) 96 dB
CONVERSION RATE Internal clock, no data transfer,
single conversion (Note 5) 5.52 7.07 Conversion Time tCONV
External clock 3.75
μs
Acquisition Time tACQ (Note 6) 729 ns
External clock, data transfer and conversion 0.1 4.8 Serial Clock Frequency fSCLKExternal clock, data transfer only 9MHz
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInternal Clock Frequency fINTCLK Internal clock 3.2 4.0 MHz
Aperture Delay tAD 15 ns
Aperture Jitter tAJ <50 ps
8-bit-wide data-transfer mode 4.17 200.00
16-bit-wide data-transfer mode 3.125 150.00
Internal clock, single conversion, 8-bit-wide
data-transfer mode 89
Internal clock, single conversion, 16-bit-
wide data-transfer mode 68
Internal clock, scan mode, 8-bit-wide data-
transfer mode (four conversions) 103
Sample Rate (Note 7) fS
External clock, scan mode, 16-bit-wide
data-transfer mode (four conversions) 82
ksps
Duty Cycle 45 55 %
ANALOG INPUT (AIN_) Input Range VAIN_ 0 VREF V
Input Capacitance CAIN_ 45 pF
EXTERNAL REFERENCE Input Voltage Range VREF (Note 8) 3.8 AVDD
- 0.2 V
VAIN_ = 0 34
SCLK idle 0.1Input Current IREF
CS = DVDD, SCLK idle 0.1
μA
INTERNAL REFERENCE Reference Voltage VREFIN 4.042 4.096 4.136 V
Reference Short-Circuit Current IREFSC 13 mA
Reference Temperature
Coefficient ±25 ppm/°C
Reference Wake-Up Time tRWAKE VREF = 0 5 ms
DIGITAL INPUTS (SCLK, CS, DSEL, DSPR, DIN) (DVDD = +2.7V to +5.25V) Input High Voltage VIH0.7
DVDD V
Input Low Voltage VIL 0.3
DVDDV
Input Leakage Current IIN Digital inputs = 0 to DVDD ±0.1±1 μA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL OUTPUT (DOUT, DSPX, EOC) (DVDD = +2.7V to +5.25V) Output High Voltage VOH ISOURCE = 0.5mA DVDD -
0.4 V
ISINK = 10mA, DVDD = +4.75V to +5.25V 0.8 Output Low Voltage VOLISINK = 1.6mA, DVDD = +2.7V to +5.25V 0.4 V
Three-State Output Leakage
Current ILCS = DVDD ±0.1±10 μA
Three-State Output Capacitance COUTCS = DVDD 15 pF
POWER SUPPLIES Analog Supply AVDD 4.75 5.25 V
Digital Supply DVDD 2.70 5.25 V
External reference 2.7 3.3 200ksps Internal reference 3.6 4.2
External reference 1.4 100ksps Internal reference 2.7
External reference 0.14 10ksps Internal reference 1.8
External reference 0.014
Analog Supply Current (Note 9) IAVDD
1ksps Internal reference 1.7
mA
200ksps 0.87 1.3
100ksps 0.45
10ksps 0.045 Digital Supply Current IDVDDDOUT =
all zeros
1ksps 0.005
mA
Internal reference and
reference buffer on
between conversions
0.66
Power-Down Supply Current IAVDD +
IDVDD
CS = DVDD,
SCLK = 0,
DIN = 0,
DSPR = DVDD
Internal reference on,
reference buffer off
between conversions
0.20
mA
Shutdown Supply Current IAVDD +
IDVDD
CS = DVDD, SCLK = 0, DIN = 0,
DSPR = DVDD, full power-down 0.6 10 μA
Power-Supply Rejection Ratio PSRR AVDD = DVDD = 4.75V to 5.25V, full-scale
input (Note 10) 63 dB
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)(AVDD
= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external
VREF= +4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQExternal clock (Note 6)729ns
SCLK to DOUT ValidtDOCDOUT = 30pF50ns
CS Fall to DOUT EnabletDVCDOUT = 30pF80ns
CS Rise to DOUT DisabletTRCDOUT = 30pF80ns
CS Pulse WidthtCSW100ns
SCLK riseCS to SCLK SetuptCSSSCLK fall (DSP)100ns
SCLK riseCS to SCLK HoldtCSHSCLK fall (DSP)0ns
Conversion93SCLK High Pulse WidthtCHDuty cycle 45% to 55%Data transfer50ns
Conversion93SCLK Low Pulse WidthtCLDuty cycle 45% to 55%Data transfer50ns
SCLK PeriodtCP209ns
SCLK riseDIN to SCLK SetuptDSSCLK fall (DSP)50ns
SCLK riseDIN to SCLK HoldtDHSCLK fall (DSP)0ns
CS Falling to DSPR RisingtDF100ns
DSPR to SCLK Falling SetuptFSS100ns
DSPR to SCLK Falling HoldtFSH0ns
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)(AVDD= +4.75V to +5.25V, DVDD
= +2.7V to +5.25V, fSCLK= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion
(200ksps), external VREF= +4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQExternal clock (Note 6)729ns
SCLK to DOUT ValidtDOCDOUT = 30pF100ns
CS Fall to DOUT EnabletDVCDOUT = 30pF100ns
CS Rise to DOUT DisabletTRCDOUT = 30pF80ns
CS Pulse WidthtCSW100ns
SCLK riseCS to SCLK SetuptCSSSCLK fall (DSP)100ns
SCLK riseCS to SCLK HoldtCSHSCLK fall (DSP)0ns
Conversion93SCLK High Pulse WidthtCHDuty cycle 45% to 55%Data transfer93ns
Conversion93SCLK Low Pulse WidthtCLDuty cycle 45% to 55%Data transfer93ns
SCLK PeriodtCP209ns
SCLK riseDIN to SCLK SetuptDSSCLK fall (DSP)100ns
SCLK riseDIN to SCLK HoldtDHSCLK fall (DSP)0ns
CS Falling to DSPR RisingtDF100ns
DSPR to SCLK Falling SetuptFSS100ns
DSPR to SCLK Falling HoldtFSH0ns
Note 1:AVDD= DVDD= +5.0V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3:Offset and reference errors nulled.
Note 4:DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Note 5:Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOCtransition minus tACQin 8-bit
data-transfer mode.
Note 6:See Figures 10 and 17.
Note 7:fSCLK= 4.8MHz, fINTCLK= 4.0MHz. Sample rate is calculated with the formula fs= n1(n2 / fSCLK+ n3 / fINTCLK)-1where:= number of scans, n2= number of SCLK cycles, and n3= number of internal clock cycles (see Figures 11–14).
Note 8:Guaranteed by design; not production tested.
Note 9:Internal reference and buffer are left on between conversions.
Note 10:Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CDOUT= 30pF, external VREF= +4.096V, TA= +25°C, unless otherwise noted.)
INL vs. CODE
MAX1167/68 toc01
CODE
INL (LSB)
DNL vs. CODE
MAX1167/68 toc02
CODE
DNL (LSB)
FFT AT fAIN = 1kHz
MAX1167/68 toc03
FREQUENCY (kHz)
AMPLITUDE (dB)
SINAD vs. FREQUENCYMAX1167/68 toc04
FREQUENCY (kHz)
SINAD (dB)1
fSAMPLE = 200kbps
SFDR vs. FREQUENCYMAX1167/68 toc05
FREQUENCY (kHz)
SFDR (dB)1
fSAMPLE = 200ksps
THD vs. FREQUENCYMAX1167/68 toc06
FREQUENCY (kHz)
THD (dB)1
fSAMPLE = 200kbps
SUPPLY CURRENT vs. CONVERSION RATE
(EXTERNAL CLOCK)MAX1167/68 toc07
CONVERSION RATE (ksps)
SUPPLY CURRENT (mA)
IAVDD, INT REF
IAVDD, EXT REF
DVDD = AVDD = +5V
DOUT = ALL ZEROS
EXTERNAL CLOCK
SPI MODE
IDVDD
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(INTERNAL REFERENCE)MAX1167/68 toc08
IAVDD
(mA)
DVDD = +5V
fS = 200ksps
TA = 0°C
TA = -40°C
TA = +85°C
TA = +70°C
TA = +25°C
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(EXTERNAL REFERENCE)MAX1167/68 toc09
IAVDD
(mA)
TA = 0°C
TA = -40°C
TA = +85°C
TA = +70°C
TA = +25°C
DVDD = +5V
fS = 200ksps
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CDOUT= 30pF, external VREF= +4.096V, TA= +25°C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1167/68 toc10
DVDD (V)
DVDD
(mA)
AVDD = +5V
VIL = 0
VIH = DVDD
fS = 200ksps
DOUT = 1010...1010
DOUT = 0000...0000
POWER-DOWN SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
(INTERNAL REFERENCE)MAX1167/68 toc11
AVDD (V)
IDVDD
IAVDD
(mA)
DVDD = +5V
IAVDD
IDVDD
POWER-DOWN SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
(INTERNAL REFERENCE)MAX1167/68 toc12
DVDD (V)
IDVDD
IAVDD
(mA)
DVDD = +5VAVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
(EXTERNAL REFERENCE)MAX1167/68 toc13
AVDD (V)
IDVDD
IAVDD
(nA)
DVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
(EXTERNAL REFERENCE)MAX1167/68 toc14
DVDD (V)
DVDD
IAVDD
(nA)
DVDD = +5VAVDD = +5V
IAVDD
IDVDD
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE (INTERNAL REFERENCE)MAX1167/68 toc15
IDVDD
IAVDD
(mA)3510-15
DVDD = AVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (EXTERNAL REFERENCE)MAX1167/68 toc16
DVDD
IAVDD
(nA)3510-15
DVDD = AVDD = +5V
IAVDD
IDVDD
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CDOUT= 30pF, external VREF= +4.096V, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGEMAX1167/68 toc17
AVDD (V)
OFFSET ERROR (
VREF = +4.096V
GAIN ERROR vs. SUPPLY VOLTAGEMAX1167/68 toc18
AVDD (V)
GAIN ERROR (%FSR)
VREF = +4.096V
OFFSET ERROR vs. TEMPERATUREMAX1167/68 toc19
TEMPERATURE (°C)
OFFSET ERROR (3510-15
VREF = +4.096V
GAIN ERROR vs. TEMPERATUREMAX1167/68 toc20
TEMPERATURE (°C)
GAIN ERROR (%FSR)3510-15
VREF = +4.096V
CHANNEL-TO-CHANNEL ISOLATION
vs. FREQUENCYMAX1167/68 toc21
FREQUENCY (kHz)
ISOLATION (dB)604020
INTERNAL +4.096V REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1167/68 toc22
AVDD (V)
REF
(V)
DVDD = +5V
TA = 0°CTA = -40°C
TA = +85°C
TA = +25°C
TA = +70°C
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE VOLTAGEMAX1167/68 toc23
VREF (V)
IREF
(μ
VAIN = 0
fSCLK = 4.8MHz
AVDD = DVDD = +5V
199ksps, EXTERNAL CLOCK
87.19ksps, INTERNAL CLOCK
INTERNAL REFERENCE VOLTAGE
vs. REF LOADMAX1167/68 toc24
IREF (mA)
REF
(V)106842
fSCLK = 0
INTERNAL REFERENCE MODE
LOAD APPLIED TO REF
CREF = 1μF
INTERNAL CLOCK CONVERSION TIME
(8th RISING SCLK TO FALLING EOC)MAX1167/68 toc25
NUMBER OF SCAN-MODE CONVERSIONS
tCONV
(ms)765432
fSCLK = 4.8MHz
8-BIT DATA-TRANSFER MODE
16-BIT DATA-TRANSFER MODE121722
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description
PIN
MAX1167MAX1168
NAMEFUNCTION3DOUT
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance
when CS is high.4SCLKSerial Clock Input. SCLK drives the conversion process in external clock mode and clocks
data out.5DIN
Serial Data Input. Use DIN to communicate with the command/configuration/control
register. In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In
DSP mode, the falling edge of SCLK clocks in data at DIN.EOCEnd-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
conversion with the result available at DOUT. In external clock mode, EOC remains high.7AIN0Analog Input 08AIN1Analog Input 19AIN2Analog Input 210AIN3Analog Input 315REFReference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND
with a 10µF capacitor. Bypass with a 1µF (min) capacitor when using internal reference.16REFCAPRefer ence Byp ass C ap aci tor C onnecti on. Byp ass to AG N D w i th a 0.1µF cap aci tor w hen
usi ng i nter nal r efer ence. Inter nal r efer ence and b uffer shut d ow n i n exter nal r efer ence m od e.17AGNDAnalog Ground. Connect to pin 18 (MAX1168) or pin 12 (MAX1167).18AGNDPrimary Analog Ground (Star Ground). Power return for AVDD.19AVDDAnalog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.20CS
Active-Low Chip-Select Input. Forcing CS high places the MAX1167/MAX1168 in shutdown
with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low
transition on CS activates normal operating mode. In DSP mode, after the initial CS
transition from high to low, CS can remain low for the entire conversion process (see the
Operating Modes section).21DGNDDigital Ground22DVDDDigital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.1DSPRDSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.2DSEL
Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not
leave DSEL unconnected.11AIN4Analog Input 412AIN5Analog Input 5
Detailed DescriptionThe MAX1167/MAX1168 low-power, multichannel, 16-bit
ADCs feature a successive-approximation ADC, auto-
matic power-down, integrated +4.096V reference, and a
high-speed SPI/QSPI/MICROWIRE-compatible interface.
A DSPR input and DSPX output allow the MAX1168 to
communicate with digital signal processors (DSPs) with
no external glue logic. The MAX1167/MAX1168 operate
with a single +5V analog supply and feature a separate
digital supply, allowing direct interfacing with +2.7V to
+5.5V digital logic.
Figures 3 and 4 show the functional diagrams of the
MAX1167/MAX1168, and Figures 5 and 6 show the
MAX1167/MAX1168 in a typical operating circuit. The
serial interface simplifies communication with micro-
processors (µPs).
In external reference mode, the MAX1167/MAX1168
have two power modes: normal mode and shutdown
mode. Driving CShigh places the MAX1167/MAX1168 in
shutdown mode, reducing the supply current to 0.6µA
(typ). Pull CSlow to place the MAX1167/MAX1168 in
normal operating mode. The internal reference mode
offers software-programmable, power-down options as
shown in Table 5.
In SPI/QSPI/MICROWIRE mode, a falling edge on CS
wakes the analog circuitry and allows SCLK to clock in
data. Acquisition and conversion are initiated by SCLK.
The conversion result is available at DOUT in unipolar
serial format. DOUT is held low until data becomes
available (MSB first) on the 8th falling edge of SCLK
when in 8-bit transfer mode, and on the 16th falling
edge when in 16-bit transfer mode (see the Operating
Modessection). Figure 8 shows the detailed SPI/QSPI/
MICROWIRE serial-interface timing diagram.
In external clock mode, the MAX1168 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
DSP initiates a conversion that is driven by SCLK. The
MAX1168 formats a frame-sync pulse to notify the DSP
that the conversion results are available at DOUT in
MSB-first, unipolar, serial-data format. Figure 16 shows
the detailed DSP serial-interface timing diagram (see the
Operating Modessection).
Analog InputFigure 7 illustrates the input-sampling architecture of
the ADC. The voltage applied at REF or the internal
+4.096V reference sets the full-scale input voltage.
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description (continued)
PIN
MAX1167MAX1168NAMEFUNCTION13AIN6Analog Input 614AIN7Analog Input 723DSPXDSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.24N.C.No Connection. Not internally connected.
DGND
1mACLOAD = 30pF
DOUTDOUT
CLOAD = 30pF
1mA
DGND
DVDD
a) VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-
DOUT Delay Time
DGND
1mACLOAD = 30pF
DOUTDOUT
CLOAD = 30pF
1mA
DGND
DVDD
a) VOH TO HIGH-Zb) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
MAX1167/MAX1168
Track/Hold (T/H)In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive digital-to-analog converter
(DAC) samples the analog input.
During the acquisition, the analog input (AIN_) charges
capacitor CDAC. At the end of the acquisition interval
the T/H switches open. The retained charge on CDAC
represents a sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to zero within the limits of 16-bit resolution. At the
end of the conversion, force CS high and then low to
reset the T/H switches back to track mode (AIN_),
where CDACcharges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ= 11(RS+ RIN+ RDS(ON)) ✕45pF + 0.3µs
where RIN= 340Ω, RS= the input signal’s source
impedance, RDS(ON)= 60Ω, and tACQis never less
than 729ns. A source impedance of less than 200Ω
does not significantly affect the ADC’s performance.
Multichannel, 16-Bit, 200ksps Analog-to-Digital
ConvertersREFERENCE
REF
REFCAPAVDDDVDD
AGND
AGNDDGND
AIN0
AIN1
AIN2
AIN3
SCLK
DIN
ANALOG-INPUT
MULTIPLEXER
MULTIPLEXER
CONTROL
ACCUMULATOR
MEMORY
INPUT REGISTER
BIAS
OSCILLATOR
OUTPUTDOUT
EOC
ANALOG-SWITCH FINE TIMING
SUCCESSIVE-APPROXIMATION
REGISTER
MAX1167
DAC
BUFFER
RAIL
COMPARATOR
Figure 3. MAX1167 Functional Diagram
The MAX1168 features a 16-bit-wide data-transfer
mode that includes a longer acquisition time (11.5
clock cycles). Longer acquisition times are useful in
applications with input source resistances greater than
1kΩ. Noise increases when using large source resis-
tances. To improve the input signal bandwidth under
AC conditions, drive AIN_ with a wideband buffer
(>10MHz) that can drive the ADC’s input capacitance
and settle quickly.
Input BandwidthThe ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, making possible the digitization of
high-speed transient events and the measurement of
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted, high-frequency signals into
the frequency band of interest, use anti-alias filtering.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to AVDDor AGND, allow the input to swing from
(AGND - 0.3V) to (AVDD+ 0.3V) without damaging the
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
ConvertersREFERENCE
REF
REFCAPAVDDDVDD
AGND
AGNDDGND
AIN0
AIN1
AIN2
AIN3
SCLK
DIN
ANALOG-INPUT
MULTIPLEXER
MULTIPLEXER
CONTROL
ACCUMULATOR
MEMORY
INPUT REGISTER
BIAS
OSCILLATOR
OUTPUTDOUT
EOC
ANALOG-SWITCH FINE TIMING
SUCCESSIVE-APPROXIMATION
REGISTER
MAX1168
DAC
BUFFER
AIN4
AIN5
AIN6
AIN7
RAIL
COMPARATOR
DSPXDSEL
DSPR
Figure 4. MAX1168 Functional Diagram
MAX1167/MAX1168
Digital InterfaceThe MAX1167/MAX1168 feature an SPI/QSPI/
MICROWIRE-compatible, 3-wire serial interface. The
MAX1167 digital interface consists of digital inputs CS,
SCLK, and DIN and outputs DOUT and EOC. The
MAX1167 operates in the following modes:SPI interface with external clockSPI interface with internal clockSPI interface with internal clock and scan mode
In addition to the standard 3-wire serial interface modes,
the MAX1168 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode and
a DSEL input to determine 8-bit-wide or 16-bit-wide data-
transfer mode. When not using the MAX1168 in the DSP
interface mode, connect DSPR to DVDDand leave DSPX
unconnected.
Command/Configuration/Control RegisterTable 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
power-on-reset default state.
Initialization After Power-UpA logic high on CSplaces the MAX1167/MAX1168 in
the shutdown mode chosen by the power-down bits,
and places DOUT in a high-impedance state. Drive CS
low to power up and enable the MAX1167/MAX1168
before starting a conversion. In internal reference
mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
conversion. In external reference mode (or if the inter-
nal reference is already on), no reference settling time
is needed after power-up.
Multichannel, 16-Bit, 200ksps Analog-to-Digital
ConvertersSCLK
DOUT
AGND
DGND
AIN0
REF
AVDD
DVDD
DOUT
SCLK
+5V
DIN
ANALOG
INPUTS
+5V
1μF
0.1μF
0.1μF
GND
MAX1167
0.1μF
AIN1
AIN2
AIN3
DIN
EOCEOC
AGND
REFCAP
Figure 5. MAX1167 Typical Operating Circuit
SCLK
DOUT
AGND
DGND
AIN0
REF
AVDD
DVDD
DOUT
SCLK
+5V8
DIN
ANALOG
INPUTS
+5V
1μF
0.1μF
0.1μF
GND
MAX1168
0.1μF
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DIN
DSEL
DSPR
DSPXDSPX
EOC
AGND
REFCAP
EOC
Figure 6. MAX1168 Typical Operating Circuit
AUTOZERO
RAIL
CAPACITIVE
DAC
CDAC
REF
AGND
TRACK
HOLD
HOLDTRACK
ZERO
MUX
RIN
RDSON
AIN_
CMUX
CSWITCH
Figure 7. Equivalent Input Circuit
BIT7 (MSB)BIT6BIT5BIT4BIT3BIT2BIT1BIT0 (LSB)COMMANDCH SEL2CH SEL1CH SEL0SCAN1SCAN0REF/PD_SEL1REF/PD SEL0INT/EXT CLKPOWER-UP00000110
Table 1. Command/Configuration/Control Register
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
BIT7BIT6BIT5
CH SEL2CH SEL1CH SEL0
CHANNEL
AIN_0011021304150617
Table 2. Channel Select
BIT4BIT3ACTIONSCAN1SCAN0Single channel, no scan00
Sequentially scan channels 0 through N
(N ≤ 3)01
Sequentially scan channels 2 through N
(2 ≤ N ≤ 3)10
Scan channel N four times11
Table 3. MAX1167 Scan Mode, Internal
Clock Only
BIT4BIT3ACTIONSCAN1SCAN0Single channel, no scan00
Sequentially scan channels 0 through N
(N ≤ 7)01
Sequentially scan channels 4 through N
(4 ≤ N ≤ 7)10
Scan channel N eight times11
Table 4. MAX1168 Scan Mode, Internal
Clock Only (Not for DSP Mode)
BIT2BIT1
REF/PD_
SEL1
REF/PD
SEL0
REFERENCEREFERENCE MODE
(INTERNAL REFERENCE)
TYPICAL
SUPPLY
CURRENT
TYPICAL WAKE-
UP TIME
(CREF = 1µF)0InternalInternal reference and reference buffer on
between conversions1mANA1InternalInternal reference and reference buffer off
between conversions0.6µA5ms0InternalInternal reference on, reference buffer off
between conversions0.43mA5ms1ExternalInternal reference and buffer always off0.6µANA
Table 5. Power-Down Modes
BIT0
INT/EXT
CLK
CLOCK MODEExternal clockInternal clock
Table 6. Clock Modes
