MAX1162ACUB+ ,16-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1162BEUB+ ,16-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with +2.7V to +5.25V digital logic.♦ ..
MAX11645EUA+T ,Low-Power, 1-/2-Channel, I²C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm PackageApplications IndicatorsOrdering InformationMedical Instruments System Supervision2PIN- I C SLAVE Ba ..
MAX1165AEUI+ ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceELECTRICAL CHARACTERISTICS(AV = DV = +5V, external reference = +4.096V, C = 4.7µF, C = 0.1µF, T = T ..
MAX1165BCUI ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceApplications*Future product—contact factory for availability.Temperature Sensor/MonitorIndustrial P ..
MAX1166BCUP ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceMAX1165/MAX116619-2551; Rev 2; 8/08Low-Power, 16-Bit Analog-to-Digital Converterswith Parallel Inte ..
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EEPA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1162ACUB+-MAX1162BEUB+
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
General DescriptionThe MAX1162 low-power, 16-bit analog-to-digital con-
verter (ADC) features a successive-approximation ADC,
automatic power-down, fast 1.1µs wakeup, and a high-
speed SPI™/QSPI™/MICROWIRE™-compatible inter-
face. The MAX1162 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with +2.7V to +5.25V digital logic.
At the maximum sampling rate of 200ksps, the
MAX1162 consumes typically 2.75mA. Power con-
sumption is typically 13.75mA (AVDD= DVDD= +5V) at
a 200ksps (max) sampling rate. AutoShutdown™
reduces supply current to 140µA at 10ksps and to less
than 10µA at reduced sampling rates.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
µMAX®and 10-pin DFN) make the MAX1162 ideal for
battery-powered and data-acquisition applications or
for other circuits with demanding power consumption
and space requirements.
ApplicationsMotor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
Features16-Bit Resolution, No Missing Codes+5V Single-Supply OperationAdjustable Logic Level (+2.7V to +5.25V)Input-Voltage Range: 0 to VREFInternal Track/Hold, 4MHz Input BandwidthSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSmall 10-Pin µMAX or 10-Pin DFN PackageLow Power
2.75mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
ShutdownAIN
AGND
DVDD
DGNDCS
AGND
AVDD
REF
MAX1162
µMAX/DFNTOP VIEW
DOUTSCLK
Pin Configuration
Ordering Information19-2525; Rev 1; 4/10
Functional Diagram appears at end of data sheet.
PARTTEMP
RANGE
PIN-
PACKAGE
INL
(LSB)MAX1162BCUB+0°C to +70°C10 µMAX±2
MAX1162BC_B*0°C to +70°C10 DFN±2
MAX1162CCUB+0°C to +70°C10 µMAX±4
MAX1162CC_B*0°C to +70°C10 DFN±4
MAX1162BEUB+-40°C to +85°C10 µMAX±2.5
MAX1162BE_B*-40°C to +85°C10 DFN±2.5
MAX1162CEUB+-40°C to +85°C10 µMAX±4
MAX1162CE_B*-40°C to +85°C10 DFN±4
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
*Future product—contact factory for DFN package availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, CREF= 4.7µF,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +6V
DVDDto DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN, REF to AGND...................................-0.3V to (AVDD + 0.3V)
SCLK, CSto DGND..................................................-0.3V to +6V
DOUT to DGND.......................................-0.3V to (DVDD + 0.3V)
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW
Operating Temperature Ranges
MAX1162_CUB .................................................0°C to +70°C
MAX1162_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)Resolution16Bits
TA = -40°C-2.5+2.5
TA = 0°C-2+2MAX1162B
TA = +85°C-2+2
TA = -40°C-4+4
TA = 0°C-4+4
Relative Accuracy (Note 2)INL
MAX1162C
TA = +85°C-4+4
LSB
TA = -40°CNMC*2
TA = 0°CNMC*1.75MAX1162B
TA = +85°CNMC*1.75
TA = -40°C-2+2
TA = 0°C-2+2
Differential NonlinearityDNL
MAX1162C
TA = +85°C-2+2
LSB
Transition NoiseRMS noise±0.65LSBRMS
Offset Error0.11mV
Gain Error(Note 3)±0.002±0.01%FSR
Offset Drift0.4ppm/oC
Gain Drift(Note 3)0.2ppm/oC
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, CREF= 4.7µF,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-Signal-to-Noise Plus DistortionSINAD8689.5dB
Signal-to-Noise RatioSNR8790dB
Total Harmonic DistortionTHD-90dB
Spurious-Free Dynamic RangeSFDR92103dB
Full-Power Bandwidth-3dB point4MHz
Full-Linear BandwidthSINAD > 86dB10kHz
CONVERSION RATEConversion TimetCONV(Note 4)5240µs
Serial Clock FrequencyfSCLK0.14.8MHz
Aperture DelaytAD15ns
Aperture JittertAJ<50ps
Sample RatefSfSCLK / 24200ksps
Track/Hold Acquisition TimetACQ1.1µs
ANALOG INPUT (AIN)Input RangeVAIN0VREFV
Input CapacitanceCAIN40pF
EXTERNAL REFERENCEInput-Voltage RangeVREF3.8AVDDV
VREF = +4.096V, fSCLK = 4.8MHz100
VREF = +4.096V, SCLK idle0.01Input CurrentIREF
CS = DVDD, SCLK idle0.01
DIGITAL INPUTS (SCLK, CS)Input High VoltageVIHDVDD = +2.7V to +5.25V0.7 x
DVDDV
Input Low VoltageVILDVDD = +2.7V to +5.25V0.3 x
DVDDV
Input Leakage CurrentIINVIN = 0 to DVDD±0.1±1µA
Input HysteresisVHYST0.2V
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT)Output High VoltageVOHISOURCE = 0.5mA, DVDD = +2.7V to +5.25VDVDD -
0.25VV
ISINK = 10mA, DVDD = +4.75V to +5.25V0.7Output Low VoltageVOLISINK = 1.6mA, DVDD = +2.7V to +5.25V0.4V
Three-State Output Leakage
CurrentILCS = DVDD±0.1±10µA
Three-State Output CapacitanceCOUTCS = DVDD15pF
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)(AVDD
= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.1µs
SCLK to DOUT ValidtDOCDOUT = 50pF50ns
CS Fall to DOUT EnabletDVCDOUT = 50pF80ns
CS Rise to DOUT DisabletTRCDOUT = 50pF80ns
CS Pulse WidthtCSW50ns
CS Fall to SCLK Rise SetuptCSS100ns
CS Rise to SCLK Rise HoldtCSH0ns
SCLK High Pulse WidthtCH65ns
SCLK Low Pulse WidthtCL65ns
SCLK PeriodtCP208ns
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, CREF= 4.7µF,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIESAnalog SupplyAVDD4.755.25V
Digital SupplyDVDD2.75.25V
200ksps2.753.25
100ksps1.4
10ksps0.14Analog Supply CurrentIAVDDCS = DGND
1ksps0.014
200ksps0.61.0
100ksps0.3
10ksps0.03Digital Supply CurrentIDVDD
CS = DGND,
DOUT = all
zeros
1ksps0.003
Shutdown Supply CurrentIAVDD +
IDVDDCS = DVDD, SCLK = idle0.110µA
Power-Supply Rejection RatioPSRRAVDD = DVDD = +4.75V to +5.25V, full-scale
input (Note 5)68dB
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Note 1:AVDD= DVDD= +5V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset and reference errors nulled.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)(AVDD= +4.75V to +5.25V, DVDD
= +2.7V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF=
+4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.1µs
SCLK to DOUT ValidtDOCDOUT = 50pF100ns
CS Fall to DOUT EnabletDVCDOUT = 50pF100ns
CS Rise to DOUT DisabletTRCDOUT = 50pF80ns
CS Pulse WidthtCSW50ns
CS Fall to SCLK Rise SetuptCSS100ns
CS Rise to SCLK Rise HoldtCSH0ns
SCLK High Pulse WidthtCH65ns
SCLK Low Pulse WidthtCL65ns
SCLK PeriodtCP208ns
INL vs. OUTPUT CODEMAX1162 toc01
OUTPUT CODE
INL (LSB)
DNL vs. OUTPUT CODE
MAX1162 toc02
OUTPUT CODE
DNL (LSB)
MAX1162 FFT
MAX1162 toc03
FREQUENCY (kHz)
MAGNITUDE (dB)
Typical Operating Characteristics(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, CREF= 4.7µF, VREF= +4.096V, TA= +25°C, unless otherwise noted.)
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, CREF= 4.7µF, VREF= +4.096V, TA= +25°C, unless otherwise noted.)
MAX1162 toc10
ISHDN
(nA)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATUREMAX1162 toc11
SHUTDOWN SUPPLY CURRENT (nA)3510-15
SINAD vs. FREQUENCY
MAX1162 toc04
FREQUENCY (kHz)
SINAD (dB)1
SFDR vs. FREQUENCY
MAX1162 toc05
FREQUENCY (kHz)
SFDR (dB)1
THD vs. FREQUENCY
MAX1162 toc06
FREQUENCY (kHz)
THD (dB)10.1100
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1162 toc07
CONVERSION RATE (kHz)
SUPPLY CURRENT (mA)0.01
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1162 toc08
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. TEMPERATURE
MAX1162 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15-4085
3.5
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, CREF= 4.7µF, VREF= +4.096V, TA= +25°C, unless otherwise noted.)
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc12
SUPPLY VOLTAGE (V)
OFFSET ERROR (
OFFSET ERROR VS. TEMPERATURE
MAX1162 toc13
TEMPERATURE (°C)
OFFSET ERROR (
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc14
SUPPLY VOLTAGE (V)
GAIN ERROR (%)
GAIN ERROR vs. TEMPERATURE
MAX1162 toc15
TEMPERATURE (°C)
GAIN ERROR (%)
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Detailed DescriptionThe MAX1162 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 16-bit out-
put. Figure 4 shows the MAX1162 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
The MAX1162 has two power modes: normal and shut-
down. Driving CShigh places the MAX1162 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CSlow places the MAX1162 in normal operating
mode. Falling edges on CSinitiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface timing diagram.
Analog InputFigure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
Track-and-Hold (T/H)In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDACrepresents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
16-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDACto the input
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ= 13(RS+ RIN) x 35pF
where RIN= 800Ω, RS= the input signal’s source
impedance, and tACQis never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that can
drive the ADC’s input capacitance and settle quickly.
Pin Description
PINNAMEFUNCTIONREFExternal Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF
capacitor.
2AVDDAnalog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor.
3, 9AGNDAnalog Ground. Connect pins 3 and 9 together. Place star ground at pin 3.CS
Active-Low Chip-Select Input. Forcing CS high places the MAX1162 in shutdown with a typical
current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.SCLKSerial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
6DOUTSerial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS
is high.DGNDDigital Ground
8DVDDDigital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.AINAnalog Input
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Input BandwidthThe ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to AVDDor AGND, allow the input to swing from
AGND - 0.3V to AVDD+ 0.3V, without damaging the
device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
SCLK
DOUT
tCSStCHtCL
tDV
tCSH
tCSW
tTRtDO
tCP
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLKAIN
VREF
+5V
+5V
4.7μF
0.1μF
0.1μF
GND
MAX1162
DOUT
a) VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
1mA
DGNDDGND
CLOAD = 50pFCLOAD = 50pF
VDD
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
DOUT
a) VOH TO HIGH-Zb) VOL TO HIGH-Z
DOUT
1mA
1mA
DGNDDGND
CLOAD = 50pFCLOAD = 50pF
VDD
Figure 2. Load Circuits for DOUT Disable Time
