MAX115CAX+ ,2x4-Channel, Simultaneous-Sampling 12-Bit ADCsApplications Ordering InformationMultiphase Motor ControlPART TEMP. RANGE PIN-PACKAGEPower-Grid Syn ..
MAX115EAX ,2x4-Channel, Simultaneous-Sampling 12-Bit ADCsFeaturesThe MAX115/MAX116 are high-speed, multichannel, Four Simultaneous-Sampling T/H Amplifiers ..
MAX11600EKA+T ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsFeatures2♦ High-Speed I C-Compatible Serial InterfaceThe MAX11600–MAX11605 low-power, 8-bit, multic ..
MAX11603EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsApplicationsMedical InstrumentsBattery-Powered Test EquipmentPin Configurations and Typical Operati ..
MAX11605EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V = 4.5V to 5.5V (MAX1160 ..
MAX11609EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsFeatures2The MAX11606–MAX11611 low-power, 10-bit, multichan- ♦ High-Speed I C-Compatible Serial Int ..
MAX3485ESA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3485ESA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX115CAX+
2x4-Channel, Simultaneous-Sampling 12-Bit ADCs
________________General DescriptionThe MAX115/MAX116 are high-speed, multichannel,
12-bit data-acquisition systems (DAS) with simultane-
ous track/holds (T/Hs). These devices contain a 12-bit,
2µs, successive-approximation analog-to-digital con-
verter (ADC), a +2.5V reference, a buffered reference
input, and a bank of four simultaneous-sampling T/H
amplifiers that preserve the relative phase information
of the sampled inputs. The MAX115/MAX116 have two
multiplexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V. A fault condition on any channel will not dam-
age the IC. Available input ranges are ±5V (MAX115)
and ±2.5V (MAX116).
The parallel interface’s data access and bus release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microproces-
sors. The MAX115/MAX116 conversion results can be
accessed without resorting to wait-states.
________________________ApplicationsMultiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring
Digital Signal Processing
Vibration and Waveform Analysis
____________________________FeaturesFour Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (Eight Single-Ended
Inputs Total)2µs Conversion Time per Channel Throughput: 390ksps (1 Channel)
218ksps (2 Channels)
152ksps (3 Channels)
116ksps (4 Channels)Input Range: ±5V (MAX115)2.5V (MAX116)Fault-Protected Input Multiplexer (±17V)Internal +2.5V or External Reference OperationProgrammable On-Board SequencerHigh-Speed Parallel DSP InterfaceInternal 10MHz Clock
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs19-1928; Rev 0; 1/01
PART
MAX115CAX0°C to +70°C
TEMP. RANGEPIN-PACKAGE36 SSOP
EVALUATION KIT
AVAILABLE
Ordering InformationMAX115EAX-40°C to +85°C36 SSOP
MAX116CAX0°C to +70°C36 SSOP
MAX116EAX-40°C to +85°C36 SSOP
AGND
CH3B
CH3A
CH4B
CH4A
AVSS
INT
CONVST
CLK
D10
D11 (MSB)
AGND
REFOUT
REFIN
AVDD
CH1A
CH1B
CH2A
CH2B
SSOPTOP VIEW
MAX115
MAX116D3
D0/A2 (LSB)
D1/A3
DGND
DVDD
Pin ConfigurationTypical Operating CircuitD0/A2
D1/A3
D10
D11
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
MAX115
MAX116
CONVST
CONTROL INTERFACE
CLK
REFOUTDGND
AGND
REFINDVDD
4.7μF
16MHz
0.1μF
0.1μF
-5V
0.1μF
+5V
0.1μF
+5V
AVSS
AVDD
INTCSRDWR
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle. TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND...........................................................-0.3V to 6V
AVSSto AGND............................................................0.3V to -6V
DVDDto DGND...........................................................-0.3V to 6V
AGND to DGND.......................................................-0.3V to 0.3V
CH_ _ to AGND....................................................................±17V
REFIN, REFOUT to AGND..........................................-0.3V to 6V
Digital Inputs/Outputs to DGND..............-0.3V to (DVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
36-Pin SSOP (derate 11.8mW/°C above +70°C)..........941mW
Operating Temperature Ranges
MAX115_CAX/MAX116_CAX...............................0°C to +70°C
MAX115_EAX/MAX116_EAX............................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s)....................................300°C
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERAll channels12NResolutionBits
0.6±1INLIntegral Nonlinearity (Note 2)LSB
MAX115±5±15
Bipolar Zero Error±30
Bipolar Zero-Error MatchBetween all channelsmV25
MAX115180µV/°CZero-Code Tempco±15Gain Error±25MAX115mVGain Error Match
120MAX115Gain Error TempcoµV/°C
SNRSignal-to-Noise RatiodB
-80THD(Notes 4, 5)Total Harmonic DistortiondBSFDR(Note 4)Spurious-Free Dynamic Range dB(Note 6)Channel-to-Channel Isolation dB
LSB0.6±1DNLDifferential Nonlinearity(Note 4)
MAX116±5±10
±18= +25°C = TMINto TMAX= +25°C= TMINto TMAX
MAX11690±10
±18MAX116= +25°C= TMINto TMAX= +25°C= TMINto TMAXMAX116
ACCURACY (Note 1)
DYNAMIC PERFORMANCE (fCLK= 16MHz, fIN= 10.06kHz) (Notes 1, 3)
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle. TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERMAX115V±5VINInput Voltage Range
MAX115 (-5V to +5V range)µA±625IINInput Current16CINInput Capacitance600tACQAcquisition Time
MHz10Small-Signal Bandwidth
MHz1.3Full-Power Bandwidth
mV/ms2Drop Rate10Aperture Delay30Aperture Jitter500Aperture-Delay Matching= +25°CV2.4622.52.532VREFOUTOutput Voltage
0 < IREF< 1mAmV/mA0.5External Load Regulation
(Note 8)ppm/°C30REFOUT Tempco0.1External Capacitive Bypass
at REFIN2.402.502.60Input Voltage Range4.722External Capacitive Bypass
at REFOUT±50Input Current10Input Resistance (Note 9)10Input Capacitance
MHz16External Clock Frequency2.4VIHInput High Voltage0.8VILInput Low Voltage
CONVST, RD, WR, CS, CLK±115CINInput Capacitance
A0–A3µA±10IINInput Current
MAX116±2.5
MAX116 (-2.5V to +2.5V range)±15
MHz5.61014.8Internal Clock Frequency
ANALOG INPUT
TRACK/HOLD
REFERENCE OUTPUT (Note 7)
REFERENCE INPUT
EXTERNAL CLOCK
DIGITAL INPUTS (CONVST, RD,WR, CS, CLK, A0–A3) (Note 1)
INTERNAL CLOCK
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERIOUT= 1mAV4VOHOutput High Voltage
IOUT= -1.6mAV0.4VOLOutput Low Voltage
D0–D11µA±10Three-State Leakage Current10Three-State Output
Capacitance4.7555.25AVDDPositive Supply Voltage-5.25-5-4.75AVSSNegative Supply Voltage4.7555.25DVDDDigital Supply Voltage1725IAVDDPositive Supply Current-20-15IAVSSNegative Supply Current36Digital Supply Current1Shutdown Positive Current-1Shutdown Negative Current13Shutdown Digital Current
(Note 10)LSB±1PSRR+Positive Supply Rejection
(Note 10)LSB±1PSRR-Negative Supply Rejection
(Note 11)mW175Power Dissipation
DIGITAL OUTPUTS (D0–D11, INT)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle. TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS(See Figure 4, AVDD= +5V, AVSS= -5V, DVDD= +5V, AGND = DGND = 0, TA= TMINto TMAX, Typical values are at TA= +25°C,
unless otherwise noted.)
Guaranteed by designns0tCWSCSto WRSetup Time
Guaranteed by designns0tCWHCSto WRHold Time30tWRWRLow Pulse Width30
CONDITIONStASAddress Setup Time0tAHAddress Hold Time
25pF loadns55tIDRDto INTDelay45tRDDelay Time Between Reads
Guaranteed by designns0tCRSCSto RDSetup Time
Guaranteed by designns0tCRHCSto RDHold Time30tRDRDLow Pulse Width
25pF load (Note 12)ns40tDAData-Access Time
25pF load (Note 13)ns545tDHBus-Relinquish Time30tCWCONVSTPulse Width
UNITSMINTYPMAXSYMBOLPARAMETER
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
TIMING CHARACTERISTICS (continued)(See Figure 4, AVDD= +5V, AVSS= -5V, DVDD= +5V, AGND = DGND = 0, TA= TMINto TMAX, Typical values are at TA= +25°C,
unless otherwise noted.)
Mode 1, Channel 1
Mode 2, Channel 24
Mode 3, Channel 36
Mode 4, Channel 48
tCONV
Exiting shutdownms20Startup Time
Note 1:AVDD= +5V, AVSS= -5V, DVDD= +5V, VREFIN= 2.500V (external), VIN= ±5V (MAX115) or ±2.5V (MAX116).
Note 2:Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:CLK synchronized with CONVST.
Note 4:fIN= 10.06kHz, VIN= ±5V (MAX115) or ±2.5V (MAX116).
Note 5:First five harmonics.
Note 6:All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digi-
tized.
Note 7:AVDD= DVDD= +5V, AVSS= -5V, VIN= 0V (all channels).
Note 8:Temperature drift is defined as the change in output voltage from +25°C to TMINor TMAX. It is calculated as
TC = [ΔREFOUT/REFOUT] / ΔT.
Note 9:See Figure 2.
Note 10:Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN= +2.5V (internal).
Note 11:Tested with all inputs connected to AGND. VREFIN= +2.5V (internal).
Note 12:The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit
of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 13:The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the
120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capac-
itance.
Conversion Time
Mode 1, Channel 1
ksps
Conversion RateMode 2, Channel 2218
Mode 3, Channel 3152
Mode 4, Channel 4116
_______________Detailed DescriptionThe MAX115/MAX116 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
12-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX115/MAX116 internal micro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (Figure 2). The
MAX115/MAX116 can operate with either an external or
internal clock. For internal operation, connect CLK to
DVDD.
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
______________________________________________________________Pin DescriptionFigure 1. Load Circuit for Access Time and Bus Relinquish Time
TO OUTPUT
PIN
120pF
1.0mA
1.6mA
1.6V
Channel 3 Multiplexed Inputs (single-ended)CH3A, CH3B34, 35
Channel 4 Multiplexed Inputs (single-ended)CH4A, CH4B32, 33
Analog Supply VoltageAVSS31
Interrupt output. Falling edge indicates the end of a conversion sequence.INT30
Conversion-Start input. Rising edge initiates sampling and conversion sequence.CONVST29
Read Input (active-low)RD28
Write Input (active-low)WR27
Digital GroundDGND18
Data BitsD3, D219, 20
Bidirectional Data Bits/Address BitsD1/A3, D0/A221, 22
Clock Input (duty cycle must be 30% to 70%). Connect CLK to DVDD to activate internal clock.CLK25
Chip-Select Input (active-low)CS26
Reference-Buffer output. Bypass with a 4.7µF capacitor to AGND.REFOUT7
Analog ground. Both pins must be connected to ground.AGND8, 36
Data Bits. D11 = MSB.D11–D49–16
Digital Supply VoltageDVDD17
External reference input/internal reference output. Bypass with a 0.1µF capacitor to AGND.REFIN6
Analog Supply VoltageAVDD5
PINChannel 1 Multiplexed Inputs (single-ended)CH1B, CH1A3, 4
Channel 2 Multiplexed Inputs (single-ended)CH2B, CH2A1, 2
FUNCTIONNAMEAddress BitsA1, A023, 24
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCsMUX
2.50V
BANDGAP REFERENCE
REFIN
10kΩ
AGNDREFOUT
MUX
T/H
T/H
T/H
T/HA
MUXA
MUXA
MUX
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
12-BIT
DAC
CONTROL LOGIC
BUS INTERFACE
CLKCONVSTINTCSRDWRDVDDDGND
SAR
4x12
RAM
VREF
THREE-STATE
OUTPUT
DRIVERS
AVDD
AGND
AVSS
D0/A2
D1/A3
D11 (MSB)
MAX115
MAX116
VREF
COMP
10MHz
CLOCK
Figure 2. Functional Diagram
