MAX1139EEE ,2.7V to 3.6V and 4.5V to 5.5V / Low-Power / 4-/12-Channel / 2-Wire Serial 10-Bit ADCsApplicationsOrdering InformationMedical InstrumentsBattery-Powered Test EquipmentTEMP PIN- INLPARTR ..
MAX1139EEE-T ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCsFeatures2The MAX1136–MAX1139 low-power, 10-bit, multichannel♦ High-Speed I C-Compatible Serial Inte ..
MAX113CAG ,+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1UA Power-Down
MAX113EAG ,+3V, 400ksps, 4/8-Channel, 8-Bit ADCs with 1UA Power-Down
MAX1142ACAP ,14-Bit ADC, 200ksps, +5V Single-Supply with Referenceapplications such as indus-trial process control, instrumentation, and medical♦ 2.5μA Shutdown Mode
MAX1142ACAP+ ,14-Bit ADC, 200ksps, +5V Single-Supply with Referenceapplications. The MAX1142 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX3483EEPA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EEPA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1139EEE
2.7V to 3.6V and 4.5V to 5.5V / Low-Power / 4-/12-Channel / 2-Wire Serial 10-Bit ADCs
General DescriptionThe MAX1136–MAX1139 low-power, 10-bit, multichan-
nel analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an2C™-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V (MAX1137/
MAX1139) or 4.5V to 5.5V (MAX1136/MAX1138) and
require only 670µA at the maximum sampling rate of
94.4ksps. Supply current falls below 230µA for sam-
pling rates under 46ksps. AutoShutdown™ powers
down the devices between conversions, reducing sup-
ply current to less than 1µA at low throughput rates.
The MAX1136/MAX1137 have four analog input chan-
nels each, while the MAX1138/MAX1139 have 12 ana-
log input channels each. The fully differential analog
inputs are software configurable for unipolar or bipolar,
and single ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1137/
MAX1139 feature a 2.048V internal reference and the
MAX1136/MAX1138 feature a 4.096V internal reference.
The MAX1136/MAX1137 are available in an 8-pin µMAX
package. The MAX1138/MAX1139 are available in a
16-pin QSOP package. The MAX1136–MAX1139 are
guaranteed over the extended temperature range
(-40°C to +85°C). For pin-compatible 12-bit parts, refer
to the MAX1136–MAX1139 data sheet. For pin-compati-
ble 8-bit parts, refer to the MAX1036–MAX1039 data
sheet.
ApplicationsHand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
FeaturesHigh-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed ModeSingle-Supply
2.7V to 3.6V (MAX1137/MAX1139)
4.5V to 5.5V (MAX1136/MAX1138)Internal Reference
2.048V (MAX1137/MAX1139)
4.096V (MAX1136/MAX1138)External Reference: 1V to VDDInternal Clock4-Channel Single-Ended or 2-Channel Fully
Differential (MAX1136/MAX1137)12-Channel Single-Ended or 6-Channel Fully
Differential (MAX1138/MAX1139)Internal FIFO with Channel-Scan ModeLow Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down ModeSoftware-Configurable Unipolar/BipolarSmall Packages
8-Pin µMAX (MAX1136/MAX1137)
16-Pin QSOP (MAX1138/MAX1139)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Ordering Information19-2334; Rev 1; 4/02
Pin Configurations appear at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
Selector Guide appears at end of data sheet.AutoShutdown is a trademark of Maxim Integrated Products, Inc.2C is a trademark of Philips Corp.
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), CREF= 0.1µF, fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND............-0.3V to the lower of (VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C).............362mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), CREF= 0.1µF, fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), CREF= 0.1µF, fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C. See Tables 1–5 for programming notation.)
TIMING CHARACTERISTICS (Figure 1)(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), CREF= 0.1µF, fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C. See Tables 1–5 for programming notation.)
Note 1:For DC accuracy, the MAX1136/MAX1138 are tested at VDD= 5V and the MAX1137/MAX1139 are tested at VDD= 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3:Offset nulled.
Note 4:Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5:A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6:The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7:When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.01µF capacitor.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9:Measured as for the MAX1137/MAX1139
and for the MAX1136/MAX1138
Note 10:A master device must provide a data hold time for SDA (referred to VILof SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11:CB= total capacitance of one bus line in pF.
Note 12:fSCLmust meet the minimum clock low time plus the rise/fall times.
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), CREF= 0.1µF, fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at = +25°C. See Tables 1–5 for programming notation.)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Typical Operating Characteristics(VDD= 3.3V (MAX1137/MAX1139), VDD= 5V (MAX1136/MAX1138), fSCL= 1.7MHz, external clock, fSAMPLE= 94.4ksps, single-
ended, unipolar, TA= +25°C, unless otherwise noted.)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Typical Operating Characteristics (continued)(VDD= 3.3V (MAX1137/MAX1139), VDD= 5V (MAX1136/MAX1138), fSCL= 1.7MHz, external clock, fSAMPLE= 94.4ksps, single-
ended, unipolar, TA= +25°C, unless otherwise noted.)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCsFigure 1. 2-Wire Serial Interface Timing
Detailed DescriptionThe MAX1136–MAX1139 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX1136/MAX1137 are
4-channel ADCs, and the MAX1138/MAX1139 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX1138/MAX1139.
Power SupplyThe MAX1136–MAX1139 operates from a single supply
and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX1137/MAX1139 feature a 2.048V
internal reference and the MAX1136/MAX1138 feature
a 4.096V internal reference. All devices can be config-
ured for use with an external reference from 1V to VDD.
Analog Input and Track/HoldThe MAX1136–MAX1139 analog-input architecture con-
tains an analog-input multiplexer (mux), a fully differen-
tial track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode the analog-input multiplexer con-
nects CT/Hbetween the analog input selected by
CS[3:0] (see the Configuration Setup Bytes section)
and GND (Table 3). In differential mode, the analog-
input multiplexer connects CT/Hto the “+” and “-” ana-
log inputs selected by CS[3:0] (Table 4).
During the acquisition interval the T/H switches are in
the track position and CT/Hcharges to the analog input
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCsFigure 2. MAX1138/MAX1139 Functional Diagram
Figure 3. Load Circuit
MAX1136–MAX1139signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕(VIN+- VIN-) from
CT/Hto the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion, or series of conversions, are then
internally clocked and the MAX1136–MAX1139 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ≥9 ✕(RSOURCE+ RIN) ✕CIN
where RSOURCEis the analog-input source impedance,
RIN= 2.5kΩ, and CIN= 22pF. tACQis 1.5/fSCLfor internal
clock mode and tACQ= 2/fSCLfor external clock mode.
Analog Input BandwidthThe MAX1136–MAX1139 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and ProtectionInternal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCsFigure 4. Equivalent Input Circuit
swing from (GND - 0.3V) to (VDD+ 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
Single-Ended/Differential InputThe SGL/DIFof the configuration byte configures the
MAX1136–MAX1139 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF= 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF= 0) the
digital conversion results are the difference between the
“+” and the “-” analog inputs selected by CS[3:0] (Table 4).
Unipolar/BipolarWhen operating in differential mode, the BIP/UNIbit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode will cause the digital output
code to be zero. Selecting bipolar mode sets the differ-
ential input range to ±VREF/2. The digital output code is
binary in unipolar mode and two’s complement in bipo-
lar mode, see the Transfer Functions section.
In single-ended mode the MAX1136–MAX1139 will
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital InterfaceThe MAX1136–MAX1139 feature a 2-wire interface con-
sisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1136–MAX1139 and the master at
rates up to 1.7MHz. The MAX1136–MAX1139 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ωor greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional.
They protect the input architecture of the MAX1136–
MAX1139 from high voltage spikes on the bus lines, min-
imize crosstalk, and undershoot of the bus signals.
Bit TransferOne data bit is transferred during each SCL clock
cycle. A minimum of eighteen clock cycles are required
to transfer the data in or out of the MAX1136–MAX1139.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP ConditionsThe master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see HS-mode).
Acknowledge BitsData transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1136–MAX1139 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiv-
er allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer the bus master should reattempt
communication at a later time.
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCsFigure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
