MAX1124EGK+D ,1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband ApplicationsELECTRICAL CHARACTERISTICS(AV = OV = 1.8V, V = V = 0, f = 250MHz, differential sine-wave clock inpu ..
MAX1132BCAP ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceMAX1132/MAX113319-2083; Rev 0; 8/0116-Bit ADC, 200ksps, 5V Single-Supplywith Reference
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BEAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX3480BCPI+ ,Complete, Isolated, 3.3V RS-485/RS-422 Data Interface
MAX3480BCPI+ ,Complete, Isolated, 3.3V RS-485/RS-422 Data Interface
MAX3480BCPI+ ,Complete, Isolated, 3.3V RS-485/RS-422 Data Interface
MAX3483CPA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483CPA+ ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3483CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1124EGK+D
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
General DescriptionThe MAX1124 is a monolithic 10-bit, 250Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1124 achieves a spurious-free dynamic range
(SFDR) of 71dBc. Its excellent signal-to-noise ratio
(SNR) of 57.1dB at 10MHz remains flat (within 1dB) for
input tones up to 500MHz. This makes the MAX1124
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
The MAX1124 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1124 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the industrial
(-40°C to +85°C) temperature range.
For pin-compatible, lower speed versions of the
MAX1124, refer to the MAX1122 (170Msps) and the
MAX1123 (210Msps) data sheets. For a pin-compatible
8-bit version of the MAX1124, refer to the MAX1121
data sheet.
ApplicationsWireless and Wired Broadband Communication
Cable-Head End Systems
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Features250Msps Conversion RateSNR = 56.8dB/55.5dB at fIN= 100MHz/500MHzSFDR = 71dBc/63.8dBc at fIN= 100MHz/500MHzNPR = 54.8dB at fNOTCH= 28.8MHzSingle 1.8V Supply477mW Power Dissipation at 250MspsOn-Chip Track-and-Hold and Internal ReferenceOn-Chip Selectable Divide-by-2 Clock InputLVDS Digital Outputs with Data Clock OutputEvaluation Kit Available (Order MAX1124EVKIT)
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications596061625455565763
AVCC
AGND
TOP VIEW
OGNDOV
ORPORND9PD9ND8PD8N53
D7PD7N
AGNDAGND
CLKNCLKPAV
AGND
OGND
N.C.
N.C.N.C.N.C.
D4P
D4N
OGND
OVCC
DCLKP
DCLKN
OVCC
D3P
D3N
D2PD2N
D1P
D1N
AGND
INN
INP
AGND
AVCC
AGND
AGND
AVCC
AVCC
AVCC
AGND
REFADJ
REFIO
AGNDD5N
AVCC
AGND6667
AGNDAGNDAV
T/B2221201927262524182928323130
D0N
D0P33D6N
D5PD6P
CLKDIV17
MAX1124
Pin Configuration
Ordering Information19-3029; Rev 2; 8/08
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX1124EGK-40°C to +85°C68 QFN-EP*
*EP = Exposed pad.
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND......................................................-0.3V to +2.1V
OVCCto OGND.....................................................-0.3V to +2.1V
AVCCto OVCC.......................................................-0.3V to +2.1V
AGND to OGND....................................................-0.3V to +0.3V
Analog Inputs to AGND...........................-0.3V to (AVCC+ 0.3V)
Digital Inputs to AGND.............................-0.3V to (AVCC+ 0.3V)
REF, REFADJ to AGND............................-0.3V to (AVCC+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OVCC+ 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C).........3333mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Maximum Current into Any Pin............................................50mA
ELECTRICAL CHARACTERISTICS(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL= 100Ω±1%, CL= 5pF, TA= TMINto TMAX, unless otherwise noted. ≥+25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution10Bits
Integral NonlinearityINL(Note 1)-2.4±0.8+2.4LSB
Differential NonlinearityDNLNo missing codes (Note 1)-1.0±0.5+1.5LSB
TA ≥ +25°C-25+25Transfer Curve OffsetVOS(Note 1)(Note 2)-37+37LSB
Offset Temperature Drift±20µV/°C
ANALOG INPUTS (INP, INN)Full-Scale Input Voltage RangeVFS(Note 1)110012501375mVP-P
Full-Scale Range Temperature
Drift130ppm/°C
Common-Mode Input RangeVCM1.38
±0.18V
Input CapacitanceCIN3pF
Differential Input ResistanceRIN3.004.36.25kΩ
Full-Power Analog BandwidthFPBWFigure 8600MHz
REFERENCE (REFIO, REFADJ)Reference Output VoltageVREFIO1.181.241.30V
Reference Temperature Drift90ppm/°C
REFADJ Input High VoltageVREFADJUsed to disable the internal referenceAVCC -
0.3V
SAMPLING CHARACTERISTICSMaximum Sampling RatefSAMPLE250MHz
Minimum Sampling RatefSAMPLE20MHz
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL= 100Ω±1%, CL= 5pF, TA= TMINto TMAX, unless otherwise noted. ≥+25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSClock Duty CycleSet by clock management circuit40 to 60%
Aperture DelaytAD350ps
Aperture JittertAJ0.2psRMS
CLOCK INPUTS (CLKP, CLKN)Differential Clock Input Amplitude(Note 2)200500mVP-P
Clock Input Common-Mode
Voltage Range
±0.25V
Clock Differential Input
ResistanceRCLK11 ±
25%kΩ
Clock Differential Input
CapacitanceCCLK5pF
DYNAMIC CHARACTERISTICS (at -0.5dBFS)fIN = 10MHz, TA ≥ +25°C54.357.1
fIN = 100MHz, TA ≥ +25°C5456.8
fIN = 180MHz56.3Signal-to-Noise RatioSNR
fIN = 500MHz55.5
fIN = 10MHz, TA ≥ +25°C5457
fIN = 100MHz, TA ≥ +25°C53.556.5
fIN = 180MHz56
Signal-to-Noise
and DistortionSINAD
fIN = 500MHz55
fIN = 10MHz, TA ≥ +25°C62.675
fIN = 100MHz, TA ≥ +25°C6271
fIN = 180MHz68.3
Spurious-Free
Dynamic RangeSFDR
fIN = 500MHz63.8
dBc
fIN = 10MHz-75
fIN = 100MHz-71
fIN = 180MHz-68.3
Worst Harmonics
(HD2 or HD3)
fIN = 500MHz-63.8
dBc
IMD100fIN1 = 99MHz at -7dBFS,
fIN2 = 101MHz at -7dBFS-65Two-Tone Intermodulation
DistortionIMD500fIN1 = 498.5MHz at -7dBFS,
fIN2 = 502.5MHz at -7dBFS-56
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D9P/N, ORP/N)Differential Output Voltage|VOD|250450mV
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL= 100Ω±1%, CL= 5pF, TA= TMINto TMAX, unless otherwise noted. ≥+25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Offset VoltageOVOS1.1251.310V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)Digital Input Voltage LowVIL0.2 x
AVCCV
Digital Input Voltage HighVIH0.8 x
AVCCV
TIMING CHARACTERISTICSCLK to Data Propagation DelaytPDLFigure 41.5ns
CLK to DCLK Propagation DelaytCPDLFigure 42.85ns
Data Valid to DCLK Rising EdgetCPDL -
tPDLFigure 4 (Note 2)0.921.351.86ns
LVDS Output Rise-TimetRISE20% to 80%, CL = 5pF460ps
LVDS Output Fall-TimetFALL20% to 80%, CL = 5pF460ps
Output Data Pipeline DelaytLATENCY8Clock
cycles
POWER REQUIREMENTSAnalog Supply Voltage RangeAVCC1.71.81.9V
Digital Supply Voltage RangeOVCC1.71.81.9V
Analog Supply CurrentIAVCCfIN = 100MHz220290mA
Digital Supply CurrentIOVCCfIN = 100MHz4575mA
Total Power DissipationPDISSfIN = 100MHz477657mW
Offset1.6mV/VPower-Supply Rejection Ratio
(Note 3)PSRRGain1.9%FS/V
Note 1:Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2:Parameter guaranteed by design and characterization; TA= TMINto TMAX.
Note 3:PSRR is measured with both analog and digital supplies connected to the same potential.
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband ApplicationsFFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1124 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fSAMPLE = 250.0057MHz
fIN = 11.5054MHz
AIN = -0.4795dBFS
SNR = 56.5dB
SFDR = 73.5dBc
HD2 = -82.4dBc
HD3 = -73.5dBc
HD2HD3
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1124 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fSAMPLE = 250.0057MHz
fIN = 60.0294MHz
AIN = -0.4885dBFS
SNR = 56.4dB
SFDR = 74.6dBc
HD2 = -82.1dBc
HD3 = -75.6dBc
HD2HD3
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1124 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fSAMPLE = 250.0057MHz
fIN = 183.5064MHz
AIN = -0.5335dBFS
SNR = 56dB
SFDR = 68.7dBc
HD2 = -78.1dBc
HD3 = -68.7dBc
HD2HD3
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1124 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
HD3
HD2
fSAMPLE = 250.0057MHz
fIN = 500.516MHz
AIN = -0.5155dBFS
SNR = 55.4dB
SFDR = 64.8dBc
HD2 = -69.9dBc
HD3 = -64.8dBc
FUNDAMENTAL
SNR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)MAX1124 toc05
fIN (MHz)
SNR (dB)
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc06
fIN (MHz)
SFDR (dBc)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc07
HD2/HD3 (dBc)
HD2
HD3
SNR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
MAX1124 toc08
SNR (dB)
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
MAX1124 toc09
SFDR (dBc)
Typical Operating Characteristics(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband ApplicationsHD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
MAX1124 toc10
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
HD3
HD2
SNR vs. fSAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)MAX1124 toc11
fSAMPLE (MHz)
SNR (dB)25017013090210
SFDR vs. fSAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)MAX1124 toc12
fSAMPLE (MHz)
SFDR (dBc)
HD2/HD3 vs. fSAMPLE
(fIN = 60.03294MHz, AIN = -0.5dBFS)
MAX1124 toc13
fSAMPLE (MHz)
HD2/HD3 (dBc)
HD2
HD3
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
MAX1124 toc14
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fSAMPLE = 250.0057MHz
fIN1 = 99.0317MHz
fIN2 = 101.0459MHz
AIN1 = AIN2 = -7dBFS
IMD = -65dBc
2fIN1 - fIN2
2fIN2 -
fIN1
fIN1fIN2
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1124 toc15
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1124 toc16
DNL (LSB)
GAIN BANDWIDTH PLOT
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc17
GAIN (dB)
SNR vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)MAX1124 toc18
SNR (dB)3510-15
Typical Operating Characteristics (continued)
(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
SINAD vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)MAX1124 toc19
TEMPERATURE (°C)
SINAD (dB)3510-15
SFDR vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc20
TEMPERATURE (°C)
SFDR (dBc)3510-15
POWER DISSIPATION vs. fSAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124 toc21
fSAMPLE (MHz)
DISS
(mW)
FS VOLTAGE vs. FS ADJUST RESISTOR
MAX1124 toc22
FS ADJUST RESISTOR (Ω)
FS
(V)
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
FIGURE 6
SNR vs. VOLTAGE SUPPLY
(fIN = 60.0294MHz, AIN = -0.5dBFS)MAX1124 toc23
VOLTAGE SUPPLY (V)
SNR
(dB)
AVCC = OVCC
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(fSAMPLE = 250.0057MHz)MAX1124 toc24
SUPPLY VOLTAGE (V)
REFIO
(V)
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
0.0E+00
1.0E+04
3.0E+04
2.0E+04
4.0E+04
5.0E+04
6.0E+04
7.0E+04
8.0E+04
NOISE HISTOGRAM
(DC INPUT, 128k-POINT DATA RECORD)
MAX1124 toc25
DIGITAL OUTPUT NOISE
CODE COUNTS
fSAMPLE = 250MHz
PROPAGATION DELAY TIMES
vs. TEMPERATURE
MAX1124 toc26
PROPAGATION DELAY (ns)3510-15
tCPDL
tPDL
Typical Operating Characteristics (continued)(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Pin Description
PINNAMEFUNCTION1, 6, 11–14, 20,
25, 62, 63, 65AVCCAnalog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
AGNDAnalog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.REFIO
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
an external reference source to be connected to the MAX1124. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.REFADJ
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
REFIO (increases FS range). If REFADJ is connected to AVCC through a 1kΩ resistor, the
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.INPPositive Analog Input TerminalINNNegative Analog Input TerminalCLKDIV
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.CLKPTrue Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.CLKNComplementary Clock Input. This input requires an LVDS-compatible input level to maintain48543642606672
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.8148MHz,
fSAMPLE = 249.856MHz, AIN = -0.5dBFS)MAX1124 toc27
CLOCK DUTY CYCLE (%)
SINAD (dB)
NOISE POWER RATIO PLOT
MAX1124 toc28
ANALOG INPUT FREQUENCY (MHz)
POWER SPECTRAL DENSITY (dB)fSAMPLE = 250MHz
fNOTCH = 28.8MHz
NPR = 54.8dB
Typical Operating Characteristics (continued)(AVCC= OVCC= 1.8V, VAGND= VOGND= 0, fSAMPLE= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL= 100Ω, TA= +25°C.)
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Pin Description (continued)
PINNAMEFUNCTION26, 45, 61OGNDDigital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60OVCCDigital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
29–32N.C.No Connection. Do not connect to these pins.D0NComplementary Output Bit 0 (LSB)D0PTrue Output Bit 0 (LSB)D1NComplementary Output Bit 1D1PTrue Output Bit 1D2NComplementary Output Bit 2D2PTrue Output Bit 2D3NComplementary Output Bit 3D3PTrue Output Bit 3DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKN and DCLKN.DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP
and DCLKP.D4NComplementary Output Bit 4D4PTrue Output Bit 4D5NComplementary Output Bit 5D5PTrue Output Bit 5D6NComplementary Output Bit 6D6PTrue Output Bit 6D7NComplementary Output Bit 7D7PTrue Output Bit 7D8NComplementary Output Bit 8D8PTrue Output Bit 8D9NComplementary Output Bit 9 (MSB)D9PTrue Output Bit 9 (MSB)ORNComplementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.ORPTrue Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1124. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
T/B = 1: Binary output format
