MAX111BCWE ,Low-Cost / 2-Channel / 14-Bit Serial ADCsapplications. A fast550µA (MAX110)serial interface simplifies signal routing and opto-isola-640µA ( ..
MAX111BCWE+ ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsELECTRICAL CHARACTERISTICS—MAX110(V = 5V ±5%, V = -5V ±5%, f = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK ..
MAX111BEWE+ ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsFeatures♦ Single +5V Supply (MAX111)The MAX110/MAX111 analog-to-digital converters(ADCs) use an int ..
MAX111BEWE+ ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsGeneral Description ________
MAX11209EVKIT+ ,Evaluation Kits for the MAX11200, MAX11206, MAX11209, MAX11210, and MAX11213features of the MAX11200 family of data converters. The EV kits are S Real-Time Data Acquisition t ..
MAX1124EGK+D ,1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband ApplicationsELECTRICAL CHARACTERISTICS(AV = OV = 1.8V, V = V = 0, f = 250MHz, differential sine-wave clock inpu ..
MAX3471CUA+T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471EUA+ ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA+T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA-T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3480BCPI+ ,Complete, Isolated, 3.3V RS-485/RS-422 Data Interface
MAX111ACAP-MAX111ACPE-MAX111AEPE-MAX111BCPE-MAX111BCWE
Low-Cost / 2-Channel / 14-Bit Serial ADCs
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
General DescriptionThe MAX110/MAX111 analog-to-digital converters
(ADCs) use an internal auto-calibration technique to
achieve 14-bit resolution plus overrange, with no exter-
nal components. Operating supply current is only
550µA (MAX110) and reduces to 4µA in power-down
mode, making these ADCs ideal for high-resolution bat-
tery-powered or remote-sensing applications. A fast
serial interface simplifies signal routing and opto-isola-
tion, saves microcontroller pins, and offers compatibility
with SPI™, QSPI™, and MICROWIRE™. The MAX110
operates with ±5V supplies, and converts differential
analog signals in the -3V to +3V range. The MAX111
operates with a single +5V supply and converts differ-
ential analog signals in the ±1.5V range, or single-
ended signals in the 0V to +1.5V range.
Internal calibration allows for both offset and gain-error
correction under microprocessor (µP) control. Both
devices are available in space-saving 16-pin DIP and
SO packages, as well as an even smaller 20-pin SSOP
package.
________________________ApplicationsProcess Control
Weigh Scales
Panel Meters
Data-Acquisition Systems
Temperature Measurement
____________________________FeaturesSingle +5V Supply (MAX111)Two Differential Input Channels14-Bit Resolution Plus Sign and Overrange0.03% Linearity (MAX110)
0.05% Linearity (MAX111)Low Power Consumption:
550µA (MAX110)
640µA (MAX111)
4µA Shutdown CurrentUp to 50 Conversions/sec50Hz/60Hz RejectionAuto-Calibration ModeNo External Components Required16-Pin DIP/SO, 20-Pin SSOP
Ordering Information19-0283; Rev 5; 11/98
Typical Operating CircuitPin Configurations
Ordering Information continued at end of data sheet.Contact factory for dice specifications.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ABSOLUTE MAXIMUM RATINGSVDDto GND...........................................................................+6V
VSSto GND (MAX110)..............................................+0.3V to -6V
AGND to DGND.....................................................-0.3V to +0.3V
VIN1+, VIN1-......................................(VDD+ 0.3V) to (VSS- 0.3V)
VIN2+, VIN2-......................................(VDD+ 0.3V) to (VSS- 0.3V)
VREF+, VREF-....................................(VDD+ 0.3V) to (VSS- 0.3V)
Digital Inputs and Outputs.........................(VDD+ 0.3V) to -0.3V
Continuous Power Dissipation
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C).....842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
20-Pin SSOP (derate 8.00mW/°C above +70°C)...........640mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW
Operating Temperature Ranges
MAX11_ _C_ _......................................................0°C to +70°C
MAX11_ _E_ _...................................................-40°C to +85°C
MAX11_BMJE.................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX110(VDD= 5V ±5%, VSS= -5V ±5%, fXCLK= 1MHz, ‚2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= -1.5V, = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX110 (continued)(VDD= 5V ±5%, VSS= -5V ±5%, fXCLK= 1MHz, ‚2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= -1.5V, = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX111(VDD= 5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= 0V, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX111 (continued)(VDD= 5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= 0V, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Note 10:Timing specifications are guaranteed by design. All input control signals are specified with tr= tf= 5ns
(10% to 90% of +5V) and timed from a +1.6V voltage level.
Note 1:These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at VDD= 5V and VSS= -5V (MAX110).
Note 2:32,768 LSBs cover an input voltage range of ±VREF(15 bits). An additional bit (OFL) is set for VIN> VREF.
Note 3:Guaranteed by design. Not subject to production testing.
Note 4:DNL is less than ±2 counts (LSBs) out of 215counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5:See 3-Step Calibrationsection in text.
Note 6:VREF= (VREF+- VREF-), VIN= (VIN1+- VIN1-) or (VIN2+- VIN2-). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7:Conversion time is set by control bits CONV1–CONV4.
Note 8:Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristicssection for the effect of other clock frequencies. Also read the Clock Frequencysection.
Note 9:This current depends strongly on CXCLK(see Applications Informationsection).
TIMING CHARACTERISTICS(see Figure 6)
(VDD= 5V, VSS= -5V (MAX110), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
__________________________________________Typical Operating Characteristics(MAX110, VDD= 5V, VSS= -5V, VREF+= 1.5V, VREF-= -1.5V, differential input (VIN+= -VIN-), fXCLK= 1MHz, ÷2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
____________________________Typical Operating Characteristics (continued)(MAX111, VDD= 5V, VREF+= 1.5V, VREF-= 0V, differential input (VIN+= -VIN-), fXCLK= 1MHz, ÷2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
_______________Detailed DescriptionThe MAX110/MAX111 ADC converts low-frequency
analog signals to a 16-bit serial digital output (14 data
bits, a sign bit, and an overrange bit) using a first-order
sigma-delta loop (Figure 1). The differential input volt-
age is internally connected to a precision voltage-to-
current converter. The resulting current is integrated
and applied to a comparator. The comparator output
then drives an up/down counter and a 1-bit DAC. When
the DAC output is fed back to the integrator input, the
sigma-delta loop is completed.
During a conversion, the comparator output is a VREF-to VREF+square wave; its duty cycle is proportional to
the magnitude of the differential input voltage applied
to theADC. The up/down counter clocks data in from
the comparator at the oversampling clock rate and
averages the pulse-width-modulated (PWM) square
wave to produce the conversion result. A 16-bit static
shift register stores the result at the end of the conver-
sion. Figure 2 shows the ADC waveforms for a differen-
tial analog input equal to 1/2 (VREF+- VREF-). The
resulting comparator and 1-bit DAC outputs are high
for seven cycles and low for three cycles of the over-
sampling clock.
Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
is attenuated. The more clock cycles allowed during
each conversion, the greater the noise attenuation (see
Programming Conversion Time).
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Oversampling ClockXCLK internally connects to a clock-frequency divider
network, whose output is the ADC oversampling clock,
fOSC. This allows the selected clock source (internal RC
oscillator or external clock applied to XCLK) to be
divided by one, two, or four (see Clock Divider-Ratio
Control Bits).
Figure 3 shows the two methods for providing the over-
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to
XCLK (see Selecting the Oversampling Clock
Frequency).
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK
(Figure 1). Select RC-oscillator mode by connecting
RCSEL to VDD. This enables the internal oscillator and
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ADC OperationThe output data from the MAX110/MAX111 is arranged
in twos-complement format (Figures 4, 5). The sign bit
(POL) is shifted out first, followed by the overrange bit
(OR), and the 14 data bits (MSB first) (see Figure 6).
The MAX110 operates from ±5V power supplies and
converts low-frequency analog signals in the ±3V
range when using the maximum reference voltage of
VREF= 3V (VREF= VREF+- VREF-). Within the ±3V input
range, greater accuracy is obtained within ±2.5V (see
Electrical Characteristicsfor details). Note that a nega-
tive input voltage is defined as VIN-> VIN+. For the
MAX110, the absolute voltage at any analog input pin
must remain within the (VSS+ 2.25V) to (VDD- 2.25V)
range.
The MAX111 operates from a single +5V supply and
converts low-frequency differential analog signals in the
±1.5V range when using the maximum reference volt-
age of VREF= 1.5V. As indicated in the Electrical
Characteristics, greater accuracy is achieved within the
±1.2V range. The absolute voltage at any analog input
pin for the MAX111 must remain within 0V to VDD- 3.2V.
When VIN-> VIN+the input is interpreted as negative.
The overrange bit (OFL) is provided to sense when the
input voltage level has exceeded the reference voltage
level. The converter does not “saturate” until the input
voltage is typically 20% larger. The linearity is not guar-
anteed in this range. Note that the overrange bit works
properly if the reference voltage remains within the rec-
ommended voltage range (see Reference Inputs). If the
reference voltage exceeds the recommended input
range, the overrange bit may not operate properly.
Digital Interface—Starting a ConversionData is transferred into and out of the serial I/O shift
register by pulling CSlow and applying a serial clock
at SCLK. This fully static shift register allows SCLK to
range from DC to 2MHz. Output data from the ADC is
clocked out on SCLK’s falling edge and should be read
on SCLK’s rising edge. Input data to the ADC at DIN is
clocked in on SCLK’s rising edge. A new conversion
begins when CSreturns high, provided the MSB in the
input control word (NO-OP) is a 1 (see Using the
MAX110/MAX111 with MICROWIRE, SPI, and QSPI
Serial Interfaces). Figure 6 shows the detailed serial-
interface timing diagram.CSS
must remain high during the conversion(while
BUSYremains low). Bringing CSlow during the conver-
sion causes the ADC to stop converting, and may
result in erroneous output data.
Using the MAX110/MAX111 with SPI, QSPI, and
MICROWIRE Serial InterfacesFigure 7 shows the most common serial-interface con-
nections. The MAX110/MAX111 are compatible with
SPI, QSPI (CPHA = 0, CPOL = 0), and MICROWIRE
serial-interface standards.
MAX110/MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADCsFigure 4. Differential Transfer Function
Figure 5. Unipolar Transfer Function
