MAX1112CPP+ ,+5V, Low-Power, Multichannel, Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = 4.5V to 5.5V; unipolar input mode; V = 0V; f = 500kHz, external cloc ..
MAX1112EAP ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsApplicationsCSSCLKPortable Data LoggingINPUTINTHand-Held Measurement DevicesDIN SHIFTCLOCKREGISTERC ..
MAX1112EPP+ ,+5V, Low-Power, Multichannel, Serial 8-Bit ADCsApplicationsCH0OUTPUTDOUTPortable Data LoggingCH1SHIFTREGISTER SSTRBCH2ANALOGHand-Held Measurement ..
MAX1113CEE+ ,+5V, Low-Power, Multichannel, Serial 8-Bit ADCsMAX1112/MAX111319-1231; Rev 2; 4/11+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs
MAX1113EEE ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsApplicationsCSSCLKPortable Data LoggingINPUTINTHand-Held Measurement DevicesDIN SHIFTCLOCKREGISTERC ..
MAX1113EEE ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsGeneral Description ________
MAX3468CSA+ ,+5V, Fail-Safe, 40Mbps, PROFIBUS RS-485/RS-422 Transceivers
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA+ ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471CUA+T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX1112CAP+-MAX1112CPP+-MAX1112EPP+-MAX1113CEE+
+5V, Low-Power, Multichannel, Serial 8-Bit ADCs
General DescriptionThe MAX1112/MAX1113 low-power, 8-bit, 8-channel
analog-to-digital converters (ADCs) feature an internal
track/hold, voltage reference, clock, and serial inter-
face. They operate from a single 4.5V to 5.5V supply
and consume only 135µA while sampling at rates up to
50ksps. The MAX1112’s 8 analog inputs and the
MAX1113’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 4.096V internal reference, or by an
externally applied reference ranging from 1V to VDD.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1112/MAX1113 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the
SHDNinput pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1112 is available in a 20-pin SSOP package.
The MAX1113 is available in a small 16-pin QSOP
package.
________________________ApplicationsPortable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4mA to 20mA-Powered Remote
Data-Acquisition Systems
____________________________Features4.5V to 5.5V Single SupplyLow Power: 135µA at 50ksps
13µA at 1ksps8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1112)4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1113)Internal Track/Hold; 50kHz Sampling RateInternal 4.096V ReferenceSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSoftware-Configurable Unipolar or Bipolar InputsTotal Unadjusted Error:±1 LSB (max)
±0.3 LSB (typ)MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCsINPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+4.096V
REFERENCE
T/HANALOG
INPUT
MUX
8-BIT
SAR ADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7*
CH6*
CH5*
CH4*
COM
REFOUT
*MAX1112 ONLY
REFIN
OUTREF
CLOCK
MAX1112
MAX1113
SHDN
Functional Diagram19-1231; Rev 2; 4/11
EVALUATION KIT
AVAILABLE
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND...................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
QSOP (derate 8.30mW/°C above +70°C).....................667mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX1112CAP/MAX1113CEE...............................0°C to +70°C
MAX1112EAP/MAX1113EEE............................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
ELECTRICAL CHARACTERISTICS(VDD= 4.5V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
-3dB rolloffMHz1.5Small-Signal Bandwidth
kHz800
VCH_= 4.096VP-P, 25kHz (Note 3)
External reference, 4.096V
No missing codes over temperature
CONDITIONSFull-Power BandwidthInternal or external referenceLSBGain Error (Note 2)-75Channel-to-Channel Crosstalk68SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
(Up to the 5th Harmonic)
LSB±0.1Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
LSB±1DNLDifferential Nonlinearity
UNITSMINTYPMAXSYMBOLPARAMETERLSB±0.3±1TUETotal Unadjusted Error
Bits8Resolution49SINADSignal-to-Noise
and Distortion Ratio
LSB±0.1±0.5INLRelative Accuracy (Note 1)
LSB±0.3±1Offset Error
DC ACCURACY
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096VP-P, 50ksps, 500kHz external clock)
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 4.5V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
On/off leakage current, VCH_= 0V or VDD
Used for data transfer only
(Note 5)
External clock, 2MHz
CONDITIONSppm/°C±506REFOUT Short-Circuit Current18Input Capacitance±0.01±1Multiplexer Leakage Current500
kHz400Internal Clock Frequency
0 to 0.5mA output loadmV4.5Load Regulation (Note 7)10Aperture Delay1tACQTrack/Hold Acquisition Time
UNITSMINTYPMAXSYMBOLPARAMETER1 VDD+ Input Voltage Range
(Note 8)µA120Input Current
< 50Aperture Jitter
External clock, 500kHz, 10 clocks/conversion20
Internal clockµs2555tCONVConversion Time (Note 4)
Bipolar input, VCOM= VREFIN/2
Unipolar input, VCOM= 0V
COM ±
VREFIN/2
0VREFIN
Input Voltage Range, Single-
Ended and Differential (Note 6)3.9364.0964.256REFOUT Voltage
External Clock-Frequency RangeMHz
kHz
Capacitive Bypass at REFOUTµF
REFOUT Temperature Coefficient4.55.5VDDSupply Voltage
VDD= 4.5V to 5.5V; external reference,
4.096V; full-scale inputmV±0.4±4PSRPower-Supply Rejection
(Note 9)Power-down3.210
Software
SHDNat DGND
Operating mode135250Full-scale input
CLOAD= 10pFReference disabled95IDDµASupply Current
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REFIN
POWER REQUIREMENTS
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 4.5V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)= VDD(Note 5)= VDD
ISOURCE= 0.5mA
ISINK= 5mA
SHDN= open
SHDN= 0V or VDD
(Note 5)
Digital inputs = 0V or VDD
VSHDN= open
CONDITIONS15COUTThree-State Output Capacitance±0.01±10ILThree-State Leakage CurrentVDD- 0.5VOHOutput High Voltage0.4VOLOutput Low Voltage±100SHDNMaximum Allowed Leakage
for Mid-InputVDD/2VFLTSHDNVoltage, High Impedance±4SHDNInput CurrentVDD - 0.4VSHSHDNInput High Voltage0.8VILDIN, SCLK, CSInput Low Voltage1.1VDD- 1.1
ISINK= 16mA
VSM
0.815CINDIN, SCLK, CSInput Capacitance±1IINDIN, SCLK, CSInput Leakage
SHDNInput Mid-Voltage0.2VHYSTDIN, SCLK, CSInput Hysteresis
UNITSMINTYPMAXSYMBOLPARAMETER0.4VSLSHDNInput Low VoltageVIHDIN, SCLK, CSInput High Voltage3
DIGITAL INPUTS (DIN, SCLK, CS)
DIGITAL OUTPUTS (DOUT, SSTRB)SHDN
INPUT
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs100tCSS
Figure 1, external clock mode only,
CLOAD= 100pFnsto SCLK Rise Setup
Figure 1, CLOAD= 100pFns2000tCSH
CONDITIONSto SCLK Rise Hold
240tDVCSFall to Output Enable
Figure 2, CLOAD= 100pFns240tTRCSRise to Output Disable
tSDVCSFall to SSTRB Output Enable
(Note 5)
Figure 2, external clock mode only,
CLOAD= 100pFns240tSTRCSRise to SSTRB Output
Disable (Note 5)
Figure 11, internal clock mode onlyns0tSCKSSTRB Rise to SCLK Rise
(Note 5)200tCHSCLK Pulse Width High200tCLSCLK Pulse Width Low
CLOAD= 100pFns240tSSTRBSCLK Fall to SSTRB0tDHDIN to SCLK Hold1tACQTrack/Hold Acquisition Time100tDSDIN to SCLK Setup
UNITSMINTYPMAXSYMBOLPARAMETER
TIMING CHARACTERISTICS(Figures 8 and 9)
(VDD= 4.5V to 5.5V, TA= TMINto TMAX,unless otherwise noted.)
Note 1:Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:VREFIN= 4.096V, offset nulled.
Note 3:On-channel grounded; sine wave applied to all off-channels.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:Common-mode range for the analog inputs is from AGND to VDD.
Note 7:External load should not change during the conversion for specified accuracy.
Note 8:External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9:Measured as |VFS (4.5V) - VFS(5.5V) |.
Note 10:1µF at REFOUT; internal reference settling to 0.5 LSB.tDOSCLK Fall to Output Data ValidFigure 1, CLOAD= 100pF
External reference20
Internal reference (Note 10)tWAKEWakeup Timems
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
__________________________________________Typical Operating Characteristics
(VDD= 5.0V; fSCLK = 500kHz; external clock (50% duty cycle); RL= ∞; TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATUREMAX1112/13-01
TEMPERATURE (°C)
SUPPLY CURRENT (
OUTPUT CODE = FULL SCALE
CLOAD = 10pF
VDD = 5.5V
VDD = 4.5V
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1112/13-02
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (
SHDN = DGND
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX1112/13-03
DIGITAL CODE
DNL (LSB)128192
OFFSET ERROR vs. TEMPERATURE
MAX1112/13-04
TEMPERATURE (°C)
OFFSET ERROR (LSB)
INTEGRAL NONLINEARITY
vs. CODE
MAX1112/13-05
DIGITAL CODE
INL (LSB)128192
FFT PLOT
MAX1112/13-06
FREQUENCY (kHz)
AMPLITUDE (dB)101520
fCH_ = 10.034kHz, 4VP-P
fSAMPLE = 50ksps
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Pin DescriptionSSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CSis high (external clock mode only).VDDPositive Supply Voltage, 4.5V to 5.5V. Bypass to AGND with 0.1µF and 1µF capacitor
as close as possible to the device. Place the 0.1µF capacitor closer to VP-P.CSActive-Low Chip Select. Data is not clocked into DIN unless CSis low. When CSis
high, DOUT is high impedance.SCLKSerial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). DINSerial-Data Input. Data is clocked in at SCLK’s rising edge. REFOUTInternal Reference Generator Output. Bypass with a 1µF capacitor to AGND.DGNDDigital GroundDOUTSerial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance whenis high.AGNDAnalog GroundSHDN
Three-Level Shutdown Input. Normally high impedance. Pulling SHDNlow shuts the
MAX1112/MAX1113 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDNhigh shuts down the internal reference.REFINReference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8CH4–CH7Sampling Analog Inputs
1–4CH0–CH3Sampling Analog Inputs
+5V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOLFigure 1. Load Circuits for Enable Time
+5V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 2. Load Circuits for Disable Time
1–49COMGround Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
PIN
MAX1113
NAMEFUNCTION
MAX1112
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________Detailed DescriptionThe MAX1112/MAX1113 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1112
channels with Table 1 and the MAX1113 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5 LSB (±0.1 LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND if necessary.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 8-bit resolution. This
action is equivalent to transferring a charge of 18pF x
(VIN+- VIN-) from CHOLDto the binary-weighted capac-
itive DAC, which in turn forms a digital representation of
the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and CHOLD
charges to the input signal.
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
DGND
AGND
VDD
CH7
1μF
0.1μF1μF
CH0
ANALOG
INPUTS
MAX1112
MAX1113
CPU
+5V
REFIN
REFOUT
Figure 3. Typical Operating Circuit
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
COM
CSWITCH
TRACK
T/H
SWITCH
CHOLD
HOLD
CAPACITIVE DAC
REFIN
ZERO
COMPARATOR+
18pF
6.5kΩ
RIN
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1112 ONLY
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUTMUX
Figure 4. Equivalent Input Circuit
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 1b. MAX1112 Channel Selection in Differential Mode (SGL/DIF= 0)
Table 2a. MAX1113 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 2b. MAX1113 Channel Selection in Differential Mode (SGL/DIF= 0)+
111+
1
CH20+
0
CH31+
0
CH10–
1
CH01–
100–
001
COMCH7CH6SEL2CH5CH400
SEL0SEL1–
111–
0
CH21+
1
CH31–
0
CH11+
1
CH00+
010–
100
CH7CH6SEL2CH5CH400
SEL0SEL1X11X
CH10
CH0X01
SEL2CH3CH200
SEL0SEL1–
X11–
X
CH11
CH0+
X10
SEL2CH3CH200
SEL0SEL1
COM
MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Table 3.Control-Byte FormatSTARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)
NAMESGL/DIF2
BIT= single ended, 0= differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured (Tables 1 and 2).
DESCRIPTIONUNI/BIP3
START
= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode (Table 4).
PD00 (LSB)
7 (MSB)
= external clock mode, 0= internal clock mode.
Selects external or internal clock mode.
The first logic “1” bit after CSgoes low defines the beginning of the control byte.
SEL2
SEL1
SEL0
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
PD11
1 = fully operational, 0 = power-down.Selects fully operational or power-down mode.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by:
tACQ= 6 x (RS+ RIN) x 18pF
where RIN= 6.5kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1µs. Note that
source impedances below 2.4kΩdo not significantly
affect the AC performance of the ADC.
Input BandwidthThe ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog InputsInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (VDD+ 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.The MAX1112/MAX1113 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, analog inputs
are internally referenced to COM with a full-scale input
range from COM to VREFIN + COM. For bipolar opera-
tion, set COM to VREFIN/2.
In differential mode, choosing unipolar mode sets the
differential input range at 0V to VREFIN. In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±VREFIN/2.
Note that in this mode, the common-mode input range
includes both supply rails. See Table 4 for input voltage
ranges.
Quick LookTo quickly evaluate the MAX1112/MAX1113’s analog
performance, use the circuit of Figure 5. The
MAX1112/MAX1113 require a control byte to be written
to DIN before each conversion. Tying DIN to +5V feeds
