MAX1111EEE ,+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V; unipolar input mode; COM = 0V; f = 500kHz, external ..
MAX1111EEE ,+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V; unipolar input mode; COM = 0V; f = 500kHz, external ..
MAX1111EEE ,+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCsMAX1110/MAX111119-1194; Rev 2; 10/98+2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs
MAX1111EEE+ ,+2.7V, Low-Power, Multichannel, Serial, 8-Bit ADCsGeneral Description ________
MAX1111EEE+T ,+2.7V, Low-Power, Multichannel, Serial, 8-Bit ADCsApplicationsOUTPUTDOUTCH1SHIFTREGISTER SSTRBCH2Portable Data LoggingANALOGCH3T/HINPUTCH4*Hand-Held ..
MAX1111EPE ,+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCsMAX1110/MAX111119-1194; Rev 2; 10/98+2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs
MAX3468CSA+ ,+5V, Fail-Safe, 40Mbps, PROFIBUS RS-485/RS-422 Transceivers
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA+ ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471CUA+T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX1110CAP-MAX1110CPP-MAX1110EAP-MAX1111CEE-MAX1111CPE-MAX1111EEE-MAX1111EPE
+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCs
General DescriptionThe MAX1110/MAX1111 are low-power, 8-bit, 8-chan-
nel analog-to-digital converters (ADCs) that feature an
internal track/hold, voltage reference, clock, and serial
interface. They operate from a single +2.7V to +5.5V
supply and consume only 85µA while sampling at rates
up to 50ksps. The MAX1110’s 8 analog inputs and the
MAX1111’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 2.048V internal reference, or by an
externally applied reference ranging from 1V to VDD.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1110/MAX1111 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 6µA at 1ksps, and only 52µA at
10ksps. Power-down can also be controlled using the
SHDNinput pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1110 is available in 20-pin SSOP and DIP
packages. The MAX1111 is available in small 16-pin
QSOP and DIP packages.
________________________ApplicationsPortable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4–20mA-Powered Remote
Data-Acquisition Systems
____________________________Features+2.7V to +5.5V Single SupplyLow Power: 85µA at 50ksps
6µA at 1ksps8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1110)4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1111)Internal Track/Hold; 50kHz Sampling RateInternal 2.048V ReferenceSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSoftware-Configurable Unipolar or Bipolar InputsTotal Unadjusted Error: ±1LSB max
±0.3LSBtyp
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
________________Functional Diagram
Pin Configurations appear at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIREis a trademark of National Semiconductor Corp.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND..............................................................-0.3V to 6V
AGND to DGND.......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................................-0.3V to 6V
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
16 Plastic DIP (derate 10.53mW/°C above +70°C)......842mW
16 QSOP (derate 8.30mW/°C above +70°C)................667mW
16 CERDIP (derate 10.00mW/°C above +70°C) ..........800mW
20 Plastic DIP (derate 11.11mW/°C above +70°C)......889mW
20 SSOP (derate 8.00mW/°C above +70°C)................640mW
20 CERDIP (derate 11.11mW/°C above +70°C) ..........889mW
Operating Temperature Ranges
MAX1110C_P/MAX1111C_E................................0°C to +70°C
MAX1110E_P/MAX1111E_E.............................-40°C to +85°C
MAX1110MJP/MAX1111MJE..........................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.5V; unipolar input mode; COM = 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion
cycle (50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)(VDD= +2.7V to +5.5V, TA= TMINto TMAX,unless otherwise noted.)
Note 1:Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:See Typical Operating Characteristics.
Note 3:VREFIN= 2.048V, offset nulled.
Note 4:On-channel grounded; sine wave applied to all off-channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:Common-mode range for the analog inputs is from AGND to VDD.
Note 8:External load should not change during the conversion for specified accuracy.
Note 9:External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10:Measured as |VFS (2.7V) - VFS(3.6V) |.
Note 11:1µF at REFOUT; internal reference settling to 0.5LSB.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
__________________________________________Typical Operating Characteristics(VDD= +2.7V; fSCLK = 500kHz; external clock (50% duty cycle); RL= ¥; TA = +25°C, unless otherwise noted.)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________Pin DescriptionFigure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
_______________Detailed DescriptionThe MAX1110/MAX1111 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1110
channels with Table 1 and the MAX1111 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLDfrom the positive input (IN+) to the negative
input (IN-). In single-ended mode, IN- is simply COM.
This unbalances node ZERO at the input of the com-
parator. The capacitive DAC adjusts during the remain-
der of the conversion cycle to restore node ZERO to 0V
within the limits of 8-bit resolution. This action is equiva-
lent to transferring a charge of 18pF x (VIN+- VIN-) from
CHOLDto the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and CHOLD
charges to the input signal.
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Table 1a. MAX1110 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 1b. MAX1110 Channel Selection in Differential Mode (SGL/DIF= 0)
Table 2a. MAX1111 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 2b. MAX1111 Channel Selection in Differential Mode (SGL/DIF= 0)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Table 3.Control-Byte FormatThe time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by:
tACQ= 6 x (RS+ RIN) x 18pF
where RIN= 6.5kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1µs. Note that
source impedances below 2.4kΩdo not significantly
affect the AC performance of the ADC.
Input BandwidthThe ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog InputsInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (VDD+ 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.The MAX1110/MAX1111 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, the analog
inputs are internally referenced to COM with a full-scale
input range from COM to VREFIN +COM. For bipolar
operation, set COM to VREFIN/ 2.
In differential mode, choosing unipolar mode sets the
differential input range at 0V to VREFIN. In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±VREFIN/ 2.
Note that in this mode, the common-mode input range
includes both supply rails. Refer to Table 4 for input
voltage ranges.
Quick LookTo quickly evaluate the MAX1110/MAX1111’s analog
performance, use the circuit of Figure 5. The
MAX1110/MAX1111 require a control byte to be written
to DIN before each conversion. Tying DIN to +3V feeds
