MAX1111EEE+ ,+2.7V, Low-Power, Multichannel, Serial, 8-Bit ADCsGeneral Description ________
MAX1111EEE+T ,+2.7V, Low-Power, Multichannel, Serial, 8-Bit ADCsApplicationsOUTPUTDOUTCH1SHIFTREGISTER SSTRBCH2Portable Data LoggingANALOGCH3T/HINPUTCH4*Hand-Held ..
MAX1111EPE ,+2.7V / Low-Power / Multichannel / Serial 8-Bit ADCsMAX1110/MAX111119-1194; Rev 2; 10/98+2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs
MAX1112CAP ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsFeaturesThe MAX1112/MAX1113 are low-power, 8-bit, 8-chan-' +4.5V to +5.5V Single Supplynel analog-t ..
MAX1112CAP ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsMAX1112/MAX111319-1231; Rev 1; 10/98+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs
MAX1112CAP ,+5V, Low-Power, Multi-Channel, Serial 8-Bit ADCsFeaturesThe MAX1112/MAX1113 are low-power, 8-bit, 8-chan-' +4.5V to +5.5V Single Supplynel analog-t ..
MAX3468CSA+ ,+5V, Fail-Safe, 40Mbps, PROFIBUS RS-485/RS-422 Transceivers
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA+ ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471CUA+T ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX3471EUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX1110CAP+-MAX1110CAP+T-MAX1110EAP+-MAX1110EAP+T-MAX1111CEE+T-MAX1111EEE+-MAX1111EEE+T
+2.7V, Low-Power, Multichannel, Serial, 8-Bit ADCs
General DescriptionThe MAX1110/MAX1111 low-power, 8-bit, 8-channel
analog-to-digital converters (ADCs) feature an internal
track/hold, voltage reference, clock, and serial inter-
face. They operate from a single 2.7V to 5.5V supply
and consume only 85µA while sampling at rates up to
50ksps. The MAX1110’s 8 analog inputs and the
MAX1111’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential
operation.
Successive-approximation conversions are performed
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter-
mined by the 2.048V internal reference, or by an
externally applied reference ranging from 1V to VDD.
The 4-wire serial interface is compatible with the SPI™,
QSPI™, and MICROWIRE™ serial-interface standards.
A serial-strobe output provides the end-of-conversion
signal for interrupt-driven processors.
The MAX1110/MAX1111 have a software-program-
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 6µA at 1ksps, and only 52µA at
10ksps. Power-down can also be controlled using the
SHDNinput pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1110 is available in a 20-pin SSOP package.
The MAX1111 is available in a small 16-pin QSOP
package.
________________________ApplicationsPortable Data Logging
Hand-Held Measurement Devices
Medical Instruments
System Diagnostics
Solar-Powered Remote Systems
4mA to 20mA-Powered Remote
Data-Acquisition Systems
____________________________Features2.7V to 5.5V Single SupplyLow Power: 85µA at 50ksps
6µA at 1ksps8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1110)4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1111)Internal Track/Hold; 50kHz Sampling RateInternal 2.048V ReferenceSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSoftware-Configurable Unipolar or Bipolar InputsTotal Unadjusted Error: ±1 LSB (max)
±0.3 LSB(typ)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCsINPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.048V
REFERENCE
T/HANALOG
INPUT
MUX
8-BIT
SAR ADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7*
CH6*
CH5*
CH4*
COM
REFOUT
*MAX1110 ONLY
REFIN
OUTREF
CLOCK
MAX1110
MAX1111
SHDN
________________Functional Diagram19-1194; Rev 4; 4/11
EVALUATION KIT
AVAILABLE
Ordering Information appears at end of data sheet.
Pin Configurations appear at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIREis a trademark of National Semiconductor Corp.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND..............................................................-0.3V to 6V
AGND to DGND.......................................................-0.3V to 0.3V
CH0–CH7, COM, REFIN,
REFOUT to AGND......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................................-0.3V to 6V
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
QSOP (derate 8.30mW/°C above +70°C).....................667mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX1110CAP/MAX1111CEE...............................0°C to +70°C
MAX1110EAP/MAX1111EGE............................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
ELECTRICAL CHARACTERISTICS(VDD= 2.7V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
-3dB rolloffMHz1.5Small-Signal Bandwidth
kHz800
VCH_= 2.048VP-P, 25kHz (Note 4)
External reference, 2.048V
VDD= 2.7V to 3.6V
VDD= 2.7V to 3.6V
No missing codes over temperature
±0.35±1
CONDITIONSFull-Power BandwidthInternal or external referenceLSBGain Error (Note 3)-75Channel-to-Channel Crosstalk68SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
(up to the 5th harmonic)
±0.15±0.5
LSB±0.1Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
LSB±1DNLDifferential Nonlinearity
UNITSMINTYPMAXSYMBOLPARAMETERLSB±0.3±1TUETotal Unadjusted Error
Bits8Resolution49SINADSignal-to-Noise
and Distortion Ratio
VDD= 5.5V (Note 2)LSB±0.2INLRelative Accuracy (Note 1)
VDD= 5.5V (Note 2)LSB±0.5Offset Error
DC ACCURACY
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 2.048VP-P, 50ksps, 500kHz external clock)
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)
On/off-leakage current, VCH_= 0V or VDD
Used for data transfer only
(Note 6)
External clock, 2MHz
CONDITIONSppm/°C±503.5REFOUT Short-Circuit Current18Input Capacitance±0.01±1Multiplexer Leakage Current500
kHz400Internal Clock Frequency
0 to 0.5mA output loadmV2.5Load Regulation (Note 8)10Aperture Delay1tACQTrack/Hold Acquisition Time
UNITSMINTYPMAXSYMBOLPARAMETER1 VDD+
0.05Input Voltage Range
(Note 9)µA120Input Current
<50Aperture Jitter
External clock, 500kHz, 10 clocks/conversion20
Internal clockµs2555tCONVConversion Time (Note 5)
Bipolar input, VCOM= VREFIN/2
Unipolar input, VCOM= 0V
VCOM±
VREFIN/2
0VREFIN
Input Voltage Range, Single-
Ended and Differential (Note 7)1.9682.0482.128REFOUT Voltage
External Clock-Frequency RangeMHz
kHz
Capacitive Bypass at REFOUTµF
REFOUT Temperature Coefficient2.75.5VDDSupply Voltage250
IDDSupply Current (Note 2)
VDD= 2.7V to 3.6V
Full-scale input
CLOAD= 10pF
VDD= 2.7V to 3.6V; external reference,
2.048V; full-scale inputmV±0.4±4PSRPower-Supply Rejection
(Note 10)
Operating mode
Power-down3.210
Software
SHDNat DGND
Operating mode120250VDD= 5.5V
Full-scale input
CLOAD= 10pF
Reference disabled
Reference disabled
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REFIN
POWER REQUIREMENTS
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 5.5V; unipolar input mode; VCOM= 0V; fSCLK= 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA= TMIN toTMAX; unless otherwise noted.)= VDD(Note 6)= VDD
ISOURCE= 0.5mA
ISINK= 5mA
SHDN= open
VSHDN= 0V or VDD
(Note 6)
Digital inputs = 0V or VDD
SHDN= open
CONDITIONS15COUTThree-State Output Capacitance±0.01±10ILThree-State Leakage CurrentVDD- 0.5VOHOutput High Voltage0.4VOLOutput Low Voltage±100SHDNMaximum Allowed Leakage
for Mid-InputVDD/2VFLTSHDNVoltage, High Impedance±4SHDNInput CurrentVDD - 0.4VSHSHDNInput High Voltage0.8VILDIN, SCLK, CSInput Low Voltage1.1VDD- 1.1
ISINK= 16mA
VSM
0.815CINDIN, SCLK, CSInput Capacitance±1IINDIN, SCLK, CSInput Leakage
SHDNInput Mid-Voltage0.2VHYSTDIN, SCLK, CSInput Hysteresis
UNITSMINTYPMAXSYMBOLPARAMETER0.4VSLSHDNInput Low Voltage
VDD≤3.6V
VDD> 3.6VV2VIHDIN, SCLK, CSInput High Voltage3
DIGITAL INPUTS: DIN, SCLK, CS
DIGITAL OUTPUTS: DOUT, SSTRBSHDN
INPUT
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD= 2.7V to 5.5V, TA= TMINto TMAX,unless otherwise noted.)
Note 1:Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:See Typical Operating Characteristics.
Note 3:VREFIN= 2.048V, offset nulled.
Note 4:On-channel grounded; sine wave applied to all off-channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:Common-mode range for the analog inputs is from AGND to VDD.
Note 8:External load should not change during the conversion for specified accuracy.
Note 9:External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10:Measured as |VFS (2.7V) - VFS(3.6V) |.
Note 11:1µF at REFOUT; internal reference settling to 0.5 LSB.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Track/Hold Acquisition TimetACQ1µs
DIN to SCLK SetuptDS100ns
DIN to SCLK HoldtDH0ns
SCLK Fall to Output Data ValidtDOFigure 1, CLOAD = 100pF20200ns
CS Fall to Output EnabletDVFigure 1, CLOAD = 100pF240ns
CS Rise to Output DisabletTRFigure 2, CLOAD = 100pF240ns
CS to S C LK Ri se S etup tCSS100ns
CS to SCLK Rise HoldtCSH0ns
SCLK Pulse Width HightCH200ns
SCLK Pulse Width LowtCL200ns
SCLK Fall to SSTRBt SSTRBCLOAD = 100pF240ns
CS Fall to SSTRB Output Enable
(Note 6)tSDVFigure 1, external clock mode only,
CLOAD = 100pF240ns
CS Rise to SSTRB output
Disable (Note 6)tSTRFigure 2, external clock mode only,
CLOAD = 100pF240ns
SSTRB Rise to SCLK Rise
(Note 6)tSCKFigure 11, internal clock mode only0ns
External reference20µsWake-Up TimetWAKEInternal reference (Note 11)12ms
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
__________________________________________Typical Operating Characteristics
(VDD= 2.7V; fSCLK = 500kHz; external clock (50% duty cycle); RL= ∞; TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGEMAX1110-01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
OUTPUT CODE = 10101010
CLOAD = 60pF
CLOAD = 30pF
SUPPLY CURRENT vs. TEMPERATURE
MAX1110-02
TEMPERATURE (°C)
SUPPLY CURRENT (
OUTPUT CODE = FULL SCALE
CLOAD = 10pF
VDD = 5.5V
VDD = 3.6V
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1110-03
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (
SHDN = DGND
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1110-04
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
INTEGRAL NONLINEARITY vs.
SUPPLY VOLTAGE
MAX1110-05
SUPPLY VOLTAGE (V)
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX1110-06
DIGITAL CODE
DNL (LSB)128192
OFFSET ERROR vs. TEMPERATURE
MAX1110-07
TEMPERATURE (°C)
OFFSET ERROR (LSB)
INTEGRAL NONLINEARITY
vs. CODE
MAX1110-08
DIGITAL CODE
INL (LSB)128192
FFT PLOT
MAX1110-09
FREQUENCY (kHz)
AMPLITUDE (dB)
fCH_ = 10.034kHz, 2VP-P
fSAMPLE = 50ksps
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
______________________________________________________________Pin DescriptionSSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/
MAX1111 begin the A/D conversion and goes high when the conversion is done.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CSis high (external clock mode only).VDDPositive Supply Voltage, 2.7V to 5.5VCSActive-Low Chip Select. Data is not clocked into DIN unless CSis low. When CSis
high, DOUT is high impedance. The voltage at CScan exceed VDD (up to 5.5V).SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at
SCLK can exceed VDD (up to 5.5V).DINSerial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN can
exceed VDD (up to 5.5V).REFOUTInternal Reference Generator Output. Bypass with a 1µF capacitor to AGND.DGNDDigital GroundDOUTSerial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance whenis high.AGNDAnalog GroundSHDN
Three-Level Shutdown Input. Normally high impedance. Pulling SHDNlow shuts the
MAX1110/MAX1111 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDNhigh shuts down the internal reference.REFINReference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8CH4–CH7Sampling Analog Inputs
1–4CH0–CH3Sampling Analog Inputs
+3V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOLFigure 1. Load Circuits for Enable Time
+3V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 2. Load Circuits for Disable Time
1–49COMGround Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
PIN
MAX1111NAMEFUNCTIONMAX1110
_______________Detailed DescriptionThe MAX1110/MAX1111 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 shows the Typical Operating Circuit.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in Figure 4, the equivalent input cir-
cuit. In single-ended mode, IN+ is internally switched to
the selected input channel, CH_, and IN- is switched to
COM. In differential mode, IN+ and IN- are selected
from the following pairs: CH0/CH1, CH2/CH3,
CH4/CH5, and CH6/CH7. Configure the MAX1110
channels with Table 1 and the MAX1111 channels with
Table 2.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5 LSB (±0.1 LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans two SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLDfrom the positive input (IN+) to the negative
input (IN-). In single-ended mode, IN- is simply COM.
This unbalances node ZERO at the input of the com-
parator. The capacitive DAC adjusts during the remain-
der of the conversion cycle to restore node ZERO to 0V
within the limits of 8-bit resolution. This action is equiva-
lent to transferring a charge of 18pF x (VIN+- VIN-) from
CHOLDto the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the sixth bit of the 8-bit control byte has
been shifted in. It enters its hold mode on the falling
clock edge after the eighth bit of the control byte has
been shifted in. If the converter is set up for single-
ended inputs, IN- is connected to COM, and the con-
verter samples the “+” input; if it is set up for differential
inputs, IN- connects to the “-” input, and the difference
(IN+ - IN-) is sampled. At the end of the conversion, the
positive input connects back to IN+, and CHOLD
charges to the input signal.
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCsVDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
DGND
AGND
VDD
CH7
1μF
0.1μF1μF
CH0
ANALOG
INPUTS
MAX1110
MAX1111
CPU
+2.7V
REFIN
REFOUT
Figure 3. Typical Operating Circuit
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
COM
CSWITCH
TRACK
T/H
SWITCH
CHOLD
HOLD
CAPACITIVE DAC
REFIN
ZERO
COMPARATOR+
18pF
6.5kΩ
RIN
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*.
*MAX1110 ONLY
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Table 1a. MAX1110 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 1b. MAX1110 Channel Selection in Differential Mode (SGL/DIF= 0)
Table 2a. MAX1111 Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 2b. MAX1111 Channel Selection in Differential Mode (SGL/DIF= 0)+
111+
1
CH20+
0
CH31+
0
CH10–
1
CH01–
100–
001
COMCH7CH6SEL2CH5CH400
SEL0SEL1–
111–
0
CH21+
1
CH31–
0
CH11+
1
CH00+
010–
100
CH7CH6SEL2CH5CH400
SEL0SEL1X11X
CH10
CH0X01
SEL2CH3CH200
SEL0SEL1–
X11–
X
CH11
CH0+
X10
SEL2CH3CH200
SEL0SEL1
COM
MAX1110/MAX1111
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Table 3.Control-Byte FormatSTARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)
NAMESGL/DIF2
BIT= single ended, 0= differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured (Tables 1 and 2).
DESCRIPTIONUNI/BIP3
START
= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. Select differential operation
if bipolar mode is used (Table 4).
PD00 (LSB)
7 (MSB)
= external clock mode, 0= internal clock mode.
Selects external or internal clock mode.
The first logic “1” bit after CSgoes low defines the beginning of the control byte.
SEL2
SEL1
SEL0
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
PD11
1 = fully operational, 0 = power-down.Selects fully operational or power-down mode.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by:
tACQ= 6 x (RS+ RIN) x 18pF
where RIN= 6.5kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1µs. Note that
source impedances below 2.4kΩdo not significantly
affect the AC performance of the ADC.
Input BandwidthThe ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog InputsInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from (AGND - 0.3V) to (VDD+ 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.The MAX1110/MAX1111 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, the analog
inputs are internally referenced to COM with a full-scale
input range from COM to VREFIN +COM. For bipolar
operation, set COM to VREFIN/2.
In differential mode, choosing unipolar mode sets the
differential input range at 0V to VREFIN. In unipolar
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±VREFIN/2.
Note that in this mode, the common-mode input range
includes both supply rails. Refer to Table 4 for input
voltage ranges.
Quick LookTo quickly evaluate the MAX1110/MAX1111’s analog
performance, use the circuit of Figure 5. The
MAX1110/MAX1111 require a control byte to be written
to DIN before each conversion. Tying DIN to +3V feeds
