MAX110BCPE+ ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsapplications. A fast550μA (MAX110)serial interface simplifies signal routing and opto-isola-640μA ( ..
MAX110BCWE ,Low-Cost, 2-Channel, 【14-Bit Serial ADCsMAX110/MAX11119-0283; Rev 5; 11/98Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110BCWE+ ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsMAX110/MAX11119-0283; Rev 5; 11/98Low -Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110BCWE+T ,Low-Cost, 2-Channel, ±14-Bit Serial ADCsApplicationsMAX110ACWE 0°C to +70°C 16 Wide SO ±0.03Process ControlMAX110BCWE 0°C to +70°C 16 Wide ..
MAX110BEAP ,Low-Cost, 2-Channel, 【14-Bit Serial ADCsGeneral Description ________
MAX110BEPE ,Low-Cost, 2-Channel, 【14-Bit Serial ADCsApplicationsMAX110ACWE 0°C to +70°C 16 Wide SO ±0.03Process ControlMAX110BCWE 0°C to +70°C 16 Wide ..
MAX3460CSD ,+5V / Fail-Safe / 20Mbps / Profibus RS-485/ RS-422 Transceivers
MAX3462CSA+ ,+5V, Fail-Safe, 20Mbps, PROFIBUS RS-485/RS-422 Transceivers
MAX3468CSA+ ,+5V, Fail-Safe, 40Mbps, PROFIBUS RS-485/RS-422 Transceivers
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA ,1.6A / RS-485/RS-422 / Half-Duplex / Differential Transceiver for Battery-Powered Systems
MAX3471CUA+ ,1.6µA, RS-485/RS-422, Half Duplex, Differential Transceiver for Battery-Powered Systems
MAX110ACPE+-MAX110AEWE+-MAX110BCPE+-MAX110BCWE+-MAX110BCWE+T-MAX111ACAP+-MAX111BCPE+-MAX111BCWE+-MAX111BEWE+
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Low-Cost, 2-Channel, ±14-Bit Serial ADC
General DescriptionThe MAX110/MAX111 analog-to-digital converters
(ADCs) use an internal auto-calibration technique to
achieve 14-bit resolution plus overrange, with no exter-
nal components. Operating supply current is only
550μA (MAX110) and reduces to 4μA in power-down
mode, making these ADCs ideal for high-resolution bat-
tery-powered or remote-sensing applications. A fast
serial interface simplifies signal routing and opto-isola-
tion, saves microcontroller pins, and offers compatibility
with SPI™, QSPI™, and MICROWIRE™. The MAX110
operates with ±5V supplies, and converts differential
analog signals in the -3V to +3V range. The MAX111
operates with a single +5V supply and converts differ-
ential analog signals in the ±1.5V range, or single-
ended signals in the 0V to +1.5V range.
Internal calibration allows for both offset and gain-error
correction under microprocessor (μP) control. Both
devices are available in space-saving 16-pin DIP and
SO packages, as well as an even smaller 20-pin SSOP
package.
________________________ApplicationsProcess Control
Weigh Scales
Panel Meters
Data-Acquisition Systems
Temperature Measurement
____________________________FeaturesSingle +5V Supply (MAX111)Two Differential Input Channels14-Bit Resolution Plus Sign and Overrange0.03% Linearity (MAX110)
0.05% Linearity (MAX111)Low Power Consumption:
550μA (MAX110)
640μA (MAX111)
4μA Shutdown CurrentUp to 50 Conversions/sec50Hz/60Hz RejectionAuto-Calibration ModeNo External Components Required16-Pin DIP/SO, 20-Pin SSOP
Ordering Information19-0283; Rev 5; 11/98
Typical Operating CircuitPin ConfigurationsIN1+
IN1-
REF+
REF-
RCSEL
SCLK
DIN
DOUT
IN2+
IN2-
VDD
+5V
-5V (0V)
FROM μC
MAX110
MAX111
( ) ARE FOR MAX111
VSS
(AGND)
IN1+
REF-
REF+
VDD
RCSEL
XCLK
SCLK
BUSY
IN1-
IN2+
IN2-
VSS (AGND)
GND
DIN
DOUT
TOP VIEW
MAX110
MAX111
DIP/SO( ) ARE FOR MAX111
PART
MAX110ACPEMAX110BCPE
MAX110ACWE0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGEPIN-PACKAGE16 Plastic DIP
16 Plastic DIP
16 Wide SO
MAX110BCWE0°C to +70°C16 Wide SO
MAX110ACAP0°C to +70°C20 SSOP
MAX110BCAP0°C to +70°C20 SSOP
EVALUATION KIT
AVAILABLEMAX110BC/D0°C to +70°CDice*
Ordering Information continued at end of data sheet.Contact factory for dice specifications.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
INL(%)±0.03
±0.05
±0.03
±0.05
±0.03
±0.05
±0.05
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ABSOLUTE MAXIMUM RATINGSVDDto GND...........................................................................+6V
VSSto GND (MAX110)..............................................+0.3V to -6V
AGND to DGND.....................................................-0.3V to +0.3V
VIN1+, VIN1-......................................(VDD+ 0.3V) to (VSS- 0.3V)
VIN2+, VIN2-......................................(VDD+ 0.3V) to (VSS- 0.3V)
VREF+, VREF-....................................(VDD+ 0.3V) to (VSS- 0.3V)
Digital Inputs and Outputs.........................(VDD+ 0.3V) to -0.3V
Continuous Power Dissipation
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C).....842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
20-Pin SSOP (derate 8.00mW/°C above +70°C)...........640mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW
Operating Temperature Ranges
MAX11_ _C_ _......................................................0°C to +70°C
MAX11_ _E_ _...................................................-40°C to +85°C
MAX11_BMJE.................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX110(VDD= 5V ±5%, VSS= -5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= -1.5V, = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
LSB500
CONDITIONSIIN+, IIN-Input Bias Current
(Note 3)pF10
-0.83 x VREF≤VIN≤0.83 x VREF
-VREF≤VIN≤VREF
-0.83 x VREF≤VIN≤0.83 x VREF
Input Capacitance
-VREF≤VIN≤VREFVSS +VDD -
VIN+,
VIN-
Absolute Input Voltage
Range-VREF+VREFVINDifferential Input Voltage
Range
ppm30Power-Supply Rejection15
ppm/°C8Full-Scale Error
Temperature Drift±0.1
μV/°C0.003Offset Error
Temperature Drift
(Note 6)
UNITSMINTYPMAXSYMBOLPARAMETER±4Offset Error
±0.018
±0.03±0.06
±0.015±0.03
±0.04
VIN+= VIN-= 0V
MAX110BC/E
MAX110AC/E
After gain calibration (Note 5)
After offset null
VSS= -5V, VDD= 4.75V to 5.25V
VDD= 5V, VSS= -4.75V to -5.25V
(Notes 3, 4)±2DNLDifferential Nonlinearity
ppm/V6CMRRCommon-Mode Rejection
Ratio-2.5V ≤(VIN+= VIN-) ≤2.5V
Uncalibrated0Full-Scale ErrorUncalibrated
-VREF≤VIN≤VREF
-0.83 x VREF≤VIN≤0.83 x VREF
%FSRINLRelative Accuracy
(Notes 3, 5–7)
±0.1
±0.05MAX110BM
(Note 2)14 + POL
+ OFLRESResolutionBits
No-Missing-Codes
Resolution(Note 3)13 + POL
+ OFLBits
ACCURACY (Note 1)
ANALOG INPUTS
Low-Cost, 2-Channel, ±14-Bit Serial ADC
ELECTRICAL CHARACTERISTICS—MAX110 (continued)(VDD= 5V ±5%, VSS= -5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= -1.5V, = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)4.755.25VDDPositive Supply Voltage
0.8VIL-4.75-5.25VSSNegative Supply Voltage
Input Low Voltage
IDDPositive Supply CurrentVDD= 5.25V,
VSS= -5.25V
Performance guaranteed by supply rejection test
Performance guaranteed by supply rejection test10
VDD- 0.5VOHOutput High Voltage
Input Capacitance
fXCLK= 500kHz,
continuous-conversion modeISSNegative Supply CurrentVDD= 5.25V,
VSS= -5.25V
20.4810IDD
ILKGInput Leakage Current
XCLK unloaded,
continuous-conversion mode, RC
oscillator operational (Note 9)
fXCLK= 500kHz,
continuous-conversion mode
(Note 3)±10ILKGLeakage Current10Output Capacitance0.052
Digital inputs at 0V or 5V
Power-Down Current
DOUT, BUSY, VDD= 4.75V, ISOURCE= 1.0mA
VDD= 5.25V, VSS= -5.25V, VXCLK= 0V, PD = 1
VOUT= 5V or 0V
(Note 3)
10,240 clock-cycles/conversion
DOUT, BUSY, ISINK= 1.6mA
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER204.80tCONVSynchronous Conversion
Time (Note 7)102,400 clock-cycles/conversion
MHz0.251.25fOSCOversampling Clock
Frequency(Note 8)2.4VIHInput High Voltage
ISS03.0VREFDifferential Reference
Input Voltage Range10Reference Input
Capacitance(Note 3)0.4VOLOutput Low VoltageXCLK, ISINK= 200μA
VDD- 0.5XCLK, VDD= 4.75V, ISOURCE= 200μA500IREF+,
IREF-Reference Input CurrentVREF+= 2.5V, VREF-= 0VVSS +VDD -
VREF+,
VREF-
Absolute Reference Input
Voltage Range
CONVERSION TIME
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD)
POWER REQUIREMENTS(all digital inputs at 0V or 5V)
REFERENCE INPUTS
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX111(VDD= 5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= 0V, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
LSB500
CONDITIONSIIN+, IIN-Input Bias Current
(Note 3)pF10
-0.667 x VREF≤VIN≤0.667 x VREF
-VREF≤VIN≤VREF
-0.667 x VREF≤VIN≤0.667 x VREF
Input Capacitance
-VREF≤VIN≤VREF0VDD - 3.2VIN+,
VIN-
Absolute Input Voltage
Range-VREF+VREFVINDifferential Input Voltage
Range
-VREF≤VIN≤VREF
ppm15VDD= 4.75V to 5.25VPower-Supply Rejection
%FSRINL
ppm/°C8Full-Scale Error
Temperature Drift
Relative Accuracy,
Differential Input
(Notes 3, 5–7)
(Notes 3, 4)
±0.25±0.2
±0.20
DNLDifferential Nonlinearity
(Note 6)
UNITSMINTYPMAXSYMBOLppm/V6
(Note 2)
PARAMETER14 + POL
+ OFLRESResolution
CMRR±4Offset Error
Common-Mode Rejection
Ratio10mV ≤(VIN+= VIN-) ≤2.0V
Bits
No-Missing-Codes
Resolution
±0.10
(Note 3)0
±0.05±0.10
Full-Scale ErrorUncalibrated
±0.03±0.05
MAX111BM
13 + POL
+ OFLBits
±0.18
VIN+= VIN-= 0V
MAX111BC/E
MAX111AC/E
After gain calibration (Note 5)
VIN≤0.667 x VREF
0V ≤VIN≤VREF
VIN≤0.667 x VREF
0V ≤VIN≤VREF
0V ≤VIN≤VREF
VIN≤0.667 x VREF
%FSRINL
Relative Accuracy,
Single-Ended Input
(IN- = GND)
±0.25
±0.15
±0.10
±0.1
±0.06
MAX111BM
±0.18MAX111BC/E
MAX111AC/E
ACCURACY (Note 1)
ANALOG INPUTS-0.667 x VREF≤VIN≤0.667 x VREF
Low-Cost, 2-Channel, ±14-Bit Serial ADC
ELECTRICAL CHARACTERISTICS—MAX111 (continued)(VDD= 5V ±5%, fXCLK= 1MHz, ÷2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+= 1.5V, VREF-= 0V, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)4.755.25VDDPositive Supply Voltage
VOL
0.8VIL
Output Low Voltage
Input Low Voltage
tCONVSynchronous Conversion
Time (Note 7)102,400 clock-cycles/conversion
XCLK, ISINK= 200μA10Reference Input
Capacitance
MHz0.251.25
fOSCOversampling Clock
Frequency(Note 8)2.4VIHInput High Voltage
(Note 3)01.5VREF
IDDSupply CurrentVDD= 5.25V
Differential Reference
Input Voltage Range
Performance guaranteed by supply rejection test
500IREF+,
IREF-Reference Input Current10
VREF+= 1.5V, VREF-= 0V
0.40VDD - 3.2VREF+,
VREF-
VDD- 0.5VOHOutput High Voltage
Input Capacitance
Absolute Reference Input
Voltage Range
VDD- 0.5
fXCLK= 500kHz,
continuous-conversion mode±1
XCLK, VDD= 4.75V, ISOURCE= 200μA
20.4810IDD
ILKGInput Leakage Current
XCLK unloaded,
continuous-conversion mode, RC
oscillator operational (Note 9)
(Note 3)±1ILKGLeakage Current10Output Capacitance
Digital inputs at 0V or 5V
Power-Down Current
DOUT, BUSY, VDD= 4.75V, ISOURCE= 1.0mA
VDD= 5.25V, VXCLK= 0V, PD = 1
VOUT= 5V or 0V
(Note 3)
10,240 clock-cycles/conversion
DOUT, BUSY, ISINK= 1.6mA
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
CONVERSION TIME
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD)
POWER REQUIREMENTS(all digital inputs at 0V or 5V)
REFERENCE INPUTS
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Note 10:Timing specifications are guaranteed by design. All input control signals are specified with tr= tf= 5ns
(10% to 90% of +5V) and timed from a +1.6V voltage level.
Note 1:These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at VDD= 5V and VSS= -5V (MAX110).
Note 2:32,768 LSBs cover an input voltage range of ±VREF(15 bits). An additional bit (OFL) is set for VIN> VREF.
Note 3:Guaranteed by design. Not subject to production testing.
Note 4:DNL is less than ±2 counts (LSBs) out of 215counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5:See 3-Step Calibrationsection in text.
Note 6:VREF= (VREF+- VREF-), VIN= (VIN1+- VIN1-) or (VIN2+- VIN2-). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7:Conversion time is set by control bits CONV1–CONV4.
Note 8:Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristicssection for the effect of other clock frequencies. Also read the Clock Frequencysection.
Note 9:This current depends strongly on CXCLK(see Applications Informationsection).
TIMING CHARACTERISTICS(see Figure 6)
(VDD= 5V, VSS= -5V (MAX110), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MHz
1.13.0MAX11_ BM
RC Oscillator Frequency1.32.8MAX11_ _C/E
2.0TA= +25°C
PARAMETERSYMBOLMINTYPMAXUNITSto SCLK Hold Time
(Note 10)tCSH0ns
DIN to SCLK Setup Time
(Note 10)tDS
DIN to SCLK Hold Time
(Note 10)tDH0ns
100CSto SCLK Setup Time
(Note 10)tCSS
120SCLK, XCLK Pulse Width
(Note 10)tCK
1603580100Data Access Time
(Note 10)tDA12060100120SCLK to DOUT Valid
Delay (Note 10)tDO14080Bus Relinquish Time
(Note 10)tDH120ns
MAX11_ BM
MAX11_ _C/E= +25°C
MAX11_ BM
MAX11_ _C/E
CONDITIONSMAX11_ _C/E
MAX11_ _C/E
MAX11_ BM= +25°C
MAX11_ BM= +25°C
CLOAD= 50pF= +25°C
CLOAD= 50pF
MAX11_ _C/E= +25°C
MAX11_ BM= +25°C
MAX11_ _C/E/M
Low-Cost, 2-Channel, ±14-Bit Serial ADCMAX110 RELATIVE ACCURACY
(-VREF < VIN < VREF)
X110 toc01
VIN (V)
(%
-40°C ≤ TA ≤ +85°C
RANGE OF INL VALUES
(200 PIECE SAMPLE SIZE)
MAX110 RELATIVE ACCURACY
(-0.83 VREF < VIN < 0.83 VREF)
AX110 toc02
VIN (V)
(%
-40°C ≤ TA ≤ +85°C
RANGE OF INL VALUES
(200 PIECE SAMPLE SIZE)
AX110-TOC03
fOSC (MHz)
(%
÷1 MODE
÷2 MODE
÷ 4 MODE
VDD = 4.75V
VSS = -4.75V
TA = +85°C
MAX110 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY (fOSC) AX110-TOC04
TEMPERATURE (°C)
(%
MAX110 RELATIVE ACCURACY
vs. TEMPERATUREMAX110-TOC050.250.500.751.001.25
fOSC (MHz)
÷ 4 MODE
÷ 2 MODE
÷ 1 MODE
MAX110 POWER DISSIPATION vs.
OVERSAMPLING FREQUENCY (fOSC) VDD = 5.25V
VIN = 0V
TA = -40°C
__________________________________________Typical Operating Characteristics(MAX110, VDD= 5V, VSS= -5V, VREF+= 1.5V, VREF-= -1.5V, differential input (VIN+= -VIN-), fXCLK= 1MHz, ÷2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
____________________________Typical Operating Characteristics (continued)(MAX111, VDD= 5V, VREF+= 1.5V, VREF-= 0V, differential input (VIN+= -VIN-), fXCLK= 1MHz, ÷2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)
AX110-TOC08
fOSC (MHz)
(%
÷4 MODE
÷2 MODE
÷ 1 MODE
VDD = 4.75V
TA = +85°C
MAX111 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY (fOSC) AX110-TOC09
TEMPERATURE (°C)
(%
MAX111 RELATIVE ACCURACY
vs. TEMPERATUREMAX110-TOC100.250.500.751.001.25
fOSC (MHz)
(m
÷ 4 MODE
÷ 2 MODE
÷ 1 MODE
MAX111 POWER DISSIPATION vs.
OVERSAMPLING FREQUENCY (fOSC) VDD = 5.25V
VIN = 0V
TA = -40°C
MAX110-TOC6
VIN (V)
MAX111 RELATIVE ACCURACY
(-0.667VREF < VIN < 0.667VREF)
(%
AX110-TOC7
VIN (V)
MAX111 RELATIVE ACCURACY
(-VREF < VIN < VREF)
(%
Low-Cost, 2-Channel, ±14-Bit Serial ADC
_______________Detailed DescriptionThe MAX110/MAX111 ADC converts low-frequency
analog signals to a 16-bit serial digital output (14 data
bits, a sign bit, and an overrange bit) using a first-order
sigma-delta loop (Figure 1). The differential input volt-
age is internally connected to a precision voltage-to-
current converter. The resulting current is integrated
and applied to a comparator. The comparator output
then drives an up/down counter and a 1-bit DAC. When
the DAC output is fed back to the integrator input, the
sigma-delta loop is completed.
During a conversion, the comparator output is a VREF-to VREF+square wave; its duty cycle is proportional to
the magnitude of the differential input voltage applied
to theADC. The up/down counter clocks data in from
the comparator at the oversampling clock rate and
averages the pulse-width-modulated (PWM) square
wave to produce the conversion result. A 16-bit static
shift register stores the result at the end of the conver-
sion. Figure 2 shows the ADC waveforms for a differen-
tial analog input equal to 1/2 (VREF+- VREF-). The
resulting comparator and 1-bit DAC outputs are high
for seven cycles and low for three cycles of the over-
sampling clock.
Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
is attenuated. The more clock cycles allowed during
each conversion, the greater the noise attenuation (see
Programming Conversion Time).
______________________________________________________________Pin DescriptionClock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input
when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = VDD. XCLK
must be connected to VDDor GND through a resistor (1MΩor less) when RC OSC
mode is selected.
XCLK8
Serial Clock Input. TTL/CMOS-compatible clock input for serial-interface data I/O.SCLK9
Busy Output. Goes low at conversion start, and returns high at end of conversion.BUSY10
Positive Power-Supply Input—connect to +5VVDD6
RC Select Input. Connect to GND to select external clock mode. Connect to VDDto
select RC OSC mode. XCLK must be connected to VDDor GND through a resistor
(1MΩor less) when RC OSC mode is selected.
RCSEL7
Positive Reference InputREF+3
Negative Reference InputREF-2
Channel 1 Positive Analog InputIN1+1
FUNCTIONNAME
SSOP
PIN
DIP/SOChip-Select Input. Pull this input low to perform a control-word-write/data-read opera-
tion. A conversion begins when CSreturns high, provided NO-OPis a 1. See the sec-
tion Using the MAX110/MAX111 with SPI, QSPI, and MICROWIRE Serial Interfaces.119
Serial Data Output. High-impedance when CSis high.DOUT1210
Serial Data Input. See Control Registersection.DIN1311
Digital GroundGND1612
MAX110 Negative Power-Supply Input—connect to -5VVSS
Channel 2 Negative Analog InputIN2-1814
Channel 2 Positive Analog InputIN2+1915
Channel 1 Negative Analog InputIN1-2016
No Connect—there is no internal connection to this pinN.C.4, 5, 14, 15—
MAX111 Analog GroundAGND1713
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Oversampling ClockXCLK internally connects to a clock-frequency divider
network, whose output is the ADC oversampling clock,
fOSC. This allows the selected clock source (internal RC
oscillator or external clock applied to XCLK) to be
divided by one, two, or four (see Clock Divider-Ratio
Control Bits).
Figure 3 shows the two methods for providing the over-
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to
XCLK (see Selecting the Oversampling Clock
Frequency).
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK
(Figure 1). Select RC-oscillator mode by connecting
RCSEL to VDD. This enables the internal oscillator and
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.
DIFFERENTIAL
ANALOG
INPUT
VREF+
DC LEVEL AT 1/2 VREF
VREF-REF+
VREF-
OUTPUT FROM
1-BIT DAC
OVERSAMPLING
CLOCK
MAX110
MAX111
Figure 2. ADC Waveforms During a Conversion
Figure 1. Functional Diagram
IN1+
IN+
IN-
INPUT
MUX
IN1-
IN2+
IN2-
REF+
REF-
INTEGRATOR
UP/DOWN
COUNTER-∫
DITHER
GENERATOR
SERIAL
SHIFT
REGISTER
DINSCLKCS1616
CONTROL
REGISTER
DOUT
BUSY
RCSEL
XCLK
OSC
TIMER + CONTROL
LOGIC + CLOCK GENERATOR
DIVIDER
NETWORK,
DIVIDE BY
1, 2, OR 4
OSCILLATOR
MAX110
MAX111
Low-Cost, 2-Channel, ±14-Bit Serial ADC
ADC OperationThe output data from the MAX110/MAX111 is arranged
in twos-complement format (Figures 4, 5). The sign bit
(POL) is shifted out first, followed by the overrange bit
(OR), and the 14 data bits (MSB first) (see Figure 6).
The MAX110 operates from ±5V power supplies and
converts low-frequency analog signals in the ±3V
range when using the maximum reference voltage of
VREF= 3V (VREF= VREF+- VREF-). Within the ±3V input
range, greater accuracy is obtained within ±2.5V (see
Electrical Characteristicsfor details). Note that a nega-
tive input voltage is defined as VIN-> VIN+. For the
MAX110, the absolute voltage at any analog input pin
must remain within the (VSS+ 2.25V) to (VDD- 2.25V)
range.
The MAX111 operates from a single +5V supply and
converts low-frequency differential analog signals in the
±1.5V range when using the maximum reference volt-
age of VREF= 1.5V. As indicated in the Electrical
Characteristics, greater accuracy is achieved within the
±1.2V range. The absolute voltage at any analog input
pin for the MAX111 must remain within 0V to VDD- 3.2V.
When VIN-> VIN+the input is interpreted as negative.
The overrange bit (OFL) is provided to sense when the
input voltage level has exceeded the reference voltage
level. The converter does not “saturate” until the input
voltage is typically 20% larger. The linearity is not guar-
anteed in this range. Note that the overrange bit works
properly if the reference voltage remains within the rec-
ommended voltage range (see Reference Inputs). If the
reference voltage exceeds the recommended input
range, the overrange bit may not operate properly.
Digital Interface—Starting a ConversionData is transferred into and out of the serial I/O shift
register by pulling CSlow and applying a serial clock
at SCLK. This fully static shift register allows SCLK to
range from DC to 2MHz. Output data from the ADC is
clocked out on SCLK’s falling edge and should be read
on SCLK’s rising edge. Input data to the ADC at DIN is
clocked in on SCLK’s rising edge. A new conversion
begins when CSreturns high, provided the MSB in the
input control word (NO-OP) is a 1 (see Using the
MAX110/MAX111 with MICROWIRE, SPI, and QSPI
Serial Interfaces). Figure 6 shows the detailed serial-
interface timing diagram.CSS
must remain high during the conversion(while
BUSYremains low). Bringing CSlow during the conver-
sion causes the ADC to stop converting, and may
result in erroneous output data.
Using the MAX110/MAX111 with SPI, QSPI, and
MICROWIRE Serial InterfacesFigure 7 shows the most common serial-interface con-
nections. The MAX110/MAX111 are compatible with
SPI, QSPI (CPHA = 0, CPOL = 0), and MICROWIRE
serial-interface standards.
XCLK
TTL/CMOS
RCSEL
GND
+5V
-5V (0V)
( ) ARE FOR MAX111.DDSS (AGND)
MAX110
MAX111
Figure 3b. Connection for Internal RC-Oscillator Mode—XCLK
connects to the internal RC oscillator. Note, the pull-up resistor
is not necessary if the internal oscillator is never shut down.
XCLK
RCSEL
1MΩ
GND
+5V
-5V (0V)
VDD
+5V
VSS (AGND)
MAX110
MAX111
( ) ARE FOR MAX111.
Figure 3a. Connection for External-Clock Mode
Low-Cost, 2-Channel, ±14-Bit Serial ADCsOUTPUT
CODE+OVERFLOW
TRANSITION
-OVERFLOW
TRANSITION
POLOFLD13...D0100 . . .000100 . . .001100 . . .000100 . . .010011 . . .111
VREF -1LSBINPUT VOLTAGE (LSBs) - VREF 011 . . .111011 . . .110011 . . .101011 . . .100
+OVERFLOW000 . . .001000 . . .001000 . . .000111 . . .111111 . . .110100 . . .011
-OVERFLOW
Figure 4. Differential Transfer Function
OUTPUT
CODEOVERFLOW
TRANSITIONPOLOFLD13...D0100 . . .000000 . . .001000 . . .000000 . . .010111 . . .111
VREF -1LSBINPUT VOLTAGE (LSBs)0123011 . . .111011 . . .110011 . . .101011 . . .100
+OVERFLOW000 . . .011
Figure 5. Unipolar Transfer Function
