MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsential analog input range is ±2.2V when using the internal • 117dB SNR at 1ksps referen ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCElectrical Characteristics(V = +3.0V to +3.6V, V = +2.7V to V , f = 24.576MHz, f = 16ksps, V = +2.5 ..
MAX11040KGUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsDRDYOUTAIN1+24-BIT DIGITALADC FILTERAIN1-● Power-Protection Relay Equipment REGISTERS A ..
MAX11044ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.70V to +5.25V, V = V = V = 0V, V = internal ..
MAX11045ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.70V to +5.25V, V = V = V = 0V, V = internal ..
MAX11045ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsFeaturesThe MAX11044/MAX11044B/MAX11045/MAX11045B/♦ 16-Bit ADC (MAX11044/MAX11044B/MAX11045/MAX1104 ..
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA+ ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3430ESA+T ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3440EESA ,15kV ESD-Protected / 60V Fault-Protected / 10Mbps / Fail-Safe RS-485/J1708 Transceivers
MAX3440EESA+ ,±15kV ESD-Protected, ±60V Fault-Protected, 10Mbps, Fail-Safe RS-485/J1708 Transceivers
MAX11040GUU+-MAX11040KGUU+
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
General DescriptionThe MAX11040K/MAX11060 are 24-/16-bit, 4-channel,
simultaneous-sampling, sigma-delta analog-to-digital
converters (ADCs). The devices allow simultaneous sam-
pling of as many as 32 channels using a built-in cascade
feature to synchronize as many as eight devices. The
serial interface of the devices allows reading data from
all the cascaded devices using a single command. Four
modulators simultaneously convert each fully differential
analog input with a programmable data output rate rang-
ing from 0.25ksps to 64ksps. The devices achieve 106dB
SNR at 16ksps and 117dB SNR at 1ksps (MAX11040K).
The devices operate from a single +3V supply. The differ-
ential analog input range is ±2.2V when using the internal
reference; an external reference is optional. Each input
is overvoltage protected up to ±6V without damage. The
devices use an internal crystal oscillator or an external
source for clock.
The devices are compatible with SPI, QSPI™,
MICROWIRE®, and DSP-compatible 4-wire serial inter-
faces. An on-board interface logic allows one serial
interface (with a single chip select) to control up to eight
cascaded devices or 32 simultaneous sampling analog
input channels.
The devices are ideally suited for power-management
systems. Each channel includes an adjustable sampling
phase enabling internal compensation for phase shift due
to external dividers, transformers, or filters at the inputs.
The output data rate is adjustable with a 0.065% resolu-
tion (at 16ksps or below) to track the varying frequency of
a periodic input. A SYNC input allows periodic alignment
of the conversion timing of multiple devices with a remote
timing source.
The devices are available in a 38-pin TSSOP package spec-
ified over the -40°C to +105°C industrial temperature range.
Applications●Power-Protection Relay Equipment●Multiphase Power Systems●Industrial Data-Acquisition Systems●Medical Instrumentation
Beneits and Features●Feature Set Ideal for Energy Measurement SystemsFour Fully Differential Simultaneously Sampled
ChannelsCascadable for Up to 32 Channels of Simultaneous
SamplingProgrammable Sampling Phase for Phase Shift
Compensation▫0 to 333μs in 1.33μs StepsProgrammable Output Data Rate with 0.065%
Resolution●Excellent Performance for High-Accuracy
Measurement Applications117dB SNR at 1ksps 106dB SNR at 16ksps0.25% Error Over a 1000:1 Dynamic Range±2.2V Full-Scale Input Range●Single-Supply Operation and Protected Inputs for
Design Simplicity and Robustness3.0V to 3.6V Analog Supply Voltage2.7V to VAVDD Digital Supply Voltage±6V Overvoltage Protected Inputs-40˚C to +105˚C Operating Temperature Range
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX11040K.related.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
QSPI is a trademark of Motorola, Inc.
PARTTEMP RANGEPIN-PACKAGE
MAX11040KGUU+-40°C to +105°C38 TSSOP
MAX11060GUU+-40°C to +105°C38 TSSOP
MAX11040K24-BIT
ADC
DIGITAL
FILTER
2.5V
REFERENCE
CRYSTAL
OSCILLATORREFIO
AIN3+
AIN3-
REF3
24-BIT
ADC
DIGITAL
FILTER
AIN2+
AIN2-
REF2
24-BIT
ADC
DIGITAL
FILTER
AIN1+
AIN1-
REF1
24-BIT
ADC
DIGITAL
FILTER
AIN0+
AIN0-
REF0
REGISTERS AND
DIGITAL
CONTROL
SERIAL
INTERFACE
DOUT
DIN
SCLK
CASCOUT
CASCIN
DRDYOUT
DRDYIN
SYNC
FAULTOVRFLW
CLKOUTXOUTDGNDAGNDXIN
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Functional Diagram
Ordering Information
EVALUATION KIT AVAILABLE
AVDD to AGND ........................................................-0.3V to +4V
DVDD to DGND......................................-0.3V to (VAVDD + 0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
DIN, SCLK, CS, XIN, SYNC, DRDYIN,
CASCIN to DGND............................-0.3V to (VDVDD + 0.3V)
DOUT, DRDYOUT, CASCOUT, CLKOUT,
XOUT to DGND................................-0.3V to (VDVDD + 0.3V)
FAULT, OVRFLW to DGND ...................................-0.3V to +4.0V
AIN_+ to AIN_- ......................................................-6.0V to +6.0V
AIN_ _ to AGND (VAVDD ≥ 3V, VDVDD ≥ 2.7V, FAULTDIS = 0, SHDN = 0, fXIN CLOCK ≥ 20MHz)...................-6.0V to +6.0V
AIN_ _ to AGND (VAVDD < 3V or VDVDD < 2.7V or FAULTDIS = 1 or SHDN = 1 or fXIN CLOCK < 20MHz)..............-3.5V to +3.5V
REFIO, REF_ to AGND..........................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
TSSOP (derated 13.7mW/°C above +70°C)..............1096mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)ResolutionMAX11040K24BitsMAX1106016
Differential NonlinearityDNL24-bit no missing code (MAX11040K);
16-bit no missing code (MAX11060)0.1LSB
Integral Nonlinearity (Note 3)INL
TA = +25°C and +105°C (MAX11040K)0.0010.004
%FSTA = -40°C (MAX11040K)0.006
MAX110600.001
Offset Error -1+1mV
Gain Error (Note 4)-1+1%FS
Offset-Error Drift (Note 5)0.5ppm/°C
Gain-Error Drift (Note 5)1ppm/°C
Change in Gain Error vs. fOUTfOUT = 0.25ksps to 64ksps< 0.025% FS
Channel-to-Channel Gain Matching0.03% FS
DYNAMIC SPECIFICATIONS (62.5Hz sine-wave input, 2.17VP-P)Signal-to-Noise RatioSNR(Note 6) (MAX11040K)103106dB(Note 6) (MAX11060)94.5
Total Harmonic DistortionTHD
TA = +25°C and +105°C (MAX11040K)-94TA = -40°C (MAX11040K)-90
MAX11060-106
Signal-to-Noise Plus DistortionSINAD
TA = +25°C and +105°C (MAX11040K)9398TA = -40°C (MAX11040K)89
MAX1106094
Spurious-Free Dynamic RangeSFDR
TA = +25°C and +105°C (MAX11040K)94100TA = -40°C (MAX11040K)89
MAX11060100
Relative Accuracy (Note 7)0.1%FS input (MAX11040K)0.25%
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBandwidth-3dB3.4kHz
Latency(Note 8)374µs
Passband FlatnessFrom DC to 1.4kHz< 0.1dB
Amplitude-Dependent Phase ErrorFS vs. 0.1% FS< 0.010.12Degrees
Channel-to-Channel Phase
Matching0.0001Degrees
Phase-Error Drift0.001Degrees
Channel-to-Channel Isolation-130dB
Common-Mode RejectionCMRR109dB
ANALOG INPUTS (AIN_+, AIN_-)Differential FS Input RangeVINVAIN_+ - VAIN_--2.2+2.2V
Single-Ended Positive Input RangeVAIN_+Referenced to AGND-2.2+2.2V
Single-Ended Negative Input RangeVAIN_-Referenced to AGND-2.2+2.2V
Positive Fault ThresholdVPFTVAIN_+ or VAIN_- (Note 9)2.252.65V
Negative Fault ThresholdVNFTVAIN_+ or VAIN_- (Note 9)-2.65-2.25V
Fault Pin Response Time2.5µs
Input ImpedanceZINVNFT ≤ VIN ≤ VPFT130kΩVIN < VNFT or VIN > VPFT> 0.5
DC Leakage CurrentIINVAIN_+ = VAIN_-±0.01±1µA
Input Sampling RatefSfS = fXINCLOCK/83.072Msps
Input Sampling Capacitance4.0pF
INTERNAL REFERENCE REFIO Output VoltageVREFTA = TMAX2.42.52.6V
REFIO Output Resistance1kΩ
REFIO Temp Drift50ppm/°C
REFIO Long-Term Stability200ppm/
1000hr
REFIO Output Noise3µVRMS
REFIO Power-Supply RejectionPSRR75dB
EXTERNAL REFERENCEREFIO Input VoltageVREF2.32.7V
REFIO Sink Current200µA
REFIO Source Current200µA
REFIO Input Capacitance10pF
CRYSTAL OSCILLATOR (XIN, XOUT)Tested Resonant Frequency(Note 10)24.576MHz
Maximum Crystal ESR30Ω
Oscillator Startup Time< 2ms
Oscillator StabilityVDVDD = 3.3V, excluding crystal10ppm/°C
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Electrical Characteristics (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN)Input Low VoltageVIL0.3 x
VDVDDV
Input High VoltageVIH0.7 x
VDVDDV
Input HysteresisVHYSVDVDD = 3.0V100mV
Input Leakage CurrentIL±0.01±1µA
Input CapacitanceCIN15pF
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)Output Low VoltageVOLISINK = 5mA0.15 x
VDVDDV
Output High VoltageVOHISOURCE = 1mA0.85 x
VDVDDV
Three-State Leakage CurrentILT±1µA
Three-State CapacitanceCOUT15pF
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT)Output Low VoltageVOLISINK = 5mA0.15 x
VDVDDV
Output High VoltageVOHInternal pullup only0.85 x
VDVDDV
Internal Pullup Resistance30kΩ
POWER REQUIREMENTSAnalog Supply VoltageAVDD3.03.6V
Digital Supply VoltageDVDD2.7VAVDDV
Analog Supply Current (Note 11)IAVDDNormal operation2535mA
Shutdown and fXINCLOCK = 0Hz0.15µA
Digital Supply Current (Note 11)IDVDDNormal operation1115mA
Shutdown and fXINCLOCK = 0Hz0.3µA
AC Positive-Supply Rejection VAVDD = 3.3V + 100mVP-P at 1kHz70dB
DC Positive-Supply Rejection VAVDD = VDVDD = 3.0V to 3.6V75dB
ESD PROTECTIONAll PinsESDHuman Body Model2.5kV
TIMING CHARACTERISTICS (Figures 7–10)SCLK Clock PeriodtSCP50ns
SCLK Pulse Width (High and Low)tPW20ns
DIN or CS to SCLK Fall SetuptSU10ns
SCLK Fall to DIN HoldtHD0ns
SCLK Rise to CS RisetCSH10ns
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Electrical Characteristics (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate, sample instant delay, and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individu-
al AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK Rise to DOUT ValidtDOTCLOAD = 30pF1.51016nsCLOAD = 100pF< 16
CS Fall to DOUT EnabletDOECLOAD = 30pF0.320ns
CS Rise to DOUT DisabletDODCLOAD = 30pF0.716ns
CS Pulse WidthtCSW16ns
CASCIN-to-SCLK Rise SetuptSC16ns
SCLK Rise to CASCOUT ValidtCOTCLOAD = 100pF20ns
SYNC Pulse Width tSYN2XIN Clock
Cycles
XIN Clock Pulse WidthtXPW16ns
DRDYIN to DRDYOUTtDRDYCLOAD = 30pF20ns
XIN Clock to DRDYOUT DelaytXDRDYDRDYIN = DGND40ns
XIN Clock PeriodtXP40ns
XIN Clock to SYNC SetuptSS(Note 12)16ns
SYNC to XIN Clock HoldtHS(Note 12)5ns
XIN-to-CLKOUT DelaytXCD40ns
Power-On Reset Delay (Note 13)< 1ms
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Electrical Characteristics (continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
HISTOGRAM OF RMS AMPLITUDE
AT 0.1% FSMAX11040K/11060 toc02
RMS AMPLITUDE (% FS)
INSTANCES
MAXIMUM EXPECTED ERROR OF CALCULATED
RMS AMPLITUDE vs. INPUT AMPLITUDE
MAX11040K/11060 toc03
INPUT AMPLITUDE (% FS)
MAXIMUM EXPECTED ERROR (%)10.1
1 MILLION 62.5Hz CYCLES
SIGNAL-TO-NOISE RATIO
vs. OUTPUT DATA RATEMAX11040K/11060 toc04
OUTPUT DATA RATE (ksps)
SNR (dB)1
FFT vs. FREQUENCY AT FULL SCALE
MAX11040K/11060 toc05
FREQUENCY (Hz)
AMPLITUDE (dB FS)
60Hz SINE-WAVE INPUT
FFT vs. FREQUENCY AT 0.1% FULL SCALEMAX11040K/11060 toc06
FREQUENCY (Hz)
AMPLITUDE (dB FS)
60Hz SINE-WAVE INPUT
RMS AMPLITUDE
vs. INPUT FREQUENCYMAX11040K/11060 toc07
RMS AMPLITUDE (dB)
-0.510,000
INL vs. DIFFERENTIAL INPUT VOLTAGEMAX11040K/11060 toc01
DIFFERENTIAL INPUT VOLTAGE (V)
INL (% FS)
RMS AMPLITUDE GAIN ERROR
vs. OUTPUT DATA RATE
MAX11040K/11060 toc08
RMS AMPLITUDE GAIN ERROR (%)
10,0001000
100100,000
RMS AMPLITUDE
vs. SOURCE RESISTANCEMAX11040K/11060 toc09
RMS AMPLITUDE (dB)
10,0001000100100,000
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Characteristics (MAX11040K)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCYMAX11040K/11060 toc10
INPUT FREQUENCY (Hz)
THD (dB)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11040K/11060 toc11
SUPPLY VOLTAGE (V)
OFFSET ERROR (% FSR)
AVDD = DVDD
OFFSET ERROR vs. TEMPERATUREMAX11040K/11060 toc12
TEMPERATURE (°C)
OFFSET ERROR (% FSR)4718-11
AVDD = DVDD
GAIN ERROR vs. SUPPLY VOLTAGEMAX11040K/11060 toc13
SUPPLY VOLTAGE (V)
GAIN ERROR (% FSR)
AVDD = DVDD
GAIN ERROR
vs. TEMPERATUREMAX11040K/11060 toc14
TEMPERATURE (°C)
GAIN ERROR (% FSR)3510-15
VAVDD = VDVDD = 3.3V
GAIN ERROR DRIFTMAX11040K/11060 toc15
TIME (hr)
GAIN ERROR (%)
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Characteristics (MAX11040K) ( continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 =
CREF3 = 1μF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATUREMAX11040K/11060 toc17
TEMPERATURE (°C)
SUPPLY CURRENT (mA)4718-11
VAVDD = VDVDD = 3.3V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX11040K/11060 toc18
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
AVDD = DVDD
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATUREMAX11040K/11060 toc19
TEMPERATURE (°C)
SUPPLY CURRENT (nA)4718-11
VAVDD = VDVDD = 3.6V
IAVDD
IDVDD
CRYSTAL OSCILLATOR STARTUP TIMEMAX11040K/11060 toc20
40µs/divt
CLKOUT
500mV/div
SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX11040K/11060 toc16
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
AVDD = DVDD
IAVDD
IDVDD
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Characteristics (MAX11040K) ( continued)
PINNAMEFUNCTIONAIN0-Negative Analog Input Channel 0AIN0+Positive Analog Input Channel 0REF0ADC0 Buffered Reference Voltage. Bypass REF0 with a 1µF capacitor to AGND.
4, 8, 10,
29, 31, 35 AGNDAnalog Ground AIN1-Negative Analog Input Channel 1 AIN1+Positive Analog Input Channel 1 REF1ADC1 Buffered Reference Voltage. Bypass REF1 with a 1µF capacitor to AGND.REFIO
Reference Voltage Output/Input. Reference voltage for analog-to-digital conversion. In internal reference
mode, the reference buffer provides a +2.5V nominal output. In external reference mode, overdrive REFIO
with an external reference between 2.3V to 2.7V. Bypass REFIO with a 1µF capacitor to AGND.
AIN2-
AIN2+
REF2
AGNDAGND
REF0
AIN0+
AIN0-
TOP VIEW
MAX11040K
MAX11060AIN3-
AIN3+
REF3REF1
AIN1+8AGNDAGND9AVDDREFIO10AGNDAGND11DGNDDGND12DVDDDVDD13XINCASCIN14XOUTCASCOUT
AIN1-15SYNCCS16DRDYINSCLK17DRDYOUTDIN18CLKOUTDOUT19OVRFLWFAULT
TSSOPMAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Pin Description
Pin Coniguration
PINNAMEFUNCTION11, 28DGNDDigital Ground
12, 27DVDDPositive Digital Supply Voltage. Bypass each DVDD to DGND with a 1µF capacitor in parallel with a
0.01µF capacitor as close as possible to the device. CASCIN
Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the
device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the
requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is
issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy
chaining multiple devices. See the Multiple Device Connection section for connection recommendations. CASCOUT
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal
the next device in the daisy-chain to begin transferring data on the next byte. CASCOUT changes after the
rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See the
Multiple Device Connection section.CS
Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT
for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a
high-impedance state. SCLKSerial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the rising edge of SCLK. SCLK must idle high (CPOL = 1).DINSerial Data Input. Data at DIN is clocked in on the falling edge of SCLK. DOUT
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by
a falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK. FAULT
Active-Low Overvoltage Fault Indicator Output. FAULT goes low when any analog input goes outside the
fault threshold range (between VPFT and VNFT). The FAULT output is open drain with a 30kΩ internal pullup
resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.OVRFLW
Active-Low Channel Data Overlow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input channels
or when FAULT goes low. The OVRFLW output is open drain with a 30kΩ internal pullup resistor, allowing
wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section. CLKOUTBuffered Clock Output. When the XTALEN bit in the coniguration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Pin Description (continued)
PINNAMEFUNCTIONDRDYOUT
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.DRDYIN
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.SYNC
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.XOUT
Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator. Leave XOUT unconnected when driving with an external frequency. See
the Crystal Oscillator section.XIN
Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See
the Crystal Oscillator section.AVDDPositive Analog Supply Voltage. Bypass to AGND with a 1µF capacitor in parallel with a 0.01µF capacitor
as close as possible to the device.REF3ADC3 Buffered Reference Voltage. Bypass with a 1µF capacitor to AGND.AIN3+Positive Analog Input Channel 3AIN3-Negative Analog Input Channel 3 REF2ADC2 Buffered Reference Voltage. Bypass with a 1µF capacitor to AGND.AIN2+Positive Analog Input Channel 2AIN2-Negative Analog Input Channel 2
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Pin Description (continued)
Detailed DescriptionThe MAX11040K/MAX11060 are 24-/16-bit, simultane-
ous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining of
the serial interface across multiple (up to eight) devices.
The serial interface of the set of synchronized devices
behaves as one device. Each channel includes a dif-
ferential analog input, a sigma-delta modulator, a digital
decimation filter, an independent programmable sampling
delay, and a buffered reference signal from the internal
or an external reference. The device contains an inter-
nal crystal oscillator. The output data rate, the effective
sample rate of the ADC, is software programmable.
The devices operate from a single 3.0V to 3.6V analog
supply and a 2.7V to VAVDD digital supply. The 4-wire
serial interface is SPI/QSPI/MICROWIRE and DSP com-
patible.
ADC ModulatorEach channel of the devices performs analog-to-digital
conversion on its input using a dedicated switched-
capacitor sigma-delta modulator. The modulator converts
the input signal into low-resolution digital data for which
the average value represents the digitized signal informa-
tion at 3.072Msps for a 24.576MHz XIN clock. This data
stream is then presented to the digital filter for processing
to remove the high-frequency noise that creates a high-
resolution 24-/16-bit output data stream.
The input sampling network of the analog input consists of
a pair of 4pF capacitors (CSAMPLE), the bottom plates of
which are connected to AIN_+ and AIN_- during the track
phase and then shorted together during the hold phase
(see Figure 1). The internal switches have a total series resistance of 400Ω. Given a 24.576MHz XIN clock, the
switching frequency is 3.072MHz. The sampling phase
lasts for 120ns.
Figure 1. Simplified Track/Hold Stage
MAX11040K
MAX11060CSAMPLE+
HOLDTO ADC
RONRON
CSAMPLE-
TRACK
TRACK
AIN_+
AIN_-
AVDD/2
MAX11040K
MAX11060AIN0+
AIN0-
1µF
AIN0-
AIN0+
24.576MHz
REF0
AIN1+
AIN1-
1µF
AIN1-
AIN1+
REF1
AIN2+
AIN2-
1µF
AIN2-
AIN2+
REF2
AIN3+
AIN3-
1µF
AIN3-
AIN3+
REF3
1µF
REFIO
0.01µF
1µF3.3V
AVDD
0.01µF
1µF3.3V
DVDD20pF
20pF
XIN
XOUT
CLKOUT
CASCOUT
CASCIN
DOUT
DRDYOUT
DIN
SCLK
SYNC
DRDYIN
FAULT
OVRFLW
MICROCONTROLLER
OR DSP
AGNDDGND
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Typical Operating Circuit
Digital FilterThe devices contain an on-chip digital lowpass filter that
processes the data stream from each modulator and gen-
erates the high-resolution output data. The lowpass filter
frequency response is determined by the programmable
output data rate. At the nominal 16ksps output data rate,
the -3dB bandwidth of the filter is 3.4kHz. The passband
flatness is better than ±0.1dB from 0 to 1.74kHz. The
notches are located at 5.75kHz and 7.195kHz. These
frequencies scale linearly with the output data rate. See
Figure 2 and Table 1 for the frequency response at differ-
ent data rates.
Since the transfer function of a digital filter is repeatable
and predictable, it is possible to correct for frequency-
dependent attenuation in downstream software. See
the Compensating for the Rolloff of the Digital Filter in
a Typical FFT Analysis section. The transfer function is
defined by the following equation:)
AINSAMPLE
SAMPLEAIN
AINXINCLOCKXINCLOCK
AINfsinfGain(f)fsinf
FIR_Gain(f)×π×=×π××
where:
Gain is the filter gain.
fAIN is the analog input frequency.
fSAMPLE is the programmed output data rate, nominally
16kHz.
fXINCLOCK is the clock frequency at XIN, nominally
24.576MHz.
FIR_Gain (fAIN) is the normalized gain of the FIR fil-
ter with the following filter coefficients, as a function of
the analog input frequency fAIN. These coefficients are
applied at the output data rate:+ 0.022- 0.074- 0.036+ 0.312+ 0.552+ 0.312- 0.036- 0.074+ 0.022
Figure 2. Digital Filter Response
Table 1. Bandwidth vs. Output Data Rate
OUTPUT DATA RATE (ksps)-3dB BANDWIDTH (kHz)-0.1dB BANDWIDTH (kHz)0.50.110.050.210.110.420.220.850.431.690.872.111.092.541.31
3.381.746.783.4813.56.96
MAX11040K fig02
fAIN/fSAMPLE
GAIN (dB)
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Modulator ClockThe modulator clock is created by dividing the frequency
at the XIN input by a factor of 8. The XIN input is driven
either directly by an external clock or by the on-chip crys-
tal oscillator.
Crystal OscillatorThe on-chip oscillator requires an external crystal (or res-
onator) with a 24.576MHz operating frequency connected
between XIN and XOUT, as shown in Figure 3. As in any
crystal-based oscillator circuit, the oscillator frequency
is sensitive to the capacitive load (CL). CL is the capaci-
tance that the crystal needs from the oscillator circuit and
not the capacitance of the crystal. The input capacitance
across XIN and XOUT is 1.5pF.
Choose a crystal with a 24.576MHz oscillation frequency and an ESR less than 30Ω, such as the MP35 from RXD
Technologies. See Figure 3 for the block diagram of the crystal oscillator. Set XTALEN = 1 in the configuration reg-
ister to enable the crystal oscillator. The CLKOUT output
provides a buffered version of the clock that is capable of
driving eight devices, allowing synchronized operation from
a single crystal. See the Multiple Device Synchronization
section in the Applications Information section.
External ClockTo use an external clock, set XTALEN = 0 in the
Configuration register and connect an external clock
source (20MHz to 25MHz) to XIN. CLKOUT becomes
high impedance.
Analog Input Overvoltage and Fault ProtectionThe full-scale differential input range of the devices is
±0.88VREF. The converter accurately represents any
input for which the positive and negative analog inputs are
separated by a magnitude of less than 0.88VREF.
The device includes special circuitry that protects it
against voltages on the analog inputs up to ±6V. Setting FAULTDIS = 1 disables the protection circuitry.
There are two mechanisms of overvoltage detection and
protection: full-scale overflow and overvoltage fault. Full-
scale overflow occurs if the magnitude of the applied
input voltage on any one or more channels is greater than
0.88VREF. In this case, the digital output is clipped to pos-
itive or negative full scale and the OVRFLW flag goes low.
Overvoltage fault occurs if the magnitude of an applied
input voltage on any one or more channels goes outside
the fault-detection thresholds. The reaction to an overvolt-
age fault is dependent on whether the fault-protection cir-
cuitry is enabled. If enabled, the input-protection circuits
engage and the FAULT flag goes low. A full-scale overflow
or an overvoltage fault condition on any one channel does
not affect the output data for the other channels.
The input protection circuits allow up to ±6V relative to
AGND on each input, and up to ±6V differentially between
AIN+ and AIN-, without damaging the devices only if the
following conditions are satisfied: power is applied, the
devices are not in shutdown mode, a clock frequency of at least 20MHz is available at XIN, and FAULTDIS = 0. The
analog inputs allow up to ±3.5V relative to AGND when
either devices are placed in shutdown mode, the clock stops, or FAULTDIS = 1.
During an overvoltage fault condition, the impedance between AIN_+ and AIN_- reduces to as low as 0.5kΩ.
The output structure and cascading features of FAULT
and OVRFLW are discussed in the Multiple Device Digital
Interface section.
Analog Input Overlow Detection and Recovery (OVRFLW)The OVRFLW flag is set based on the ADC conversion
result. When the applied voltage on one or more analog
inputs goes outside the positive or negative full scale
(±0.88VREF), OVRFLW asserts after a delay defined
by the latency of the converter, coincident with the
DRDYOUT of the full-scale clamped conversion result
(see Figure 4). The specifics of the latency are discussed
earlier in the data sheet in the Latency section.Figure 3. Crystal Oscillator Input
MAX11040K
MAX1106024.576MHz
20pF
20pF
XIN
XOUT
24.576MHz
OSCILLATOR
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
When the analog input voltage changes between the ADC
full scale and the fault threshold faster than the latency of
the converter, OVRFLW goes low with the FAULT output.
OVRFLW remains invalid until a valid clock frequency is
available at XIN.
Overvoltage-Fault Detection and Recovery (FAULT)With overvoltage-fault protection enabled (FAULTDIS = 0), FAULT immediately transitions from a high to low
when any of the analog inputs go outside the voltage
range bounded by the fault-detection thresholds VPFT
and VNFT.
Once the analog inputs return back within the fault thresh-
olds, the FAULT interrupt output goes high after a delay
called the fault-recovery time. The fault-recovery time is:
20 x tDOUT < fault-recovery time < 25 x tDOUT
where tDOUT is the data output period determined by
fXINCLOCK and the selected output data rate.
In the event the analog input voltage changes between
the ADC full scale and the fault threshold faster than
the latency of the converter, the ADC conversion result
prematurely jumps to the full-scale value when a fault is
detected (see Detection Discontinuity in Figure 4). During
a fault condition and the subsequent fault-recovery time,
the ADC conversion result remains at full scale. This cre-
ates a discontinuity in the digital conversion result only if
the fault recovery time is greater than the latency plus the
time that the input changes between the fault threshold
and the ADC full scale (see Recovery Discontinuity in
Figure 4). Neither of these steps occur if the fault-protec-tion circuitry is disabled (FAULTDIS = 1), or if the input
is slow relative to the above descriptions (see Figure 5).
For data rates faster than 32ksps (FSAMPC = 111), the converter output may contain invalid data for up to 188μs
after FAULT returns high. To prevent this behavior, disable
the overvoltage-fault protection by setting the FAULTDIS
bit in the configuration register to 1 when using FSAMPC = 111, and limit the analog input swing to ±3.5V.
|AIN+ - AIN-|
LATENCY
LATENCYLATENCY
DETECTION
DISCONTINUITYRECOVERY
DISCONTINUITY
FULL SCALE
(|0.88VREF|)
FAULT-DETECTION
THRESHOLD
(VPFT OR |VNFT|)
RECOVERY TIME
LATENCY
FAULT
OVRFLW
DIGITAL OUTPUT
DATA AT DOUT
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ReferenceThe devices operate with either a +2.5V internal band-
gap reference or an external reference source between
+2.3V and +2.7V applied at REFIO. Bypass REFIO and each REF_ to AGND with a 1μF capacitor. The reference
voltage sets the positive and negative full-scale voltage
according to the following formula:
±FS = ±0.88 VREFIO
The reference voltage at REFIO (external or internal) is
individually buffered to generate the reference voltages at
REF0 to REF3 (see Figure 6.) These independent buffers
minimize the potential for crosstalk between each of the
internal ADCs.
Serial InterfaceThe devices’ interface is fully compatible with SPI/DSP
standard serial interfaces (compatible with SPI modes CPOL = 1, CPHA = 0). The serial interface provides
access to four on-chip registers: Sampling Instant Control
register (32 bits), Data Rate Control register (16 bits),
Configuration register (8 bits), and Data register (96 bits).
All serial-interface commands begin with a command
byte, which addresses a specific register, followed by
register addressed and the number of devices cascaded
(see Figures 7, 8, and the Registers section).
The serial interface consists of eight signals: CS,
SCLK, DIN, DOUT, CASCIN, CASCOUT, DRDYIN,
and DRDYOUT. CASCIN, CASCOUT, DRDYIN, and
DRDYOUT are used for daisy chaining multiple devices
together. See the Multiple Device Connection section for
Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery
Figure 6. REFIO Input
|AIN+ - AIN-|
FULL SCALE
(|0.88VREF|)
FAULT-DETECTION
THRESHOLD
(VPFT OR |VNFT|)
FAULT
OVRFLW
RECOVERY TIME
LATENCY
LATENCY
LATENCY
DIGITAL OUTPUT
DATA AT DOUT
LATENCY
+2.5V
REFERENCEREFIO
REF3
REF2
REF1
REF0
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
and DRDYOUT. For single-device applications, connect
CASCIN and DRDYIN to DGND and drive CS low to
transfer data in and out of the devices. With DRDYIN low,
a falling edge at the data-ready signal output (DRDYOUT)
indicates that new conversion results are available for
reading in the 96-bit data register. A falling edge on SCLK
clocks in data at DIN. Data at DOUT changes on the
rising edge of SCLK and is valid on the falling edge of
SCLK. DIN and DOUT are transferred MSB first. Drive CS
high to disable the interface and place DOUT in a high-
impedance state.
An interface operation with the devices takes effect on
the last rising edge of SCLK. If CS goes high before the
complete transfer, the write is ignored. Every data trans-
fer is initiated by the command byte. The command byte
consists of an R/W bit and 7 address bits (see Table 2.)
Figures 7 and 8 show the timing for read and write opera-
tions, respectively.
Figure 7. General Read-Operation Timing Diagram
tCSW
SCLK
DIN
DOUT
DRDYIN
HIGH-ZHIGH-ZB7B6B5B4B3B2B1B0
tSUtSCP
tDCD
tCSH1tSU
tDOE
tDRDY
DATA READY
tHD
COMMAND ADDRESS
tDOT
tPW
tPW
R/WA6A5A3A2A1A0A4
DATA LENGTH (NUMBER OF BYTES) DEPENDS
ON THE REGISTER BEING READ (SEE TABLE 2)
DRDYOUT
DOUT
HIGH-ZHIGH-Z
tCSW
tSU
tHD
tSU
tPWtSCP
tPW
tCSH1
DIN
SCLKA5A3A2A1A0B7B6B5B4B3B2B1R/WB0
DATA LENGTH (NUMBER OF BYTES) DEPENDS ON
THE REGISTER BEING WRITTEN (SEE TABLE 2)
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
RegistersThe devices include four registers accessible by 7 com-
mand bytes. The command bytes provide read and write
access to the Data Rate Control register, the Sampling
Instant Control register, and the Configuration regis-
ter, and read access to the Data register. See Table 2.
Figure 9 shows the CASCIN and CASOUT timing dia-
gram. Figure 10 is the XIN clock, CLKOUT, SYNC, and
DRDYOUT timing diagram.
Figure 9. CASCIN and CASCOUT Timing Diagram
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing
Diagram
*All data lengths are proportional to the number of cascaded
devices except for reads and writes to the Data Rate Control
register. When accessing the Data Rate Control register, the
data length is fixed at 16 bits. These 16 bits are automatically
written to all cascaded devices.
**n is the total number of cascaded devices.
Table 2. Command Bytes
R/WADDRESS
[A6:A0]
DATA LENGTH*FUNCTION100000032 x n** bits Write Sampling Instant
Control Register100000032 x n bits Read Sampling Instant
Control Register101000016 bits Write Data-Rate Control
Register101000016 bits Read Data-Rate Control
Register11000008 x n bits Write Coniguration
Register11000008 x n bits Read Coniguration
Register111000096 x n bits Read Data Register
SCLK
CASCOUT
(DEVICE n)
CASCIN
(DEVICE n+1)
tSC
tCOT
XIN CLOCK
SYNC
CLKOUT
DRDYOUT
tXPtXPW
tXCD
tSS
tHS
tXDRDYtSYN
MAX11040K/MAX1106024-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
