MAX11014BGTM+ ,Automatic RF MESFET Amplifier Drain-Current ControllersApplicationsto +5.25V digital supply (1.5mA typical supply current),and a -4.5V to -5.5V negative s ..
MAX1101CWG ,Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGAELECTRICAL CHARACTERISTICS(V = V = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µ ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsential analog input range is ±2.2V when using the internal • 117dB SNR at 1ksps referen ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCElectrical Characteristics(V = +3.0V to +3.6V, V = +2.7V to V , f = 24.576MHz, f = 16ksps, V = +2.5 ..
MAX11040KGUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsDRDYOUTAIN1+24-BIT DIGITALADC FILTERAIN1-● Power-Protection Relay Equipment REGISTERS A ..
MAX11044ETN+ ,4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +2.70V to +5.25V, V = V = V = 0V, V = internal ..
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA ,80V Fault-Protected / Fail-Safe / 1/4-Unit Load / #.3V RS-485 Transceiver
MAX3430ESA+ ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3430ESA+T ,±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V RS-485 Transceiver
MAX3440EESA ,15kV ESD-Protected / 60V Fault-Protected / 10Mbps / Fail-Safe RS-485/J1708 Transceivers
MAX3440EESA+ ,±15kV ESD-Protected, ±60V Fault-Protected, 10Mbps, Fail-Safe RS-485/J1708 Transceivers
MAX11014BGTM+
Automatic RF MESFET Amplifier Drain-Current Controllers
General DescriptionThe MAX11014/MAX11015 set and control bias condi-
tions for dual MESFET power devices found in point-to-
point communication and other microwave base
stations. The MAX11014 integrates complete dual ana-
log closed-loop drain-current controllers for Class A
MESFET amplifier operation, while the MAX11015 tar-
gets Class AB operation. Both devices integrate SRAM
lookup tables (LUTs) that can be used to store temper-
ature and drain-current compensation data.
Each device includes dual high-side current-sense
amplifiers to monitor the MESFET drain currents through
the voltage drop across the sense resistors in the 0 to
625mV range. External diode-connected transistors mon-
itor the MESFET temperatures while an internal tempera-
ture sensor measures the local die temperature of the
MAX11014/MAX11015. The internal DAC sets the volt-
ages across the current-sense resistors by controlling
the GATE voltages. The internal 12-bit SAR ADC digitizes
internal and external temperature, internal DAC voltages,
current-sense amplifier voltages, and external GATE volt-
ages. Two of the 11 ADC channels are available as gen-
eral-purpose analog inputs for analog system monitoring.
The MAX11014’s gate-drive amplifier functions as an
integrator for the Class A drain-current control loop
while the MAX11015’s gate-drive amplifier functions
with a gain of -2 for Class AB applications. The current-
limited gate-drive amplifier can be fast clamped to an
external voltage independent of the digital input from
the serial interface. Both the MAX11014 and the
MAX11015 include self-calibration modes to minimize
error over time, temperature, and supply voltage.
The MAX11014/MAX11015 feature an internal reference
and can operate from separate ADC and DAC external
references. The internal reference provides a well-regu-
lated, low-noise +2.5V reference for the ADC, DAC, and
temperature sensors. These integrated circuits operate
from a 4-wire 20MHz SPI™-/MICROWIRE™-compatible
or 3.4MHz I2C-compatible serial interface (pin-selec-
table). Both devices operate from a +4.75V to +5.25V
analog supply (2.8mA typical supply current), a +2.7V
to +5.25V digital supply (1.5mA typical supply current),
and a -4.5V to -5.5V negative supply (1.1mA supply
current). The MAX11014/MAX11015 are available in a
48-pin thin QFN package specified over the -40°C to
+105°C temperature range.
FeaturesDual Drain-Current-Sense Gain Amplifier
Preset Gain of 4
±0.5% Accuracy for Sense Voltages Between
75mV and 625mV (MAX11014)Common-Mode Sense-Resistor Voltage Range
0.5V to 11V (MAX11014)
5V to 32V (MAX11015)Low-Noise Output GATE Bias with ±10mA GATE
DriveFast Clamp and Power-On Reset12-Bit DAC Controls MESFET GATE VoltageInternal Temperature Sensor/Dual Remote Diode
Temperature SensorsInternal 12-Bit ADC Measures Temperature and
VoltagePin-Selectable Serial Interface
3.4MHz I2C-Compatible Interface
20MHz SPI-/MICROWIRE-Compatible Interface
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
PARTPIN-PACKAGEAMPLIFIER
MAX11014BGTM+48 Thin QFN-EP**Class A
MAX11015BGTM+*48 Thin QFN-EP**Class AB
Ordering Information
Applications19-3985; Rev 3; 11/08
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
EVALUATION KITAVAILABLEDenotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
Note:All devices are specified over the -40°C to +105°C operating
temperature range.
Pin Configuration and Typical Operating Circuit appear at end
of data sheet.Cellular Base-Station RF MESFET Bias Controllers
Point-to-Point or Point-to-Multipoint Links
Industrial Process Control
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS(VGATEVSS= VAVSS= -5.5V to -4.75V, VAVDD= +4.75V to +5.25V, VDVDD= +2.7V to VAVDD, external VREFADC= +2.5V, external
VREFDAC= +2.5V, CREFADC= CREFDAC= 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+= +5V, CFILT1= CFILT3 = 1nF, CFILT2 =
CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0,VACLAMP1 = VACLAMP2 = -5V,TJ= TMINto TMAX, unless otherwise noted.
All typical values are at TJ= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CURRENT-SENSE AMPLIFIER (Note 1)MAX110140.511.0Common-Mode Input Voltage
RangeVRCS_+MAX11015532V
0.5V < VRCS_+ < 11V for the MAX1101490Common-Mode Rejection RatioCMRR5V < VRCS_+ < 32V for the MAX1101590dB
IRCS+200Input-Bias CurrentIRCS-
VSENSE < 100mV over the common-mode
range±2µA
Full-Scale Sense VoltageVSENSEVSENSE = VRCS_+ - VRCS_-625mV
To within ±0.5% accuracy75625
To within ±2% accuracy20625Sense Voltage Range
To within ±20% accuracy2625
Total Current Set ErrorVSENSE = 75mV±0.1±0.5%
Current-Sense Settling TimetHSCSSettles to within ±0.5% of final value< 25µs
Saturation Recovery TimeSettles to within ±0.5% accuracy, from
VSENSE = 1.875V< 45µs
CLASS AB INPUT CHANNELUntrimmed Offset19Bits
Offset Temperature Coefficient0Bits/oC
Gain4
Gain Error0.1%
AVDDto AGND.........................................................-0.3V to +6V
DVDDto DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AVSSto AGND...........................................................-0.3V to -6V
RCS1+, RCS1-, RCS2+, RCS2- to GATEVSS
(MAX11014)........................................................-0.3V to +13V
RCS1+, RCS1-, RCS2+, RCS2- to AGND
(MAX11015)........................................................-0.3V to +34V
RCS1- to RCS1+.......................................................-6V to +0.3V
RCS2- to RCS2+.......................................................-6V to +0.3V
GATEVSSto AGND...................................................+0.3V to -6V
GATE1, GATE2 to AGND.....(GATEVSS- 0.3V) to (AVDD+ 0.3V)
DVDDto AVDD..........................................-0.3V to (AVDD+ 0.3V)
All Other Analog Inputs to AGND............-0.3V to (AVDD+ 0.3V)
PGAOUT1, PGAOUT2 to AGND..............-0.3V to (AVDD+ 0.3V)
SCLK/SCL, DIN/SDA, CS/A0, N.C./A2, CNVST, OPSAFE1,
OPSAFE2 to DGND.............................-0.3V to (DVDD+ 0.3V)
DOUT/A1, SPI/I2C, ALARM, BUSY
to DGND..............................................-0.3V to (DVDD+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 27.0mW/°C
above +70°C)..........................................................2162.2mW
Operating Temperature Range.........................-40°C to +105°C
Storage Temperature Range...............................-60°C to 150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CLASS AB OUTPUT CHANNEL Untrimmed Offset (Note 1) 50 μV
Offset Temperature Coefficient 0 mV/oC
Gain -2
Gain Error 0.1 %
GATE-DRIVE AMPLIFIER/INTEGRATOR IGATE = -1mA VGATEVSS
+ 1 V
IGATE = +1mA -0.15 -4 mV
IGATE = -10mA VGATEVSS
+ 1.2 V
Output Gate-Drive Voltage Range
(Note 2) VGATE
IGATE = +10mA -1 -20 mV
Gate Voltage Settling Time—
MAX11015 tGATE
Settles to within ±0.5% of final value, RS
= 50, CGATE = 15μF, see GATE Output
Resistance vs. GATE Voltage in the
Typical Operating Characteristics
1.1 ms
No series resistance, RS = 0 0 0.5 Output Capacitive Load (Note 3) CGATERS = 500 0 15,000nF
Gate Voltage Noise RMS noise, 1kHz to 1MHz 250 nV/Hz
Maximum Power-On Transient CLOAD = 1nF ±100 mV
Output Short-Circuit Current Limit ISC Sinking or sourcing ±25 mA
Output SafeSwitch On-
Resistance ROPSWClamp GATE1 to ACLAMP1, GATE2 to
ACLAMP2 (Note 4) 3.6 k
ADC DC ACCURACY Resolution 12 Bits
Differential Nonlinearity DNLADC ±2 LSB
Integral Nonlinearity INLADC (Note 5) ±2 LSB
Offset Error ±2 ±4 LSB
Gain Error (Note 6) ±2 ±4 LSB
Gain Temperature Coefficient ±0.4 ppm/oC
Offset Temperature Coefficient ±0.4 ppm/oC
Channel-to-Channel Offset
Matching ±0.1 LSB
Channel-to-Channel Gain
Matching ±0.1 LSB
ELECTRICAL CHARACTERISTICS (continued)(VGATEVSS= VAVSS= -5.5V to -4.75V, VAVDD= +4.75V to +5.25V, VDVDD= +2.7V to VAVDD, external VREFADC= +2.5V, external
VREFDAC= +2.5V, CREFADC= CREFDAC= 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+= +5V, CFILT1= CFILT3 = 1nF, CFILT2 =
CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0,VACLAMP1 = VACLAMP2 = -5V,TJ= TMINto TMAX, unless otherwise noted.
All typical values are at TJ= +25°C.)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC DYNAMIC ACCURACY (1kHz sine-wave input, -0.5dB from full scale, 94.4ksps)Signal-to-Noise Plus DistortionSINAD70dB
Total Harmonic DistortionTHDUp to the 5th harmonic-84dB
Spurious-Free Dynamic RangeSFDR86dB
Intermodulation DistortionIMDfIN1 = 9.9kHz, fIN2 = 10.2kHz76dB
Full-Power Bandwidth-3dB point1MHz
Full-Linear BandwidthS / (N + D) > 68dB100kHz
ADC CONVERSION RATEExternal reference0.8Power-Up TimetPUInternal reference50µs
GATE_ and sense voltage measurements40Acquisition Time (Note 3)tACQAll other measurements1.5µs
Conversion TimetCONVInternally clocked6.5µs
Aperture Delay30ns
ADCIN1, ADCIN2 INPUTSInput RangeVADCIN_Relative to AGND (Note 7)0VREFADCV
Input Leakage CurrentVADCIN_ = 0V or VAVDD±0.01±1µA
Input CapacitanceCADCIN_34pF
TEMPERATURE MEASUREMENTSTJ = +25°C±0.25
TJ = -40°C to +85°C (Note 3)±1.0±2.5Internal Sensor Measurement
Error
TJ = -40°C to +105°C (Note 3)±1.0±3.5
TJ = +25°C±1.0External Sensor Measurement
Error (Note 8)TJ = -40°C to +105°C±3°C
Temperature Resolution0.125°C/LSB
External Diode Drive3.2675.00µA
External Temperature Sensor
Drive Current Ratio16.6
INTERNAL REFERENCEReference Output VoltageVREFADC = VREFDAC, TJ = +25°C+2.490+2.500+2.510V
Reference Output Temperature
Coefficient±15ppm/oC
Reference Output Impedance6.5kΩ
Power-Supply Rejection RatioPSRRVAVDD = +5V ±5%-83dB
ELECTRICAL CHARACTERISTICS (continued)(VGATEVSS= VAVSS= -5.5V to -4.75V, VAVDD= +4.75V to +5.25V, VDVDD= +2.7V to VAVDD, external VREFADC= +2.5V, external
VREFDAC= +2.5V, CREFADC= CREFDAC= 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+= +5V, CFILT1= CFILT3 = 1nF, CFILT2 =
CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0,VACLAMP1 = VACLAMP2 = -5V,TJ= TMINto TMAX, unless otherwise noted.
All typical values are at TJ= +25°C.)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCESREFADC Input Voltage RangeVREFADC+1.0VAVDDV
VREFADC = +2.5V, fSAMPLE = 178ksps60REFADC Input CurrentIREFADCAcquisition/between conversions±0.01µA
REFDAC Input Voltage RangeVREFDAC+0.50+2.52V
REFDAC Input Current26µA
DAC DC ACCURACYResolution12Bits
Integral NonlinearityINLDACMeasured at FILT_±1LSB
Differential NonlinearityDNLDACMeasured at FILT_, guaranteed monotonic±0.4±1LSB
POWER SUPPLIESAnalog Supply VoltageVAVDD+4.75+5.25V
Digital Supply VoltageVDVDD+2.7AVDDV
Negative Supply VoltageVGATEVSS,
VAVSSVGATEVSS = VAVSS-5.50-4.75V
Analog Supply CurrentIAVDDVAVDD = +5.25V2.85mA
Digital Supply CurrentIDVDDVDVDD = +5.25V1.55mA
Negative Supply CurrentIGATEVSS
+ IAVSSVGATEVSS = VAVSS = -5.5V1.11.7mA
Analog Shutdown CurrentVAVDD = +5.25V0.8µA
Digital Shutdown CurrentVDVDD = +5.25V0.2µA
Negative Shutdown CurrentVGATEVSS = VAVSS = -5.5V0.6µA
SERIAL-INTERFACE SUPPLIESVIL0.3 x
DVDD
Input Voltage
VIH0.7 x
DVDD
Input HysteresisVHYS0.05 x
DVDDV
Output Low VoltageVOLBUSY: ISINK = 0.5mA;
DOUT, ALARM: ISINK = 3mA0.4V
Output High VoltageVOH
SPI/ I2C = DVDD;
BUSY: ISOURCE = 0.5mA;
DOUT, ALARM: ISOURCE = 2mA
DVDD -
0.5VV
Input CurrentIIN±0.01±10µA
Input CapacitanceCIN5pF
ELECTRICAL CHARACTERISTICS (continued)(VGATEVSS= VAVSS= -5.5V to -4.75V, VAVDD= +4.75V to +5.25V, VDVDD= +2.7V to VAVDD, external VREFADC= +2.5V, external
VREFDAC= +2.5V, CREFADC= CREFDAC= 0.1µF, VOPSAFE1 = VOPSAFE2 = 0, VRCS1+ = VRCS2+= +5V, CFILT1= CFILT3 = 1nF, CFILT2 =
CFILT4 = 1nF, VAGND = VDGND = 0, VADCIN0 = VADCIN1 = 0,VACLAMP1 = VACLAMP2 = -5V,TJ= TMINto TMAX, unless otherwise noted.
All typical values are at TJ= +25°C.)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
SPI-INTERFACE TIMING CHARACTERISTICS(Note 9) (See Figure 1.)
2C-INTERFACE SLOW-/FAST-MODE TIMING CHARACTERISTICS(Note 9) (See Figure 2.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK Clock PeriodtCP40ns
SCLK High TimetCH16ns
SCLK Low TimetCL16ns
DIN to SCLK Rise Setup TimetDS10ns
DIN to SCLK Rise Hold TimetDH0ns
SCLK Fall to DOUT TransitiontDOCL = 30pF20ns
CS Fall to DOUT EnabletDVCL = 30pF (Note 3)40ns
CS Rise to DOUT DisabletTRCL = 30pF (Note 10)40ns
CS Rise or Fall to SCLK RisetCSS10ns
CS Pulse-Width HightCSW(Note 3)40ns
Last SCLK Rise to CS RisetCSH(Note 3)0ns
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL Clock FrequencyfSCL0400kHz
Bus Free Time Between a STOP
and START ConditiontBUF1.3µs
Hold Time (Repeated) for START
ConditiontHD;STAAfter this period, the first clock
pulse is generated0.6µs
Setup Time for a Repeated START
ConditiontSU;STA0.6µs
SCL Pulse-Width LowtLOW1.3µs
SCL Pulse-Width HightHIGH0.6µs
Data Setup TimetSU;DAT100ns
Data Hold TimetHD;DAT(Note 11)00.9µs
SDA, SCL Rise Time, ReceivingtR(Notes 3, 12)0300ns
SDA, SCL Fall Time, ReceivingtF(Notes 3, 12)0300ns
SDA Fall Time, TransmittingtF(Notes 3, 12, 13)20 + 0.1 x CB250ns
Setup Time for STOP ConditiontSU;STO0.6µs
Capacitive Load for Each Bus LineCB(Notes 3, 14)400pF
Pulse Width of Spikes Suppressed
By the Input FiltertSP(Note 15)50ns
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers2C-WIRE-INTERFACE HIGH-SPEED-MODE TIMING CHARACTERISTICS(Note 9) (See Figure 3.)
CB = 100pF maxCB = 400pFPARAMETERSYMBOLCONDITIONS
MINMAXMINMAX
UNITSSerial Clock FrequencyfSCL03.401.7MHz
Setup Time (Repeated) START
ConditiontSU;STA160160ns
Hold Time (Repeated) START
ConditiontHD;STA160160ns
SCL Pulse-Width LowtLOW160320ns
SCL Pulse-Width HightHIGH60120ns
Data Setup TimetSU;DAT1010ns
Data Hold TimetHD;DAT(Note 11)0700150ns
SCL Rise TimetRCL(Note 3)10402080ns
SCL Rise Time, After a Repeated
START Condition and After an
Acknowledge Bit
tRCL1(Note 3)108020160ns
SCL Fall TimetFCL(Note 3)10402080ns
SDA Rise TimetRDA(Note 3)108020160ns
SDA Fall TimetFDA(Note 3)108020160ns
Setup Time for STOP ConditiontSU;STO160160ns
Capacitive Load for Each Bus LineCB(Note 14)100400pF
Pulse Width of Spikes Suppressed
By the Input FiltertSP(Note 15)010010ns
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
MISCELLANEOUS TIMING CHARACTERISTICS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMinimum Time to Wait After a
Write Command Before
Reading Back Data from the
Same Location
tRDBK(Note 16)1µs
CNVST Active-Low Pulse
Width in ADC Clock Mode 01tCNV01(Note 3)20ns
CNVST Active-Low Pulse
Width in ADC Clock Mode 11
to Initiate a Temperature
Conversion
tCNV11(Note 3)20ns
CNVST Active-Low Pulse
Width in ADC Clock Mode 11
for ADCIN1/2 Acquisition
tACQ11A(Note 3)1.5µs
ADC Power-Up Time (External
Reference)tAPUEXT0.8µs
ADC Power-Up Time (Internal
Reference)tAPUINT50µs
DAC Power-Up Time (External
Reference)tDPUEXT2µs
DAC Power-Up Time (Internal
Reference)tDPUINT50µs
Acquisition Time (Internally
Timed in ADC Clock Modes
00 or 01)
tACQ0.6µs
Conversion Time (Internally
Clocked)tCONV6.5µs
Delay to Start of Conversion
TimetCONVW(Note 17)1µs
Temperature Conversion Time
(Internally Clocked)tCONVT30µs
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Note 1:All current-sense amplifier specifications are tested after a current-sense calibration (valid when drain current = 0mA). See
RCS Error vs. GATE Current in the Typical Operating Characteristics. The calibration is valid only at one temperature and
supply voltage and must be repeated if either the temperature or supply voltage changes.
Note 2:The hardware configuration register’s CH_OCM1 and CH_OCM0 bits are set to 0. See Table 10a. The max specification is
limited by tester limitations.
Note 3:Guaranteed by design. Not production tested.
Note 4:At power-on reset, the output safe switch is closed. See the ALMHCFG(Read/Write)section.
Note 5:Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been calibrated out.
Note 6:Offset nulled.
Note 7:Absolute range for analog inputs is from 0 to VAVDD.
Note 8:Device and sensor at the same temperature. Verified by the current ratio (see the Temperature Measurementssection).
Note 9:All timing specifications referred to VIHor VILlevels.
Note 10:DOUTgoes into tri-state mode after the CSrising edge. Keep CSlow long enough for the DOUT value to be sampled
before it goes to tri-state.
Note 11:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 12:tRand tFmeasured between 0.3 x DVDDand 0.7 x DVDD.
Note 13:CB= total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
linearly interpolated.
Note 14:An appropriate bus pullup resistance must be selected depending on board capacitance. For more information, refer to the
I2C documentation on the Philips website.
Note 15:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 16:When a command is written to the serial interface, it is passed to the internal oscillator clock to be executed. There is a
small synchronization delay before the new value is written to the appropriate register. If the user attempts to read the new
value back before tRDBK, no harm will be caused to the data, but the read command may not yet show the new value.
Note 17:This is the minimum time from the end of a command before CNVSTshould be asserted. The time allows for the data from
the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the
write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of
the wrong ADC channel).
MISCELLANEOUS TIMING CHARACTERISTICS (continued)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllerstHD;DAT
SDA
SCL
tRCL1tRCL
tRCL1
tFDASr
tLOWtLOWtHIGHtHIGH
tFCL
tRDA
tHD;STAtSU;DAT
Sr = REPEATED START, P = STOP
tSU;STA
tSU;STO
Figure 3. High-Speed Timing Diagram
tCSS
SCLK
tDH
tDV
tDS
DIN
DOUTC6D1D0
tCHtCSH
tCSS
tCSW
tCLtCP
tDOtTR
Figure 1. SPI Serial-Interface Timing Diagram
SDA
SCL
tSU;STOtSPtHD;STA
tSU;STA
tHIGH
tSU;DAT
tHD;DAT
tHD;STASSrP
S = START, Sr = REPEATED START, P = STOP
tLOWtBUF
Figure 2. Slow-/Fast-Speed Timing Diagram
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersDIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX11014 toc01
DVDD SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
AVDD = 5.25V
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX11014 toc02
AVDD SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
RCS ERROR vs. TEMPERATURE
MAX11014 toc03
TEMPERATURE (°C)
RCS ERROR (mV)
AFTER CALIBRATION
BEFORE CALIBRATION
40μs/div
-5V
MAX11014 toc04
VGATE
1V/div
GATE VOLTAGE POWER-UPFILT1/FILT3 SETTLING TIME
vs. FILT1/FILT3 CAPACITIVE LOAD
MAX11014 toc05
CAPACITIVE LOAD (pF)
SETTLING TIME (
10% TO 90%
tRISE
tFALL
RCS ERROR vs. GATE CURRENT
MAX11014 toc06
GATE CURRENT (mA)
RCS ERROR (mV)
SOURCING
SINKING-3-4-2-10
MAX11014 toc07
VGATE (V)
GATE OUTPUT RESISTANCE (
GATEVSS = AVSS = -5V
GATE OUTPUT RESISTANCE
vs. GATE VOLTAGE1μs/div
FILT1
1mV/div
AC-COUPLED
MAX11014 toc08
GLITCH IMPULSEDAC INTEGRAL NONLINEARITY
vs. OUPUT CODE
MAX11014 toc09
OUTPUT CODE
DAC INL (LSB)
Typical Operating Characteristics(VGATEVSS= -5.5V; VAVDD= VDVDD= +5V, GATEVSS= AVSS= -5V, external VREFADC= +2.5V; external VREFDAC= +2.5V; CREF=
0.1µF; TA= TMINto TMAX, unless otherwise noted.)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllersypical Operating Characteristics (continued)(VGATEVSS= -5.5V; VAVDD= VDVDD= +5V, GATEVSS= AVSS= -5V, external VREFADC= +2.5V; external VREFDAC= +2.5V; CREF=
0.1µF; TA= TMINto TMAX, unless otherwise noted.)
DAC DIFFERTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11014 toc10
OUTPUT CODE
DAC DNL (LSB)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11014 toc11
OUTPUT CODE
ADC INL (LSB)
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11014 toc12
OUTPUT CODE
ADC DNL (LSB)
ADC SINAD vs. FREQUENCY
MAX11014 toc13
FREQUENCY (kHz)
SINAD (dB)
ADC SFDR vs. FREQUENCY
MAX11014 toc14
FREQUENCY (kHz)
SFDR (dB)
ADC TOTAL HARMONIC DISTORTION
vs. FREQUENCY
MAX11014 toc15
FREQUENCY (kHz)
THD (%)
ADC FFT PLOT
MAX11014 toc16
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)103040
fANALOG_IN = 9.982kHz
fCLK = 3.052MHz
SINAD = 71.28dBc
SNR = 71.51dBc
THD = -84.18dBc
SFDR = -86.94dBc
DIGITAL SUPPLY CURRENT
vs. SAMPLING RATE
MAX11014 toc17
SUPPLY CURRENT (mA)
AVDD = DVDD = 5V
ADC INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11014 toc18
SUPPLY VOLTAGE (V)
ADC REFERENCE VOLTAGE (V)
AVDD = DVDD
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersDAC INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11014 toc19
SUPPLY VOLTAGE (V)
DAC REFERENCE VOLTAGE (V)
AVDD = DVDD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11014 toc20
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
VREFDAC
VREFADC
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX11014 toc21
AVDD (V)
ADC OFFSET ERROR (LSB)
ADC OFFSET ERROR vs. TEMPERATUREMAX11014 toc22
TEMPERATURE (°C)
ADC OFFSET ERROR (LSB)
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX11014 toc23
AVDD (V)
ADC GAIN ERROR (LSB)
ADC GAIN EROR vs. TEMPERATURE
MAX11014 toc24
TEMPERATURE (°C)
ADC GAIN ERROR (LSB)
INTERNAL TEMPERATURE SENSOR ERROR
vs. TEMPERATUREMAX11014 toc25
INTERNAL TEMPERATURE SENSOR ERROR (
TEMPERATURE (°C)
GND
VRCS1-
100mV/div
VPGAOUT1
200mV/div
VFILT1
200mV/div
0 TO 100mV VSENSE
TRANSIENT RESPONSEMAX11014 toc26
10ms/div
GND
GND
VRCS1-
200mV/div
VPGAOUT1
500mV/div
VFILT1
500mV/div
0 TO 250mV VSENSE
TRANSIENT RESPONSEMAX11014 toc27
10ms/div
ypical Operating Characteristics (continued)(VGATEVSS= -5.5V; VAVDD= VDVDD= +5V, GATEVSS= AVSS= -5V, external VREFADC= +2.5V; external VREFDAC= +2.5V; CREF=
0.1µF; TA= TMINto TMAX, unless otherwise noted.)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Pin Description
PINNAMEFUNCTIONDIN/SDASerial Data Input. Data is latched into the serial interface on the rising edge of SCLK in SPI mode.
Connect a pullup resistor to SDA in I2C mode.DOUT/A1
Serial Data Output in SPI Mode/Address Select 1 in I2C Mode. Data transitions on the falling edge of
SCLK. DOUT is high impedance when CS is high. Connect A1 to DVDD or DGND to set the device
address to I2C mode.ADCIN1Analog Input 1ADCIN2Analog Input 2DXN1Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to
DXN1.DXP1Remote-Diode Current Source. Connect DXP1 to the base/collector of a remote temperature-sensing
npn transistor. Do not leave DXP1 open; connect to DXN1 if no remote diode is used.DXN2Remote-Diode Current Sink. Connect the emitter of a base-emitter junction remote npn transistor to
DXN2.DXP2Remote-Diode Current Source. Connect DXP2 to the base/collector of a remote temperature-sensing
npn transistor. Do not leave DXP2 open; connect to DXN2 if no remote diode is used.REFDACDAC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See
the HCFG (Read/Write) section.REFADCADC Reference Input/Output. Connect a 0.1µF capacitor to AGND in external reference mode. See
the HCFG (Read/Write) section.
11, 27AVDDPositive Analog Supply Voltage. Set AVDD between +4.75V and +5.25V. Bypass with a 1µF and a
0.1µF capacitor in parallel to AGND.
12, 26AGNDAnalog GroundACLAMP2MESFET2 External Clamping Voltage InputGATE2MESFET2 Gate Connection. See the Gate-Drive Amplifiers section.GATEVSSGate-Drive Amplifier Negative Power-Supply Input. Set GATEVSS between -4.75V and -5.5V. Connect
externally to AVSS. Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND.
16, 28, 29,
34–37N.C.No Connection. Not internally connected.ACLAMP1MESFET1 External Clamping Voltage InputGATE1MESFET1 Gate Connection. See the Gate-Drive Amplifiers section.FILT1Channel 1 Filter 1 Input. See Figures 5 and 6.FILT2Channel 1 Filter 2 Input. See Figures 5 and 6.FILT3Channel 2 Filter 3 Input. See Figures 5 and 6.FILT4Channel 2 Filter 4 Input. See Figures 5 and 6.PGAOUT1Channel 1 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6.PGAOUT2Channel 2 Amplifier Voltage Output. See the PGAOUT Outputs section and Figures 5 and 6.AVSSNegative Analog Supply Voltage. Set AVSS between -4.75V and -5.5V. Connect externally to
GATEVSS. Bypass with a 1µF and a 0.1µF capacitor in parallel to AGND.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Pin Description (continued)
PINNAMEFUNCTIONRCS2+
Channel 2 Current-Sense-Resistor Connection. Connect to the external supply powering channel 2’s
MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with
a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS1+.RCS2-Channel 2 Current-Sense-Resistor Connection. Connect to the channel 2 MESFET drain. Decouple as
required by the application. If unused, connect to RCS2+.RCS1-Channel 1 Current-Sense-Resistor Connection. Connect to the channel 1 MESFET drain. Decouple as
required by the application. If unused, connect to RCS1+.RCS1+
Channel 1 Current-Sense-Resistor Connection. Connect to the external supply powering channel 1’s
MESFET drain, in the range of +0.5V to +11V (MAX11014) or +5V to +32V (MAX11015). Bypass with
a 1µF and a 0.1µF capacitor in parallel to AGND. If unused, connect to RCS2+.OPSAFE1Operating Safe Channel 1 Input. Set OPSAFE1 high to clamp GATE1 to ACLAMP1 for fast protection
of enhancement FET power transistors.OPSAFE2Operating Safe Channel 2 Input. Set OPSAFE2 high to clamp GATE2 to ACLAMP2 for fast protection
of enhancement FET power transistors.BUSYBUSY Output. BUSY asserts high under certain conditions when the device is busy. See the BUSY
Output section.DVDDDigital Supply Voltage. Set DVDD between +2.7V and AVDD. Bypass with a 1µF and a 0.1µF capacitor
in parallel to DGND.DGNDDigital GroundCNVSTActive-Low Conversion Start Input. Set CNVST low to begin a conversion in clock modes 01 and 11.
Connect CNVST to DVDD when issuing conversion commands through the serial interface.ALARMALARM Output. ALARM asserts when the temperature or voltage measurements exceed their preset
high or low thresholds.CS/A0
Chip-Select Input in SPI Mode/Address Select 0 in I2C Mode. CS is an active-low input. When CS is
low, the serial interface is enabled. When CS is high, DOUT is high impedance. Connect A0 to DVDD
or DGND to set the device address in I2C mode.SPI/I2CSPI-/I2C-Interface Select Input. Connect SPI/I2C to DVDD to select SPI mode. Connect SPI/I2C to
DGND to select I2C mode.N.C./A2No Connection in SPI Mode/Address Select 2 in I2C Mode. Connect A2 to DVDD or DGND to set the
device address in I2C mode.SCLK/SCL
Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.)
Connect a pullup resistor to SCL in I2C mode. See Table 10 for details on programming the clock
mode.
—EPExposed Pad. Connect to AGND and a large copper plane to meet power dissipation specifications.
Do not use as a ground connection.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Detailed DescriptionThe MAX11014/MAX11015 set and monitor the bias con-
ditions for dual MESFET power devices found in cellular
base stations and point-to-point microwave links. The
internal DAC sets the voltage across the current-sense
resistor by controlling the GATE voltage. These devices
integrate a 12-bit ADC to measure voltage, internal and
external temperature, and communicate through a 4-wire
20MHz SPI-/MICROWIRE-compatible serial interface or
2-wire 3.4MHz I2C-compatible serial interface
(pin-selectable).
The MAX11014/MAX11015 operate from an internal
+2.5V reference or individual ADC and DAC external
references. The external current-sense resistors moni-
tor voltages over the 0 to (VDACREF / 4) range. Two cur-
rent-sense amplifiers with a preset gain of four monitor
the voltage across the sense resistors. The
MAX11014/MAX11015 accurately measure their inter-
nal die temperature and two external remote diode tem-
perature sensors. The remote pn junctions are typically
the base-emitter junction of an npn transistor, either
discrete or integrated on a CPU, FPGA, or ASIC.
The MAX11014/MAX11015 also feature an ALARM out-
put that can be triggered during an internal or external
overtemperature condition, an excessive current-sense
voltage, or an excessive GATE voltage. Figure 4 shows
the MAX11014’s functional diagram.
The MAX11014 integrates complete dual analog
closed-loop drain-current controllers for Class A
MESFET amplifier operation. See the MAX11014 Class
A Control Loopsection. The analog control loop sets
the drain current through the current-sense resistors.
The MESFET gate-drive amplifier can vary the DAC
code accordingly if the temperature or other system
variables change.
Implement Class A amplifier operation with the follow-
ing three steps:Characterization
Characterize the MESFET over temperature to deter-
mine the amplifier’s set of drain-current values,
assuming the part-to-part calibration curve is consis-
tent. There may be an offset shift, but no important
change in the shape of the function. Load these val-
ues into the MAX11014 LUTs at power-up. In opera-
tion, there is a linear interpolation between the
values stored in the LUTs.
Adjust the drain current for other variables such as
output power or drain voltage by loading values into
the numerical KLUTs.Calibration
In production of the power amplifier, measure the
quiescent drain current at a fixed calibration temper-
ature (probably room) and adjust the VSET(CODE)
value until the drain current is within the specified
limits for that temperature. The VSET(CODE)value is
stored for loading after power-up. Prior to operation,
command a PGA calibration after powering up by
writing to the PGA calibration control register, setting
the TRACK bit to 0 and the DOCAL bit to 1 (see
Table 18).Operation
Upon request, the MAX11014 measures the temper-
ature of the MESFET and compares it with the previ-
ous reading. If the temperature reading has
changed, the MAX11014 reads the LUTs with the
characterization data and updates the DAC to cor-
rect the drain current. Setting the TRACK, DOCAL,
and SELFTIME bits to 1 in the PGA calibration con-
trol register starts automatic monitoring and adjust-
ment of drain current for variations in temperature.
Also, if the KLUTs are used, their values are monitored
for changes.A DACcorrection is then made ifnecessary.
For Class AB operation with the MAX11015, measure
the MESFET temperature and set the GATE_ voltage
through the LUTs and DAC to control the drain current.
See the MAX11015 Class AB Controlsection.
Implement Class AB amplifier operation with the same
three steps as Class A operation, with the exception
that the LUTs set the GATE_ voltage for constant drain
current with varying temperature.
Power-On ResetOn power-up, the MAX11014/MAX11015 are in full
power-down mode (see the SHUT (Write)section). To
change to normal power mode, write two commands to
the shutdown register. Set the FULLPD bit to 0 (other
bits in the shutdown register are ignored) on the first
command. A second command to this register then
activates the internal blocks.
MAX11014 Class A Control LoopThe MAX11014 is designed to set and continuously
control the drain current for MESFET power amplifiers
configured to operate in Class A. Set the DAC code to
control the voltage across the RCS_+ and RCS_- cur-
rent-sense resistor connections. The MAX11014 inter-
nal control loop automatically keeps the voltage across
the current-sense resistor to the value set by the DAC.
See the 12-Bit DACsection.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersREFADC
MUX
INTERNAL
TEMPERATURE
SENSOR
INTERNAL
+2.5V
REFERENCE
POR
CONVERSION, SCAN,
OSCILLATOR, AND CONTROL
VOLTAGE/TEMPERATURE DIGITAL
COMPARATOR
ADCIN1
BIAS CURRENT
GENERATOR
DRAIN
SUPPLY
DRAIN
SUPPLY
SCLK/SCLDIN/SDADOUT/A1
CNVST
BUSY
POWER
GOOD
DVDD
DGND
GATEVSS
GATE1
RCS1+
RESET
REGISTER
MAP
ACLAMP1
DIGITAL
CONTROL
12-BIT DAC CODE
FILT1
FILT2
RCS1-
12-BIT
REGISTER
GATE2
RCS2+
ACLAMP2
FILT3
FILT4
RCS2-
12-BIT
REGISTER
ALARM
ALARM
LIMIT
ALARM
SENSE
VOLTAGE
CONTROL
DAC
CHANNEL
SELECT
ADC
CHANNEL
SELECT
DAC
CONTROL
ADC
CONTROL
SERIAL
INTERFACE
48-ENTRY INTERPOLATING
TEMPERATURE SRAM LUT
48-ENTRY INTERPOLATING K
SRAM LUT
48-ENTRY INTERPOLATING
TEMPERATURE SRAM LUT
48-ENTRY INTERPOLATING K
SRAM LUT
ALU
ADCIN2
DXP1
DXN1
DXP2
DXN2
12-BIT ADC
REFDAC
AGND
AVDD
AVSS
PGAOUT1PGAOUT2
CHANNEL 1CHANNEL 2
OPSAFE1
OPSAFE2
CHANNEL
1 DAC
CHANNEL
2 DACSS
N.C./A2SPI/I2C
EXTERNAL
TEMPERATURE
SENSOR
PROCESSING
MAX11014
MAX11015
CS/A0
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersOnce the control loop has been set, the MAX11014
automatically maintains the drain-current value. Figure
5 details the amplifiers that bias the channel 1 and
channel 2 control loops.
The dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- by four and add an offset
voltage (+12mV nominally). These current-sense ampli-
fiers amplify sense voltages between 0 and 625mV
when VREFDAC= +2.5V. See the Current-Sense
Amplifierssection.
The current-sense amplifier output injects a scaled-down
replica of the MESFET drain current at the summing
node to complete the internal analog feedback loop. The
summing node drives the gate-drive amplifier through a
100kΩseries resistor. The gate-drive amplifier is config-
ured as an integrator by the external capacitor connect-
ed between GATE1/GATE2 and FILT2/FILT4. The
gate-drive amplifier includes automatic offset cancella-
tion between 0 and 24mV to null the 12mV offset from the
current-sense amplifier. See the Register Descriptions
and PGACAL(Write)sections.
The MAX11014’s analog control loop setpoint is
described by the following equation:
where:
VFILT(CODE = 000h) = VFILT1(channel 1) and VFILT3
(channel 2) when the THRUDAC1/THRUDAC2 register
code is set to 000h.
VFILT= VFILT1(channel 1) and VFILT3(channel 2).
VRCS_+ - VRCS_-= the voltage drop across the current-
sense resistor.
Connect a capacitor from FILT2 to GATE1 to form an
integrator (setting the control-loop dominant pole) with
the channel 1 internal 100kΩresistor. Connect a
capacitor from FILT4 to GATE2 to form an integrator
(setting the control-loop dominant pole) with the chan-
nel 2 internal 100kΩresistor. The gate-drive amplifier’s
output drives the MESFET gates. See the Gate-Drive
Amplifierssection.
The channel 1 DAC voltage is output to FILT1 through a
series 580kΩresistor. The channel 2 DAC voltage is
output to FILT3 through a series 580kΩresistor.
Connect a capacitor from FILT1 to AGND and FILT3 to
AGND to set the filter’s time constant for the respective
channel.
MAX11015 Class AB ControlThe MAX11015 is designed to be used with a Class AB
amplifier configuration to independently measure the
drain current and set the GATE_ output voltages through
the serial interface. After sensing the drain current with
no RF signal applied, set the DAC code to obtain the
desired GATE_ voltage. Figure 6 details the amplifiers
that bias the channel 1 and channel 2 control.
The MAX11015 internal 12-bit DAC voltage is applied to
the gate-drive amplifier, which has a preset gain of
-2. See the Gate-Drive Amplifierssection. Setting the
DAC code between FFFh and 000h typically produces
a GATE_ voltage between 0 and (-2 x VREFDAC). See
the HCFG(Read/Write)section for details on adjusting
the GATE_ maximum voltage.
The channel 1 DAC voltage is output to FILT1 through a
series 580kΩresistor. The channel 2 DAC voltage is
output to FILT3 through a series 580kΩresistor.
Connect a capacitor from FILT1 to AGND and FILT3 to
AGND to set the filter’s time constant for the respective
channel. Connect FILT2 and FILT4 to AGND
(MAX11015 only).
The dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- by four and add an offset
voltage (+12mV nominally). The current-sense ampli-
fiers amplify sense voltages between 0 and 625mV
when VREFDAC= +2.5V. See the Current-Sense
Amplifierssection.
Current-Sense AmplifiersThe dual current-sense amplifiers amplify the voltage
between RCS_+ and RCS_- and add an offset voltage.
Connect a resistor between RCS_+ and RCS_- to sense
the MESFET drain current. The current-sense amplifiers
scale the sense voltage by four. These amplifiers also
reject the drain supply voltage that appears as a DC
common-mode level on the current signal.
The gate-drive amplifier includes automatic offset can-
cellation between 0 and 24mV to null the 12mV offset
from the current-sense amplifier. See the PGACAL
(Write)section.
Gate-Drive AmplifiersThe gate-drive amplifiers control the MESFET gate bias
settings. The MAX11014’s channel 1 and channel 2
DAC voltages are routed through a summing node and
into the gate-drive amplifiers. The MAX11015’s channel
1 and channel 2 DAC voltages are routed directly to the
gate-drive amplifiers, which have a preset gain of -2.
See the 12-Bit DAC section for details on setting the
DAC codes.VCODEhV
RCSRCSFILTFILT__()−−==−000
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersFigure 5. MAX11014 Class A Analog Control Loop
MAX11014
GATE1
FILT2
POWER
MESFET
+0.5V TO +11V
RCS1+
RCS1-
CHANNEL 1
DAC
FILT1
SERIAL
INTERFACE
PGAOUT1
CHANNEL 1
ADC
GATE-DRIVE
AMPLIFIER
580kΩ
CS/A0
SCLK/SCL
DIN/SDA
DOUT/A1
CFILT1
100kΩ
CFILT2
GATE2
FILT4
POWER
MESFET
+0.5V TO +11V
RCS2+
RCS2-
CHANNEL 2
DAC
FILT3
PGAOUT2
CHANNEL 2
ADC
CURRENT-SENSE
AMPLIFIER
CURRENT-SENSE
AMPLIFIER
GATE-DRIVE
AMPLIFIER
580kΩ
CFILT3
100kΩ
CFILT4
N.C./A2
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersMAX11015
GATE1
FILT2
POWER
MESFET
+5V TO +32V
RCS1+
RCS1-
CHANNEL 1
DAC
FILT1
SERIAL
INTERFACE
PGAOUT1
CHANNEL 1
ADCCURRENT-SENSE
AMPLIFIER
GATE-DRIVE
AMPLIFIER
GATE-DRIVE
AMPLIFIER
580kΩ
GAIN = -2
GATE2
FILT4
POWER
MESFET
+5V TO +32V
RCS2+
RCS2-
CHANNEL 2
DAC
FILT3
PGAOUT2
CHANNEL 2
ADCCURRENT-SENSE
AMPLIFIER
580kΩ
GAIN = -2
CFILT3
CFILT1
SCLK/SCL
DIN/SDA
DOUT/A1
N.C./A2
CS/A0
Figure 6. MAX11015 Class AB Analog Control
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersConnect the MESFET drain to the RCS_- input. Connect
the MESFET’s gate to the GATE_ output. Set the GATE_
voltage to -2 x VREFDACto turn the MESFET fully off.
Set the GATE_ voltage to 0V to turn the MESFET fully
on. See Figure 7.
The MAX11014/MAX11015 GATE_ output voltage can
be clamped to the external voltage applied at
ACLAMP_. Setting OPSAFE_ high clamps the GATE_
voltage unconditionally. The GATE_ can also be
clamped by different commands issued through the
serial interface. These devices can also monitor the
alarms through the software to modify the clamping
mechanism. See the Automatic GATE Clampingand
ALMHCFG (Read/Write)sections.
12-Bit ADC DescriptionThe MAX11014/MAX11015 ADCs use a fully differential
successive-approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the ADC Transfer
Functionsection for more details.
The internal ADC block converts the results of the inter-
nal die temperature, remote diode temperature read-
ings, current-sense voltages, and ADCIN_ voltages.
The ADC block also reads back the GATE_ analog out-
put voltage and converts it to a 12-bit digital result. The
conversion results are written to the FIFO memory. The
FIFO holds up to 15 words (each word of 16 bits) with a
leading 4-bit channel tag to indicate which channel the
12-bit data comes from. See Table 25. The FIFO reads
back data words either one at a time or continuously.
See the ADCCON (Write) section. The FIFO always
stores the most recent conversion results and allows
the oldest data to be overwritten. The FIFO indicates an
overflow condition and underflow condition (read of an
empty FIFO) through the flag register. See the FLAG
(Read)section.
Analog Input Track and HoldThe equivalent circuit of Figure 8 details the
MAX11014/MAX11015’s ADCIN_ input architecture. In
track mode, a positive input capacitor is connected to
ADCIN1/ADCIN2. A negative input capacitor is con-
nected to AGND. After the T/H enters hold mode, the
difference between the sampled input voltages and
AGND is converted. The input-capacitance charging
rate determines the time required for the T/H to acquire
an input signal. The required acquisition time lengthens
with the increase of the input signal’s source imped-
ance. Any source impedance below 300Ωdoes not
significantly affect the ADC’s AC performance. A high-
impedance source can be accommodated either by
placing a 1µF capacitor between ADCIN_ and AGND.
The combination of the analog-input source impedance
and the capacitance at the analog input creates an RC
MESFETFULLY
OFF
GATE
VOLTAGE
GATE VOLTAGE
ALARM
THRESHOLDS
ADC CODE
READ
FROM
THE FIFO-2 x VREFDAC
FFFh
000h
DEFAULT
VH = FFFh
DEFAULT
VL = 000h
VGATE
WITHIN
THRESHOLDS
TOO HIGH
TOO LOW
NEW HIGH GATE
VOLTAGE ALARM
THRESHOLD
NEW LOW GATE
VOLTAGE ALARM
THRESHOLD
USER
ENTERED
DAC CODEFFFh
000h
RCS_+ TO
RCS_- SENSE
VOLTAGE
PGAOUT
VOLTAGE0mV
VREFDAC / 4
VREFADC
Figure 7. DAC Code Range
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllersfilter that limits the analog-input bandwidth.
Analog Input ProtectionInternal ESD protection diodes clamp ADCIN1/ADCIN2
to AVDDand AGND, allowing them to swing from
(AGND - 0.3V) to (AVDD+ 0.3V) without damage.
However, for accurate conversions near full scale, the
inputs must not exceed AVDDby more than 50mV or be
lower than AGND by 50mV. If an analog input voltage
exceeds the supplies, limit the input current to 2mA.
Temperature MeasurementsThe MAX11014/MAX11015 measure their internal die
temperature and two external remote-diode tempera-
tures. Write to the ADC conversion register to com-
mand a temperature conversion. See Table 19. Set the
CH6 bit to 1 to calculate the remote-diode DXP2/DXN2
temperature sensor reading and load the data into the
FIFO. Set the CH1 bit to 1 to calculate the remote-diode
DXP1/DXN1 temperature-sensor reading and load the
data into the FIFO. Set the CH0 bit to 1 to calculate the
internal die temperature-sensor reading and load the
data into the FIFO. Temperature data is output in
signed two’s-complement format at DOUT in SPI mode
and SDA in I2C mode. See Figure 22 for the tempera-
ture transfer function.
The MAX11014/MAX11015 perform internal tempera-
ture measurements with a diode-connected transistor.
The diode bias current changes from 66µA to 4µA to
produce a temperature-dependent bias voltage differ-
ence. The second conversion result at 4µA is subtract-
ed from the first at 66µA to calculate a digital value that
is proportional to absolute temperature. The stored
data result is the above digital code minus an offset to
adjust from Kelvin to Celsius. The reference voltage for
the temperature measurements is derived from the
internal reference source to ensure the temperature
calibration of 1 LSB corresponding to +0.125°C.
For external temperature readings, connect an npn
transistor between DXP_ and DXN_. Connect the base
and collector together as shown in Figure 4 to form a
base-emitter pn junction. The MAX11014/MAX11015
feature an ALARM output that trips when the internal or
external temperature rises above an upper threshold
value or drops below a lower threshold value. Set the
high and low temperature thresholds through the chan-
nel 1/channel 2 high/low temperature ALARM threshold
registers. See Tables 3, 4, and 5.
The temperature-sensing circuits power up for the first
temperature measurement in an ADC conversion scan.
The temperature-sensing block remains on until the
end of the scan to avoid an additional 50µs power-up
delay for each individual temperature channel. See the
ADCIN1,
ADCIN2
AGND
HOLD
HOLDHOLD
AVDD / 2
COMPARATOR
DACREFADC
AGND
CIN+
CIN-
ACQ
ACQ
ACQ
Figure 8. ADC Equivalent Input Circuit
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersADCCON (Write)section, Figure 31, and Figure 32. The
temperature-sensor circuits remain powered up when
the ADC conversion register’s continuous convert bit
(CONCONV) is set to 1 and the current ADC conver-
sion includes a temperature channel. The temperature-
sensor circuits remain powered up until the CONCONV
bit is set low.
The external temperature sensor drive current ratio has
been optimized for a 2N3904 npn transistor with an ide-
ality factor of 1.0065. The nonideality offset is removed
internally by a preset digital coefficient. Using a transis-
tor with a different ideality factor produces a proportion-
ate difference in the absolute measured temperature.
For more details on this topic and others related to
using an external temperature sensor, see Application
Note 1057: Compensating for Ideality Factor and Series
Resistance Differences between Thermal Sense Diodes
and Application Note 1944: Temperature Monitoring
Using the MAX1253/54 and MAX1153/54on Maxim’s
website: .
12-Bit DACThe MAX11014/MAX11015 include two voltage-output,
12-bit monotonic DACs with ±1 LSB integral nonlineari-
ty error and ±0.4 LSB differential nonlinearity error. The
DAC operates from the internal +2.5V reference or an
external reference voltage supplied at REFDAC. When
using an external voltage reference, bypass REFDAC
with a 0.1µF capacitor to AGND. The REFDAC external
voltage range is +0.7V to +2.5V.
The MAX11014’s channel 1/channel 2 DACs set the
sense voltage between RCS_+ and RCS_- by control-
ling the GATE_ bias. See the MAX11014 Class A
Control Loopsection. The MAX11015’s channel 1/chan-
nel 2 DACs drive the GATE_ outputs directly, indepen-
dent of the current-sense voltages, through the
gate-drive amplifier with a gain of -2. See theMAX11015
Class AB Controlsection.
Set the channel 1/channel 2 DAC code by writing to the
respective channel’s DAC input registers, DAC input
and output registers, or VSETregisters. Write to the
DAC input registers (Table 16) and use a subsequent
write to the software load DAC register (Table 21) to
control the timing of the update. Write to the DAC input
and output registers (Table 17) to set the DAC output
voltage code directly, independent of the software load
DAC register bits. Write to the VSET registers (Table 14)
to include LUT data in the DAC code. Writing to the
VSETregisters triggers a VDAC(CODE) calculation as
shown in the following equation:
where
VDAC(CODE)= The modified channel 1/channel 2 12-bit
DAC code.
VSET(CODE)= The 12-bit DAC code written to the chan-
nel 1 /channel 2 VSETregisters.
LUTK[K] = The interpolated, fractional 12-bit KLUT
value. The KLUT data is derived from a variety of
sources, including: the VSETregistervalue, the K para-
meter register value, or various ADC channels. See the
SRAM LUTs section.
LUTTEMP[TEMP] = The interpolated, fractional 12-bit
two’s-complement temperature LUTvalue. The tempera-
ture LUT data is derived from either internal or external
temperature values. See the SRAM LUTssection.
The VDAC(CODE) equation code is then loaded into the
DAC input register or DAC output register, depending
on the corresponding channel’s LDAC bit in the soft-
ware configuration register. See Table 11.
Self-CalibrationCalibrate channel 1 and channel 2 by writing
to the PGA calibration control register. The
MAX11014/MAX11015 function after power-up without
a calibration. However, for best performance after pow-
ering up, command a calibration by setting the TRACK
bit to 0 and the DOCAL bit to 1 (see Table 18).
Subsequently, set the TRACK, DOCAL, and SELFTIME
bits to 1 to minimize loss of performance over tempera-
ture and supply voltage.
The self-calibration algorithm cancels offsets at the
gate-drive amplifier inputs in approximately 95µV incre-
ments to improve accuracy. The self-calibration routine
can be commanded when the DACs are powered
down, but the results will not be accurate. For best
results, run the calibration after the DAC power-up time,
tDPUEXT. The ADC’s operation is suspended during a
self-calibration. The end of the self-calibration routine is
indicated by the BUSY output returning low. See the
BUSY Outputsection. Wait until the end of the self-cali-
bration routine before requesting an ADC conversion.VLUTKxLUTTEMPDACCODESETCODEKTEMP()() ( [] [])==+1
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
ADC/DAC ReferencesThe MAX11014/MAX11015 provide an internal low-
noise +2.5V reference for the ADCs, DACs, and tem-
perature sensors. Set bits D3–D0 within the hardware
configuration register to control the source of the DAC
and ADC references. See Tables 10c and 10d.
Connect a voltage source to REFADC between +1.0V
and AVDDin external ADC reference mode. Connect a
voltage source to REFDAC between +0.7V to +2.5V in
external DAC reference mode. When using an external
voltage reference, bypass REFADC and REFDAC with
0.1µF capacitors to AGND.
Power SuppliesThe MAX11014/MAX11015 operate from separate ana-
log and digital power supplies. Set the analog supply
voltage, AVDD, between +4.75V and +5.25V. Set the
digital supply voltage, DVDD, between +2.7V and
AVDD. Bypass AVDDwith a 0.1µF and 1µF capacitor to
AGND and DVDDwith a 0.1µF and 1µF capacitor to
DGND. The analog circuitry typically consumes 2.8mA
of supply current and the digital circuitry 3.7mA.
Set the negative analog supply voltages, AVSSand
GATEVSS, between -4.75V and -5.5V. Connect AVSSand
GATEVSStogether externally. Bypass each of these neg-
ative supplies with a 0.1µF and 1µF capacitor to AGND.
The RCS_+ inputs supply the power to the input section
of the current-sense amplifiers. Set RCS_+ between
+0.5V and +11V on the MAX11014 and +5V to +32V on
the MAX11015. Bypass RCS_+ with a 0.1µF and 1µF
capacitor to AGND.
Serial InterfaceThe MAX11014/MAX11015 feature a pin-selectable
I2C/SPI serial interface. Connect SPI/I2Cto DGND to
select I2C mode, or connect SPI/I2Cto DVDDto select
SPI mode. SDA and SCL (I2C mode) and DIN, SCLK,
and CS(SPI mode) facilitate communication between
the MAX11014/MAX11015 and the master.
SPI Compatibility (SPI/I2C= DVDD)The MAX11014/MAX11015 communicate through a ser-
ial interface, compatible with SPI and MICROWIRE
devices. For SPI, ensure that the SPI bus master (typi-
cally a µC) runs in master mode so it generates the ser-
ial clock signal. Set the SCLK frequency to 20MHz or
less, and set the clock polarity (CPOL) and phase
(CPHA) in the µC control registers to the same value.
The MAX11014/MAX11015 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CSlow to latch input data at
DIN on the rising edge of SCLK. Output data at DOUT
is updated on the falling edge of SCLK. See Figure 1.
Temperature values are available in signed two’s-com-
plement format, while all others are in straight binary.
A high-to-low transition on CSinitiates the 24-bit data
input cycle. Once CSis low, write an 8-bit command
byte (MSB first) at DIN to indicate which internal regis-
ter is being accessed. The command byte also identi-
fies whether the data to follow is to be written into the
serial interface or read out. See the Register
Descriptionssection. After writing the command byte,
write two data bytes at DIN or read two data bytes at
DOUT. Keep CSlow throughout the entire 24-bit word
write. The serial-interface circuitry is common to the
ADC and DAC sections.
When writing data, write an 8-bit command word and
16 data bits at DIN. See Figure 9. Data is input to the
serial interface on the rising edge of SCLK. When read-
ing data, write an 8-bit command byte at DIN and read
the following 16 data bits at DOUT. See Figure 10. Data
transitions at DOUT on the falling edge of SCLK. DIN
can be set high or low while data is being transferred
out at DOUT.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersSCLK
DIN3456789102324
(MSB)C5C4C3C2C1C0
(LSB)
D15
(MSB)D14D1D0
(LSB)
THE COMMAND BYTE
INITIALIZES THE
INTERNAL REGISTERS.THE NEXT 16 BITS
ARE DATA BITS.
Figure 9. MAX11014/MAX11015 Write Timing
SCLK
DIN3456789102324
(MSB)C5C4C3C2C1C0
(LSB)
D15
(MSB)D14D1D0
(LSB)
THE COMMAND BYTE
INITIALIZES THE
INTERNAL REGISTERS.THE NEXT 16 DATA
BITS ARE READ OUT.
DOUT
X = DON'T CARE.
NOTE: DOUT MAY BE DRIVEN UP TO 2 CLOCK CYCLES BEFORE D15 IS AVAILABLE.ANY DATA ON DOUT BEFORE D15 IS AVAILABLE, SHOULD BE IGNORED.
Figure 10. MAX11014/MAX11015 Read Timing
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers2C Compatibility (SPI/I2C= DGND)The MAX11014/MAX11015 communicate through an
I2C-compatible 2-wire serial interface consisting of a
serial data line (SDA) and a serial clock line (SCL). SDA
and SCL facilitate bidirectional communication between
the MAX11014/MAX11015 and the master at data rates
up to 3.4MHz. The master (typically a µC) initiates data
transfer on the bus and generates the SCL signal to per-
mit data transfer. The MAX11014/MAX11015 behave as2C slave devices that transfer and receive data.
SCL and SDA must be pulled high for proper I2C oper-
ation. This is typically done with pullup resistors (1kΩor
greater). Series resistors are optional. The series resis-
tors protect the input architecture from high-voltage
spikes on the bus lines and minimize crosstalk and
undershoot of the bus signals.
One data bit transfers during each SCL clock cycle. A
minimum of 9 bytes is required to transfer a byte in or
out of the MAX11014/MAX11015 (8 bits and an
acknowledge (ACK)/not-acknowledge (NACK) bit).
Data is latched in on SCL’s rising edge and read out on
SCL’s falling edge. The data on SDA must remain sta-
ble during the high period of the SCL clock pulse.
Changes in SDA while SCL is stable and high are con-
sidered control signals (see the START and STOP
Conditionssection). Both SDA and SCL remain high
when the bus is not busy.
START and STOP ConditionsThe master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high (Figure 11). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and the interface mode unchanged (see the
High-Speed Modesection).
The address byte, command byte, and data bytes are
transmitted between the START and STOP conditions.
Nine clock cycles are required to transfer the data in or
out of the MAX11014/MAX11015. See Figures 15 and
16. If the receiver returns a not-acknowledge bit, the
MAX11014/MAX11015 releases the bus. If the not
acknowledge occurs in the middle of a 16-bit word, the
remaining bits are lost.
SCL
SDASr
S = START.
Sr = REPEATED START.
P = STOP.
Figure 11. START and STOP Conditions
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Acknowledge and Not-Acknowledge ConditionsData transfers are acknowledged with an acknowledge
bit or a not-acknowledge bit. Both the master and the
MAX11014/MAX11015 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
pulls SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keeps it low
during the high period of the clock pulse (Figure 12).
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves SDA
high during the high period of the clock pulse. Monitor
the acknowledge bits to detect an unsuccessful data
transfer. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault occurs. In
the event of an unsuccessful data transfer, the bus
master should reattempt communication at a later time.
Slave AddressThe MAX11014/MAX11015 have a 7-bit I2C slave
address. The MSBs of the slave address are factory
programmed to 0101. The logic state of address inputs
A2, A1, and A0 determine the 3 LSBs of the device
address (Figure 13). Connect A2, A1, and A0 to DVDD
for a high logic state or DGND for a low logic state.
Therefore, a maximum of eight MAX11014/MAX11015
devices can be connected on the same bus at one
time.
The MAX11014/MAX11015 continuously wait for a
START condition followed by its slave address. When
the device recognizes its slave address, it is ready to
accept or send data depending on bit 8, the R/Wbit.
High-Speed ModeAt power-up, the bus timing is set for fast mode (F/S
mode, up to 400kHz I2C clock), which limits interface
speed. Switch to high-speed mode (HS mode, up to
3.4MHz I2C clock) to increase interface speed. The
interface is capable of supporting slow (up to 100kHz),
fast (up to 400kHz), and high-speed (up to 3.4MHz)
protocols. See Figure 14.
SCL
SDANACK
ACK89
S = START.
ACK = ACKNOWLEDGE.
NACK = NOT ACKNOWLEDGE.
Figure 12. Acknowledge Bits
010A21A1A0R/WACK
SLAVE ADDRESS
SCL
SDA3456789
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF ADDRESS-SELECT INPUT PINS A2, A1, AND A0.
S = START.
ACK = ACKNOWLEDGE.
Figure 13. Slave Address Byte
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersTransfer from F/S mode to HS mode by addressing all
devices on the bus with the HS-mode master code
0000 1XXX (X = don’t care). After successfully receiv-
ing the HS-mode master code, the MAX11014/
MAX11015 issue a NACK, allowing SDA to be pulled
high for one cycle.
After the NACK, the MAX11014/MAX11015 operate in
HS mode. Send a repeated START followed by a slave
address to initiate HS-mode communication. If the master
generates a STOP condition, the MAX11014/MAX11015
return to F/S mode. Use a repeated START condition in
place of a STOP condition to leave the bus active and the
mode unchanged.
Command Byte/Data Bytes (Write Cycle)Begin a write cycle by issuing a START condition
(through the master), followed by 7 slave address bits
(Figure 13) and a write bit (R/W= 0). After writing the
8th bit, the MAX11014/MAX11015 (the slave) issue an
acknowledge signal by pulling SDA low for one clock.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 15 and
17, Table 1, and the Command Byte section. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
the command byte, write 2 data bytes, allowing for two
additional acknowledge signals after each byte. The
master ends the write cycle by issuing a STOP condition.
When operating in HS mode, a STOP condition returns
the bus to F/S mode. See the High-Speed Modesection.
The MAX11014/MAX11015’s internal conversion clock fre-
quency is 4.8MHz (typ), resulting in a typical conversion
time of 4.6µs. Figure 15 shows a complete write cycle.010XXXA
HS-MODE MASTER CODE
SCL
SDASr
S = START.
Sr = REPEATED START.
F/S MODEHS MODE
SLAVE TO MASTER
MASTER TO SLAVE
SLAVEADDRESSKKKK1COMMAND BYTE
P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS.
4-BYTE WRITE CYCLE
NUMBER OF BITS1
DATA BYTE1
DATA BYTE1
S = START.
ACK = ACKNOWLEDGE.
P = STOP.
Sr = REPEATED START.
Figure 14. F/S-Mode to HS-Mode Transfer
Figure 15. Write Cycle
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Command Byte/Data Bytes (Read Cycle)Begin a read cycle by issuing a START condition fol-
lowed by writing a 7-bit address (Figure 18) and a read
bit (R/W= 1). After writing the 8th bit, the
MAX11014/MAX11015 (the slave) issue an acknowl-
edge signal by pulling SDA low for one clock cycle.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 16, 18,
19, Table 1, and the Command Bytesection. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
writing the command byte, issue a repeated START
condition, write the slave address byte again, and write
a 9th bit for an acknowledge signal. After a third
acknowledge signal, read out the 2 bytes at SDA. After
reading the first byte, the master should send an
acknowledge bit. After reading the second byte, the
master should send a not-acknowledge bit followed by
a STOPsignal.
Default ReadsA standard I2C read command involves writing the
slave address, command byte, slave address byte
again, and then reading the data at SDA. This is
detailed in the 5-byte read cycle sequence in Figure
16. Read from the MAX11014/MAX11015 through the
default read command to avoid writing a command
byte and second slave address byte. See the default
read sequence in Figure 16.
Begin a default read cycle by writing the slave address
byte followed by an acknowledge bit. Read out the next
2 data bytes, with acknowledge bits from the master to
the slave following each byte. Continue to acknowledge
the data by sending acknowledge signals. After read-
ing the final byte, the master should send a not-
acknowledge bit followed by a STOPsignal. The
default read cycle reads out the data from the register
(located in Table 2) of the previously assigned com-
mand byte. See Figure 18. This default read feature is
useful for 2-wire reads to maximize the data throughput
without having the overhead of setting the slave
address and command byte each time.
Figure 16. Read Cycle
SLAVEADDRESSSLAVEADDRESS
SLAVE
ADDRESS1COMMAND BYTE
P OR Sr
P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS
5-BYTE READ CYCLE
NUMBER OF BITS
NUMBER OF BITS
DATA BYTE
DATA BYTE711S
DEFAULT READ CYCLE
DATA BYTEDATA BYTE811
SLAVE TO MASTER
MASTER TO SLAVECKCKCKCKCKACKACKACK
S = START.
ACK = ACKNOWLEDGE.
Sr = REPEATED START.
P = STOP.
NACK = NOT ACKNOWLEDGE.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersSCL
SDA
SDA
DIRECTIONA5A4A3A2A1A0R/WACK
OUTINC5C4C3C2C1C0
OUT
ACK
SCL
SDA
SDA
DIRECTION
D15D14D13D12D11D10D9D8ACK
OUTIND6D5D4D3D2D1D0
ACK
OUTIN
R/W
S = START.
ACK = ACKNOWLEDGE.
P = STOP.
Figure 17. MAX11014/MAX11015 I2C Write Timing
SCL
SDAD7D6D5D4D3D2D1D0NACKOUT
SDA
DIRECTION
SCL
SDAA6A5A4A3A2A1A0ACK
OUTIN
D15D14D13D12D11D10D9D8
ACK
SDA
DIRECTION
R/W
SCL
SDA
SDA
DIRECTIONA5A4A3A2A1A0R/WACK
OUTINC5C4C3C2C1C0
OUT
ACK
R/W
S = START.
ACK = ACKNOWLEDGE.
Sr = REPEATED START.
P = STOP.
NACK = NOT ACKNOWLEDGE.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Command ByteBegin a write or read to the MAX11014/MAX11015 by
writing a command byte at DIN/SDA. Set bit C7 to 1 for
a read operation. Set bit C7 to 0 for a write operation.
See Table 1. The remaining bits, C6–C0, determine the
register accessed by the command byte. Table 2 indi-
cates the register’s read/write access. C7 is the MSB of
the command byte and C0 is the LSB. Following the
command byte, write or read 2 data bytes to/from bits
D15–D0. D15 is the MSB of the 2 data bytes and D0 is
the LSB. See Figures 9, 10, 17, 18, and 19 and the
Register Descriptionssection.
SCL
SDAD7D6D5D4D3D2D1D0NACKOUT
S = START.
ACK = ACKNOWLEDGE.
NACK = NOT ACKNOWLEDGE.
P = STOP.
SDA
DIRECTION
SCL
SDA
SDA
DIRECTIONA5A4A3A2A1A0R/WACKINC5C4C3C2C1C0ACK
R/W
OUT, DATA FROM LAST READ COMMAND BYTE REGISTER
Figure 19. MAX11014/MAX11015 I2C Default Read Timing
24-BIT SERIAL INPUT WORD
COMMAND BYTEDATA BITS
MSBLSBR/WC6C5C4C3C2C1C0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Table 1. Input Command Bits
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
Register DescriptionsThe MAX11014/MAX11015 communicate between the
internal registers and external bus lines through the serial
interface. Table 1 details the command bits (C7–C0) and
the data bits (D15–D0) of the serial input word. Table 2
details the command byte and the subsequent register
accessed. Tables 3–27 detail the various read and write
internal registers and their power-on reset states.
On power-up, the MAX11014/MAX11015 are in full
HEX CODEREGISTER DESCRIPTIONMNEMONICWRITEREADADC ConversionADCCON62—
ALARM Flag RegisterALMFLAG—F8
Channel 1 DAC InputIPDAC148—
Channel 1 DAC Input and OutputTHRUDAC14A—
Channel 1 High GATE Voltage ALARM ThresholdVH128A8
Channel 1 High Sense Voltage ALARM ThresholdIH124A4
Channel 1 High Temperature ALARM ThresholdTH120A0
Channel 1 K ParameterUSRK144—
Channel 1 Low GATE Voltage ALARM ThresholdVL12AAA
Channel 1 Low Sense Voltage ALARM ThresholdIL126A6
Channel 1 Low Temperature ALARM ThresholdTL122A2
Channel 1 VSETVSET140—
Channel 2 DAC InputIPDAC24C—
Channel 2 DAC Input and OutputTHRUDAC24E—
Channel 2 High GATE Voltage ALARM ThresholdVH234B4
Channel 2 High Sense Voltage ALARM ThresholdIH230B0
Channel 2 High Temperature ALARM ThresholdTH22CAC
Channel 2 K ParameterUSRK246—
Channel 2 Low GATE Voltage ALARM ThresholdVL236B6
Channel 2 Low Sense Voltage ALARM ThresholdIL232B2
Channel 2 Low Temperature ALARM ThresholdTL22EAE
Channel 2 VSETVSET242—
First-In First-Out MemoryFIFO—80
Flag RegisterFLAG—F6
Hardware ALARM ConfigurationALMHCFG3CBC
Hardware ConfigurationHCFG38B8
LUT AddressLUTADD7A—
LUT DataLUTDAT7CFC
PGA Calibration ControlPGACAL5E—
ShutdownSHUT64—
Software ALARM ConfigurationALMSCFG3EBE
Software ClearSCLR74—
Software ConfigurationSCFG3ABA
Software Load DACLDAC66—
Table 2. Register Listing (see Appendix: Startup Code Examplefor sample startup
sequence)
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllerschange to normal power mode, write two commands to
the shutdown register. Set the FULLPD bit to 0 (other
bits in the shutdown register are ignored) on the first
command. A second command to this register acti-
vates the internal blocks.
TH1 and TH2 (Read/Write)Set the external channel 1 and channel 2 high tempera-
ture ALARM thresholds by writing command bytes 20h
and 2Ch, respectively. Following the command byte,
write 12 bits of data to bits D11–D0. Read the high tem-
perature channel 1 and channel 2 ALARM thresholds
by writing command bytes A0h and ACh, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Temper-
ature data must be written and read in two’s-comple-
ment format, with the LSB corresponding to +0.125°C.
See Table 3. The POR value of the high temperature
ALARM threshold registers is 0111 1111 1111, which
corresponds to +255.875°C. See Table 4 for examples
of channel 1/channel 2 high and low temperature
threshold settings. See Figures 25 and 27 for ALARM
examples.
TL1 and TL2 (Read/Write)Set the external channel 1 and channel 2 low tempera-
ture ALARM thresholds by writing command bytes 22h
and 2Eh, respectively. Following the command byte,
write 12 bits of data to bits D11–D0. Read the low tem-
perature channel 1 and channel 2 ALARM thresholds
by writing command bytes A2h and AEh, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Temper-
ature data must be written and read in two’s-comple-
ment format, with the LSB corresponding to +0.125°C.
See Table 5. The POR value of the low temperature
ALARM threshold registers is 1000 0000 0000, which
corresponds to -256.0°C. See Figures 25 and 27 for
ALARM examples.
IH1 and IH2 (Read/Write)Set the channel 1 and channel 2 high sense voltage
ALARM thresholds by writing command bytes 24h and
30h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the high sense
voltage channel 1 and channel 2 ALARM thresholds by
writing command bytes A4h and B0h, respectively.
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX011111111111
BIT VALUE
(°C)XXXXMSB
(sign)12864321684210.50.25LSB
TEMPERATURE
SETTING
DATA BITS D11–D0
(TWO’S COMPLEMENT)
-40°C1110 1100 0000
-1.625°C1111 1111 0011
0°C0000 0000 0000
+27.125°C0000 1101 1001
+105°C0011 0100 1000
Table 3. TH1 and TH2 (Read/Write)
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX100000000000
BIT VALUE
(°C)XXXXMSB
(sign)12864321684210.50.25LSB
Table 5. TL1 and TL2 (Read/Write)
Table 4. High/Low Temperature ALARM Threshold Examples
X = Don’t care.
X = Don’t care.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current ControllersFollowing the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Sense volt-
age data must be written and read in straight binary
format. See Table 6. The POR value of the high sense
voltage ALARM threshold registers is 1111 1111 1111.
See Figures 25 and 27 for ALARM examples.
The sense voltage is measured between RCS_+ and
RCS_-. A reading of 1111 1111 1111 corresponds to
VREFDAC/ 4. A reading of 0000 0000 0000 corre-
sponds to 0mV.
IL1 and IL2 (Read/Write)Set the channel 1 and channel 2 low sense voltage
ALARM thresholds by writing command bytes 26h and
32h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the low sense volt-
age channel 1 and channel 2 ALARM thresholds by
writing command bytes A6h and B2h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Sense volt-
age data must be written and read in straight binary
format. See Table 7. The POR value of the low sense
voltage ALARM threshold registers is 0000 0000 0000.
See Figures 25 and 27 for ALARM examples.
The sense voltage is measured between RCS_+ and
RCS_-. A reading of 1111 1111 1111 corresponds to
VREFDAC/ 4. A reading of 0000 0000 0000 corre-
sponds to 0mV.
VH1 and VH2 (Read/Write)Set the channel 1 and channel 2 high GATE voltage
ALARM thresholds by writing command bytes 28h and
34h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the high GATE
voltage channel 1 and channel 2 ALARM thresholds by
writing command bytes A8h and B4h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Voltage data
must be written and read in straight binary format. See
Table 8. The POR value of the high GATE voltage
ALARM threshold registers is 1111 1111 1111. See
Figure 7 for a GATE voltage example. See Figures 25
and 27 for ALARM examples.
VL1 and VL2 (Read/Write)Set the channel 1 and channel 2 low GATE voltage
ALARM thresholds by writing command bytes 2Ah and
36h, respectively. Following the command byte, write
12 bits of data to bits D11–D0. Read the low GATE volt-
age channel 1 and channel 2 ALARM thresholds by
writing command bytes AAh and B6h, respectively.
Following the command byte, read 12 bits of data from
bits D11–D0. Bits D15–D12 are don’t care. Voltage data
must be written and read in straight binary format. See
Table 9. The POR value of the low GATE voltage
ALARM threshold registers is 0000 0000 0000. See
Figure 7 for a GATE voltage example. See Figures 25
Table 7. IL1 and IL2 (Read/Write)
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX000000000000
BIT VALUEXXXXMSB——————————LSB
Table 8. VH1 and VH2 (Read/Write)
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX111111111111
BIT VALUEXXXXMSB——————————LSB
Table 6. IH1 and IH2 (Read/Write)
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX111111111111
BIT VALUEXXXXMSB——————————LSB
X = Don’t care.
X = Don’t care.
X = Don’t care.
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
HCFG (Read/Write)Select each channel’s maximum GATE voltage, clock
mode, ADC monitoring, DAC and ADC reference
modes by setting bits D11–D0 in the hardware configu-
ration register. Set the command byte to 38h to write to
the hardware configuration register. Set the command
byte to B8h to read from the hardware configuration
register. Bits D15–D12 are don’t care. Set the
CH2OCM1/0 bits, D11 and D10, to determine the maxi-
mum positive GATE2 output voltage. Set the
CH1OCM1/0 bits, D9 and D8, to determine the maxi-
mum positive GATE1 output voltage. See Table 10.
Set the ADCMON bit, D6, to 1 to load the ADC results
into the FIFO. Set ADCMON to 0 to not load ADC
results into the FIFO. Set the CKSEL1/0 bits, D5 and
D4, to determine the conversion and acquisition timing
clock modes. See Table 10b. Also, see the Internally
Timed AcquisitionsandConversions andthe Externally
Timed AcquisitionsandConversionssections. Set the
ADCREF1/0 bits, D3 and D2, to determine the ADC ref-
erence source. See Table 10c. Set the DACREF1/0 bits,
D1 and D0, to determine the DAC reference source.
See Table 10d.
SCFG (Read/Write)Write to the software configuration register to determine
whether a VDAC(CODE)calculation value is loaded to
the DAC input register or DAC input and output regis-
ter. This register also sets the control modes for the K
parameter and temperature lookup values in the
VDAC(CODE)calculation. Set the command byte to 3Ah
to write to the software configuration register. Set the
command byte to BAh to read from the software config-
uration register.
BITD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
RESET
STATEXXXX000000000000
BIT VALUEXXXXMSB——————————LSB
BIT NAMEDATA BITRESET STATEFUNCTIOND15–D12XDon’t care.
CH2OCM1D110
CH2OCM0D100Maximum GATE2 voltage control bits.
CH1OCM1D90
CH1OCM0D80Maximum GATE1 voltage control bits.D7XDon’t care.
ADCMOND60
ADC monitor bit. Set to 1 to load ADC results into the FIFO. Set to 0 to not
load any ADC results into the FIFO. The value of ADCMON does NOT
affect whether the results from any particular ADC conversion are
checked against ALARM limits or examined for changes to the
VDAC(CODE) equations.
CKSEL1D50
CKSEL0D40Clock mode and CNVST configuration bits.
ADCREF1D30
ADCREF0D20ADC reference select bits.
DACREF1D10
DACREF0D00DAC reference select bits.
X = Don’t care.
Table 9. VL1 and VL2 (Read/Write)
Table 10. HCFG (Read/Write)
