MAX1091BCEI ,250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1091/MAX1093 low-power, 10-bit analog-to- 10-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1092ACEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceApplications D6 3 22 REFD5 4 21 REFADJIndustrial Control Systems Data LoggingD4 5 20 GNDEnergy Mana ..
MAX1092AEEG ,400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel InterfaceApplications D6 3 22 REFD5 4 21 REFADJIndustrial Control Systems Data LoggingD4 5 20 GNDEnergy Mana ..
MAX1092BCEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel Interfaceapplications or for other circuits withdemanding power consumption and space require- Pin Configura ..
MAX1092BEEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at ..
MAX1092BEEG+ ,400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at ..
MAX339EPE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersMAX338/MAX33919-0272; Rev 4; 4/128-Channel/Dual 4-Channel,Low-Leakage, CMOS Analog Multiplexers____ ..
MAX339ESE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX339ESE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.MAX338/MAX33919-0272; Rev 0; 8/948-Channel/Dual 4-Channel,Low-Leakage, CMOS Analog Multiplexers____ ..
MAX339ESE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.ApplicationsMAX338MJE -55°C to +125°C 16 CERDIP**Data-Acquisition Systems Sample-and-Hold CircuitsO ..
MAX339ESE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersMAX338/MAX33919-0272; Rev 4; 4/128-Channel/Dual 4-Channel,Low-Leakage, CMOS Analog Multiplexers____ ..
MAX339ETE ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersApplications (5mm x 5mm)Data-Acquisition Systems Sample-and-Hold CircuitsOrdering Information conti ..
MAX1091ACEI-MAX1091BCEI-MAX1093ACEG-MAX1093BCEG
250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel Interface
General DescriptionThe MAX1091/MAX1093 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a VLOGIC
pin that allows them to interface directly with a +1.8V to
+3.6V digital supply.
Power consumption is only 5.7mW (VDD = VLOGIC) at
the maximum sampling rate of 250ksps. Two software-
selectable power-down modes enable the MAX1091/
MAX1093 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can
cut supply current to under 10µA at reduced sampling
rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1091 has
eight input channels and the MAX1093 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power com-
bined with ease of use and small package size make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1091 is available in a 28-pin QSOP package,
while the MAX1093 is available in a 24-pin QSOP. For
pin-compatible +5V, 10-bitversions, refer to the
MAX1090/MAX1092 data sheet.
ApplicationsIndustrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouch Screens
Features10-Bit Resolution, ±0.5LSB Linearity+3V Single-Supply OperationUser-Adjustable Logic Level (+1.8V to +3.6V)Internal +2.5V ReferenceSoftware-Configurable, Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1091)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1093)Software-Configurable, Unipolar/Bipolar InputsLow Power: 1.9mA (250ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)Internal 3MHz Full-Power Bandwidth Track/HoldByte-Wide Parallel (8+2) InterfaceSmall Footprint: 28-Pin QSOP (MAX1091)
24-Pin QSOP (MAX1093)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
Ordering Information
Pin Configurations
Ordering Information continued at end of data sheet.Typical Operating Circuits appear at end of data sheet.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
VLOGICto GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND ................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D9, INT) to GND.....-0.3V to (VLOGIC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C) ...........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C) .........667mW
Operating Temperature Ranges
MAX1091_C_ _/MAX1093_C_ _...........................0°C to +70°C
MAX1091_E_ _/MAX1093_E_ _........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
Note 1:Tested at VDD= +3V, COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:Offset nulled.
Note 4:On channel is grounded; sine wave applied to off channels.
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)(VDD= VLOGIC= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK= 4.8MHz (50% duty
cycle), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics(VDD= VLOGIC= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel InterfaceINTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1291/3 toc11
TEMPERATURE (°C)
REF
(V)
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1091/93 TOC12
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR
vs. TEMPERATURE
MAX1091/93 TOC13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1291/3 toc14
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1291/3 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1291/3 toc16
VDD (V)
ILOGIC
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
max1291/3 toc17
TEMPERATURE (°C)
ILOGIC
-401035-156085
ypical Operating Characteristics (continued)(VDD= VLOGIC= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA= +25°C, unless otherwise noted.)
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
Detailed Description
Converter OperationThe MAX1091/MAX1093 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 10-bit digital output. Their parallel 8+2 out-
put format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1091/MAX1093.
Single-Ended and
Pseudo-Differential OperationThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1091
(Figure 3a) and to CH0–CH3 for the MAX1093 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
either of the analog inputs. This configuration is pseu-
do-differential in that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5LSB
(±0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLDas a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 10-bit resolution. This action is equivalent to
transferring a 12pF[(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1091/MAX1093
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the
supplies by more than 50mV, limit the forward-bias
input current to 4mA.
Track/HoldThe MAX1091/MAX1093 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that in internal clock
mode this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative input (-), and the difference of (IN+) - (IN-)is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ= 7 (RS+ RIN) CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the ADC’s input capacitance. Source impedances
below 3kΩhave no significant impact on the MAX1091/
MAX1093’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX1091/MAX1093 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADCs sampling rate. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1091/MAX1093 for either unipolar or bipolar opera-
tion. A write pulse (WR+ CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
250ksps, +3V, 8-/4-Channel,10-Bit ADCs
with +2.5V Reference and Parallel Interface
