MAX1062CCUB ,14-Bit / %V / 200ksps ADC with 10A ShutdownApplicationsMotor ControlTEMP. PIN- INLPARTRANGE PACKAGE (LSB)Industrial Process ControlMAX1062ACUB ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceApplications Ordering InformationTemperature Cable/Harness Tester PIN-PART TEMP RANGE INLSensor/Mon ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceFeaturesThe MAX1065/MAX1066 14-bit, low-power successive♦ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1 ..
MAX1066AEUP+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceELECTRICAL CHARACTERISTICS(AV = DV = 5V, external reference = 4.096V, C = 1µF, C = 0.1µF, T = T to ..
MAX1069ACUD ,58.6ksps / 14-Bit / 2-Wire Serial ADCApplicationsMAX1069ACUD 0°C to +70°C 14 TSSOP ±1Medical InstrumentsMAX1069BCUD 0°C to +70°C 14 TSSO ..
MAX106CHC ,5V / 600Msps / 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold AmplifierFeaturesThe MAX106 PECL-compatible, 600Msps, 8-bit analog-to-' 600Msps Conversion Ratedigital conve ..
MAX3390EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3391EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPapplications that route sig- MAX3372EEKA-T -40°C to +85°C 8 SOT23-8nals externally. The MAX3372E/MA ..
MAX3391EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications2SPI™, MICROWIRE™, and I C™ LevelI/O V 2 1 8 I/O V 1CC CCTranslation Low-Voltage ASIC L ..
MAX3391EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications+® 2SPI, MICROWIRE , and I C Level I/O V 1 1 14 VL CCTranslation I/O V 2 2 13 I/0 V 1L ..
MAX3391EEUD+T ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPFeaturesThe MAX3372E–MAX3379E and MAX3390E–MAX3393E♦ Guaranteed Data Rate Options±15kV ESD-protecte ..
MAX3392EEBC ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX1062CCUB
14-Bit / %V / 200ksps ADC with 10A Shutdown
General DescriptionThe MAX1062 low-power, 14-bit analog-to-digital con-
verter (ADC) features a successive approximation ADC,
automatic power-down, fast 1.1µs wake-up, and a high-
speed SPI™/QSPI™/MICROWIRE™-compatible inter-
face. The MAX1062 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with 2.7V to 5.25V digital logic.
At the maximum sampling rate of 200ksps, the
MAX1062 consumes only 2.5mA. Power consumption is
only 12.5mW (AVDD= DVDD= 5V) at a 200ksps (max)
sampling rate. AutoShutdown™ reduces supply current
to 130µA at 10ksps and to less than 10µA at reduced
sampling rates.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
µMAX) make the MAX1062 ideal for battery-powered
and data-acquisition applications or for other circuits
with demanding power consumption and space
requirements.
ApplicationsMotor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
Features14-Bit Resolution, 1LSB DNL+5V Single-Supply OperationAdjustable Logic Level (2.7V to 5.25V)Input Voltage Range: 0 to VREFInternal Track/Hold, 4MHz Input BandwidthSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSmall 10-Pin µMAX PackageLow Power
2.5mA at 200ksps
130µA at 10ksps
0.1µA in Power-Down Mode
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Configuration
Ordering Information19-2203; Rev 0; 10/01
Functional Diagram appears at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND........................................................-0.3V to +6V
DVDDto DGND........................................................-0.3V to +6V
DGND to AGND....................................................-0.3V to +0.3V
AIN, REF to AGND...................................-0.3V to (AVDD + 0.3V)
SCLK, CSto DGND..................................................-0.3V to +6V
DOUT to DGND.......................................-0.3V to (DVDD + 0.3V)
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW
Operating Temperature Ranges
MAX1062_CUB .................................................0°C to +70°C
MAX1062_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Note 1:AVDD= DVDD= +5V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset and reference errors nulled.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
MAX1062 TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(AVDD= +4.75V to +5.25V, DVDD= +2.7V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF=
+4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
INL vs. OUTPUT CODEMAX1062 toc01
OUTPUT CODE
INL (LSB)
DNL vs. OUTPUT CODE
MAX1062 toc02
OUTPUT CODE
DNL (LSB)
MAX1062 FFT
MAX1062 toc03
FREQUENCY (kHz)
MAGNITUDE (dB)
SINAD VS. FREQUENCY
MAX1062 toc04
FREQUENCY (kHz)
SINAD (dB)
SFDR VS. FREQUENCY
MAX1062 toc05
FREQUENCY (kHz)
SFDR (dB)
THD VS. FREQUENCY
MAX1062 toc06
FREQUENCY (kHz)
THD (dB)
SUPPLY CURRENT
VS. CONVERSION RATE
MAX1062 toc07
CONVERSION RATE (kHz)
SUPPLY CURRENT (mA)
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
MAX1062 toc08
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT VS. TEMPERATURE
MAX1062 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
Typical Operating Characteristics(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, VREF= +4.096V, TA= 25°C, unless otherwise noted.)
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, VREF= +4.096V, TA= 25°C, unless otherwise noted.)
Detailed DescriptionThe MAX1062 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 14-bit out-
put. Figure 4 shows the MAX1062 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
The MAX1062 has two power modes: normal and shut-
down. Driving CShigh places the MAX1062 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CSlow places the MAX1062 in normal operating
mode. Falling edges on CSinitiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Analog InputFigure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
Track-and-Hold (T/H)In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog
input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDACrepresents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDACto the input
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ= 11(RS+ RIN) x 35pF
where RIN= 800Ω, RS= the input signal’s source
impedance, and tACQis never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
quickly.
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Description
MAX1062
Input BandwidthThe ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to AVDDand/or AGND, allow the input to swing
from AGND - 0.3V to AVDD+ 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
14-Bit, +5V, 200ksps ADC with 10µA ShutdownFigure 3. Detailed Serial Interface Timing
Figure 4. Typical Operating Circuit
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
Digital Interface
Initialization after Power-Up and
Starting a ConversionThe digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1062 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1062 in the fully powered mode.
To start a conversion, pull CSlow. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at
DOUT.
Timing and ControlConversion-start and data-read operations are con-
trolled by the CSand SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
Note:Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in fre-
quency, duty cycle, or other aspects of the clock sig-
nal’s shape result in changing offset.
A CSfalling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros, 14 data bits, and 2 sub-bits (S1 and S0). Extra
clock pulses occurring after the conversion result has
been clocked out, and prior to the rising edge of CS,
produce trailing zeros at DOUT and have no effect on
the converter operation.
Force CShigh after reading the conversion’s LSB to
reset the internal registers and place the MAX1062 in
shutdown. For maximum throughput, force CSlow
again to initiate the next conversion immediately after
the specified minimum time (tCSW).
Note:Forcing CShigh in the middle of a conversion
immediately aborts the conversion and places the
MAX1062 in shutdown.
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
