MAX1062BCUB+ ,14-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with 2.7V to 5.25V digital logic.♦ I ..
MAX1062CCUB ,14-Bit / %V / 200ksps ADC with 10A ShutdownApplicationsMotor ControlTEMP. PIN- INLPARTRANGE PACKAGE (LSB)Industrial Process ControlMAX1062ACUB ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceApplications Ordering InformationTemperature Cable/Harness Tester PIN-PART TEMP RANGE INLSensor/Mon ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceFeaturesThe MAX1065/MAX1066 14-bit, low-power successive♦ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1 ..
MAX1066AEUP+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceELECTRICAL CHARACTERISTICS(AV = DV = 5V, external reference = 4.096V, C = 1µF, C = 0.1µF, T = T to ..
MAX1069ACUD ,58.6ksps / 14-Bit / 2-Wire Serial ADCApplicationsMAX1069ACUD 0°C to +70°C 14 TSSOP ±1Medical InstrumentsMAX1069BCUD 0°C to +70°C 14 TSSO ..
MAX3390EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPMAX3372E–MAX3379E/MAX3390E–MAX3393E19-2328; Rev 3; 9/03±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad ..
MAX3390EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3391EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPapplications that route sig- MAX3372EEKA-T -40°C to +85°C 8 SOT23-8nals externally. The MAX3372E/MA ..
MAX3391EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications2SPI™, MICROWIRE™, and I C™ LevelI/O V 2 1 8 I/O V 1CC CCTranslation Low-Voltage ASIC L ..
MAX3391EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications+® 2SPI, MICROWIRE , and I C Level I/O V 1 1 14 VL CCTranslation I/O V 2 2 13 I/0 V 1L ..
MAX3391EEUD+T ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPFeaturesThe MAX3372E–MAX3379E and MAX3390E–MAX3393E♦ Guaranteed Data Rate Options±15kV ESD-protecte ..
MAX1062ACUB+-MAX1062BCUB+
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
General DescriptionThe MAX1062 low-power, 14-bit analog-to-digital con-
verter (ADC) features a successive approximation ADC,
automatic power-down, fast 1.1µs wake-up, and a high-
speed SPI™/QSPI™/MICROWIRE™-compatible inter-
face. The MAX1062 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with 2.7V to 5.25V digital logic.
At the maximum sampling rate of 200ksps, the
MAX1062 consumes typically 2.75mA. Power con-
sumption is typically 13.75mW (AVDD= DVDD= 5V) at
a 200ksps (max) sampling rate. AutoShutdown™
reduces supply current to 140µA at 10ksps and to less
than 10µA at reduced sampling rates.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
µMAX®) make the MAX1062 ideal for battery-powered
and data-acquisition applications or for other circuits
with demanding power consumption and space
requirements.
ApplicationsMotor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
Features14-Bit Resolution, 1LSB DNL+5V Single-Supply OperationAdjustable Logic Level (2.7V to 5.25V)Input Voltage Range: 0 to VREFInternal Track/Hold, 4MHz Input BandwidthSPI/QSPI/MICROWIRE-Compatible Serial InterfaceSmall 10-Pin µMAX PackageLow Power
2.75mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA ShutdownAIN
AGND
DVDD
DGNDCS
AGND
AVDD
REF
MAX1062
µMAX
TOP VIEW
DOUTSCLK
Pin Configuration
Ordering Information19-2203; Rev 1; 5/09
Functional Diagram appears at end of data sheet.
PARTTEMP.
RANGE
PIN-
PACKAGE
INL
(LSB)MAX1062ACUB0°C to 70°C10 µMAX±1
MAX1062BCUB0°C to 70°C10 µMAX±2
MAX1062CCUB0°C to 70°C10 µMAX±3
MAX1062AEUB-40°C to 85°C10 µMAX±1
MAX1062BEUB-40°C to 85°C10 µMAX±2
MAX1062CEUB-40°C to 85°C10 µMAX±3
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND........................................................-0.3V to +6V
DVDDto DGND........................................................-0.3V to +6V
DGND to AGND....................................................-0.3V to +0.3V
AIN, REF to AGND...................................-0.3V to (AVDD + 0.3V)
SCLK, CSto DGND..................................................-0.3V to +6V
DOUT to DGND.......................................-0.3V to (DVDD + 0.3V)
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW
Operating Temperature Ranges
MAX1062_CUB .................................................0°C to +70°C
MAX1062_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (NOTE 1)Resolution14Bits
MAX1062A±1
MAX1062B±2Relative Accuracy (Note 2)INL
MAX1062C±3
LSB
Differential NonlinearityDNLNo missing codes over temperature±0.5±1LSB
Transition NoiseRMS noise±0.32LSBRMS
Offset Error0.21mV
Gain Error (Note 3)±0.002±0.01%FSR
Offset Drift0.4ppm/oC
Gain Drift (Note 3)0.2ppm/oC
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096Vp-p) (Note 1)Signal-to-Noise Plus DistortionSINAD8184dB
Signal-to-Noise RatioSNR8284dB
Total Harmonic DistortionTHD-99-86dB
Spurious-Free Dynamic RangeSFDR87101dB
Full-Power Bandwidth-3dB point4MHz
Full-Linear BandwidthSINAD > 81dB20kHz
CONVERSION RATEConversion Time (Note 4)tCONV5240µs
Serial Clock FrequencyfSCLK0.14.8MHz
Aperture Delay15ns
Aperture Jitter<50ps
Sample RatefSfSCLK / 24200ksps
Track/Hold Acquisition TimetACQ1.1µs
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG INPUT (AIN)Input RangeVAIN0VREFV
Input CapacitanceCAIN40pF
EXTERNAL REFERENCEInput Voltage RangeVREF3.8AVDDV
VREF = 4.096V, fSCLK = 4.8MHz100
VREF = 4.096V, SCLK idle0.01Input CurrentIREF
CS = DVDD, SCLK idle0.01
DIGITAL INPUTS (SCLK, CS)Input High VoltageVIHDVDD = +2.7V to +5.25V0.7 x
DVDDV
Input Low VoltageVILDVDD = +2.7V to +5.25V0.3 x
DVDDV
Input Leakage CurrentIINVIN = 0 to DVDD±0.1±1µA
Input HysteresisVHYST0.2V
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT)Output High VoltageVOHISOURCE = 0.5mA, DVDD = +2.7V to +5.25VDVDD -
0.25VV
ISINK = 10mA, DVDD = +4.75V to +5.25V0.7Output Low VoltageVOLISINK = 1.6mA, DVDD = +2.7V to +5.25V0.4V
Three-State Output Leakage
CurrentILCS = DVDD±0.1±10µA
Three-State Output CapacitanceCOUTCS = DVDD15pF
POWER SUPPLIESAnalog SupplyAVDD4.755.25V
Digital SupplyDVDD2.75.25V
200ksps2.753.25
100ksps1.4
10ksps0.14Analog Supply CurrentIAVDDCS = DGND
1ksps0.014
200ksps0.61.0
100ksps0.3
10ksps0.03Digital Supply CurrentIDVDD
CS = DGND,
DOUT = all
zeros
1ksps0.003
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Note 1:AVDD= DVDD= +5V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset and reference errors nulled.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
MAX1062 TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.1µs
SCLK to DOUT ValidtDOCDOUT = 50pF50ns
CS Fall to DOUT EnabletDVCDOUT = 50pF80ns
CS Rise to DOUT DisabletTRCDOUT = 50pF80ns
CS Pulse WidthtCSW50ns
CS Fall to SCLK Rise SetuptCSS100ns
CS Rise to SCLK Rise HoldtCSH0ns
SCLK High Pulse WidthtCH65ns
SCLK Low Pulse WidthtCL65ns
SCLK PeriodtCP208ns
(AVDD= +4.75V to +5.25V, DVDD= +2.7V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF=
+4.096V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.1µs
SCLK to DOUT ValidtDOCDOUT = 50pF100ns
CS Fall to DOUT EnabletDVCDOUT = 50pF100ns
CS Rise to DOUT DisabletTRCDOUT = 50pF80ns
CS Pulse WidthtCSW50ns
CS Fall to SCLK Rise SetuptCSS100ns
CS Rise to SCLK Rise HoldtCSH0ns
SCLK High Pulse WidthtCH65ns
SCLK Low Pulse WidthtCL65ns
SCLK PeriodtCP208ns
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +4.75V to +5.25V, fSCLK= 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF= +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSShutdown Supply CurrentIAVDD +
IDVDDCS = DVDD, SCLK = idle0.110µA
Power-Supply Rejection Ratio
(Note 5)PSRRAVDD = DVDD = +4.75V to +5.25V, full-scale
input68dB
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
INL vs. OUTPUT CODEMAX1062 toc01
OUTPUT CODE
INL (LSB)
DNL vs. OUTPUT CODE
MAX1062 toc02
OUTPUT CODE
DNL (LSB)
MAX1062 FFT
MAX1062 toc03
FREQUENCY (kHz)
MAGNITUDE (dB)
SINAD VS. FREQUENCY
MAX1062 toc04
FREQUENCY (kHz)
SINAD (dB)
fSAMPLE = 200kHz
SFDR VS. FREQUENCY
MAX1062 toc05
FREQUENCY (kHz)
SFDR (dB)
fSAMPLE = 200kHz
THD VS. FREQUENCY
MAX1062 toc06
FREQUENCY (kHz)
THD (dB)
fSAMPLE = 200kHz
SUPPLY CURRENT
VS. CONVERSION RATE
MAX1062 toc07
CONVERSION RATE (kHz)
SUPPLY CURRENT (mA)
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
MAX1062 toc08
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT VS. TEMPERATURE
MAX1062 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
AVDD = DVDD= +5V
Typical Operating Characteristics(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, VREF= +4.096V, TA= 25°C, unless otherwise noted.)
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)(AVDD= DVDD= +5V, fSCLK= 4.8MHz, CLOAD= 50pF, VREF= +4.096V, TA= 25°C, unless otherwise noted.)
MAX1062 toc10
SUPPLY VOLTAGE (V)
SHDN
(nA)
SHUTDOWN SUPPLY CURRENT
VS. SUPPLY VOLTAGESHUTDOWN SUPPLY CURRENT
VS. TEMPERATURE
MAX1062 toc11
TEMPERATURE (°C)
ISHDN
(nA)
AVDD = DVDD = +5V
OFFSET ERROR
VS. ANALOG SUPPLY VOLTAGE
MAX1062 toc12
SUPPLY VOLTAGE (V)
OFFSET ERROR (
OFFSET ERROR VS. TEMPERATURE
MAX1062 toc13
TEMPERATURE (°C)
OFFSET ERROR (
GAIN ERROR
VS. ANALOG SUPPLY VOLTAGE
MAX1062 toc14
GAIN ERROR (%)
GAIN ERROR VS. TEMPERATURE
MAX1062 toc15
GAIN ERROR (%)
Detailed DescriptionThe MAX1062 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 14-bit out-
put. Figure 4 shows the MAX1062 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
The MAX1062 has two power modes: normal and shut-
down. Driving CShigh places the MAX1062 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CSlow places the MAX1062 in normal operating
mode. Falling edges on CSinitiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Analog InputFigure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
Track-and-Hold (T/H)In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog
input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDACrepresents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDACto the input
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ= 11(RS+ RIN) x 35pF
where RIN= 800Ω, RS= the input signal’s source
impedance, and tACQis never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Description
PINNAMEFUNCTIONREFExternal Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF
capacitor.
2AVDDAnalog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor.
3, 9AGNDAnalog Ground. Connect pins 3 and 9 together. Place star ground at pin 3.CS
Active Low Chip Select Input. Forcing CS high places the MAX1062 in shutdown with a typical
current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.SCLKSerial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
6DOUTSerial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS
is high.DGNDDigital Ground
8DVDDDigital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.AINAnalog Input
MAX1062
Input BandwidthThe ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to AVDDand/or AGND, allow the input to swing
from AGND - 0.3V to AVDD+ 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
14-Bit, +5V, 200ksps ADC with 10µA ShutdownSCLK
DOUT
tCSStCHtCL
tDV
tCSH
tCSW
tTRtDO
tCP
Figure 3. Detailed Serial Interface Timing
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLKAIN
VREF
+5V
+5V
4.7μF
0.1μF
0.1μF
GND
MAX1062
DOUT
a) VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
1mA
DGNDDGND
CLOAD = 50pFCLOAD = 50pF
VDD
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
DOUT
a) VOH TO HIGH-Zb) VOL TO HIGH-Z
DOUT
1mA
1mA
DGNDDGND
CLOAD = 50pFCLOAD = 50pF
VDD
Figure 2. Load Circuits for DOUT Disable Time
Digital Interface
Initialization after Power-Up and
Starting a ConversionThe digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1062 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1062 in the fully powered mode.
To start a conversion, pull CSlow. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at
DOUT.
Timing and ControlConversion-start and data-read operations are con-
trolled by the CSand SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
Note:Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in fre-
quency, duty cycle, or other aspects of the clock sig-
nal’s shape result in changing offset. CSfalling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros, 14 data bits, and 2 sub-bits (S1 and S0). Extra
clock pulses occurring after the conversion result has
been clocked out, and prior to the rising edge of CS,
produce trailing zeros at DOUT and have no effect on
the converter operation.
Force CShigh after reading the conversion’s LSB to
reset the internal registers and place the MAX1062 in
shutdown. For maximum throughput, force CSlow
again to initiate the next conversion immediately after
the specified minimum time (tCSW).
Note:Forcing CShigh in the middle of a conversion
immediately aborts the conversion and places the
MAX1062 in shutdown.
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA ShutdownCDAC 32pFRIN
800Ω
HOLD
HOLDCSWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTOZERO
RAIL
TRACK
TRACK
Figure 5. Equivalent Input Circuit
SCLK201624121486
DOUTD13D12D11D10D9D8D7S1S0D6D3D2D1D0D5D4
tCSH
tTR
tDOtACQ
tCSS
tCH
tCL
tDN
Figure 6. External Timing Diagram
