MAX105ECS ,Dual / 6-Bit / 800Msps ADC with On-Chip / Wideband Input AmplifierFeaturesThe MAX105 is a dual, 6-bit, analog-to-digital converter Two Matched 6-Bit, 800Msps ADCs(A ..
MAX105ECS+ ,Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX105 is a dual, 6-bit, analog-to-digital converter♦ Two Matched 6-Bit, 800Msps ADCs(A ..
MAX1062ACUB+ ,14-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1062BCUB+ ,14-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with 2.7V to 5.25V digital logic.♦ I ..
MAX1062CCUB ,14-Bit / %V / 200ksps ADC with 10A ShutdownApplicationsMotor ControlTEMP. PIN- INLPARTRANGE PACKAGE (LSB)Industrial Process ControlMAX1062ACUB ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceApplications Ordering InformationTemperature Cable/Harness Tester PIN-PART TEMP RANGE INLSensor/Mon ..
MAX338CSE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX338EPE ,8-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX338ESE ,8-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX338ESE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX3390EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPMAX3372E–MAX3379E/MAX3390E–MAX3393E19-2328; Rev 3; 9/03±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad ..
MAX3390EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX105ECS
Dual / 6-Bit / 800Msps ADC with On-Chip / Wideband Input Amplifier
General DescriptionThe MAX105 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of
in-phase (I) and quadrature (Q) baseband signals. The
MAX105 converts the analog signals of both I and Q
components to digital outputs at 800Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 200MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX105 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.4dB signal-to-noise
plus distortion (SINAD) with a 200MHz analog input sig-
nal and a sampling speed of 800MHz. A fully differen-
tial comparator design and encoding circuits reduce
out-of-sequence errors, and ensure excellent
metastable performance of only one error per 1016 clock
cycles.
In addition, the MAX105 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX105 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a lower-speed, 400Msps version of the
MAX105, please refer to the MAX107 data sheet.
ApplicationsVSAT Receivers
WLANs
Test Instrumentation
Communications Systems
FeaturesTwo Matched 6-Bit, 800Msps ADCsExcellent Dynamic Performance
36.4dB SINAD at fIN≈
200MHz and
fCLK≈
800MHz Typical INL and DNL: ±0.25LSB Channel-to-Channel Phase Matching: ±0.2°Channel-to-Channel Gain Matching: ±0.04dB6:12 Demultiplexer reduces the Data Rates to
400MHzLow Error Rate: 1016Metastable States at
800MspsLVDS Digital Outputs in Two’s Complement
Format
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
Block Diagram19-2006; Rev 0; 5/01
Ordering Information
Pin Configuration appears at end of data sheet.
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V
OVCCI and OVCCQ to OGND...................................-0.3V to +4V
AGND to OGND...................................................-0.3V to +0.3V
P0I±to P5I±and A0I±to A5I±
DREADY+, DREADY- to OGNDI.............-0.3V to OVCCI+0.3V
P0Q±to P5Q±, A0Q±to A5Q±
DOR+ and DOR- to OGNDQ................-0.3V to OVCCQ+0.3V
REF to AGNDR...........................................-0.3V to AVCCR+0.3V
Differential Voltage Between INI+ and INI-....................-2V, +2V
Differential Voltage Between INQ+ and INQ-.................-2V, +2V
Differential Voltage Between CLK+ and CLK-...............-2V, +2V
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W
Operating Temperature Range
MAX105ECS.....................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead temperature (soldering, 10s)..................................+300°C
ELECTRICAL CHARACTERISTICS(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
Note 1:NL and DNL is measured using a sine-histogram method.
Note 2:Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3:Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input
voltage level does not matter.
Note 4:The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting
algorithm (e.g. FFT).
Note 5:Guaranteed by design and characterization.
Note 6:Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-
mode voltage expressed in dB.
Note 7:Measured with analog power supplies tied to the same potential.
Note 8:Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9:The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10:Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11:Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12:Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of fIN= 200.0180 MHz.
Note 13:Measured with a differential probe, 1pF capacitance.
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifierypical Operating Characteristics(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input AmplifierTHD vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc12
ANALOG INPUT POWER (dB FS)
THD (dB)
SNR vs. TEMPERATURE
MAX105 toc14
TEMPERATURE (°C)
SNR (dB)
SNR vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc10
ANALOG INPUT POWER (dB FS)
SNR (dB)
SINAD vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc11
ANALOG INPUT POWER (dB FS)
SINAD (dB)
SFDR vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc13
ANALOG INPUT POWER (dB FS)
SFDR (dB)
SINAD vs. TEMPERATURE
MAX105 toc15
TEMPERATURE (°C)
SINAD (dB)
THD vs. TEMPERATURE
MAX toc16
TEMPERATURE (°C)
THD (dB)
SFDR vs. TEMPERATURE
MAX105 toc17
TEMPERATURE (°C)
SFDR (dB)
SNR vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc18
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
Typical Operating Characteristics (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input AmplifierSINAD vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc19
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
THD vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc20
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
ENOB vs. ANALOG SUPPLY VOLTAGE,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc21
ANALOG SUPPLY VOLTAGE (V)
ENOB (Bits)
SFDR vs. ANALOG SUPPLY VOLTAGE,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc22
ANALOG SUPPLY VOLTAGE (V)
SFDR (dB)
INL vs. DIGITAL OUTPUT CODE
MAX105 toc23
DIGITAL OUTPUT CODE
INL (LSB)
DNL vs. DIGITAL OUTPUT CODE
MAX105 toc24
DIGITAL OUTPUT CODE
DNL (LSB)
REFERENCE VOLTAGE vs. ANALOG
SUPPLY VOLTAGE
MAX toc25
ANALOG SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
ANALOG SUPPLY CURRENT vs.
ANALOG SUPPLY VOLTAGE
MAX105 toc26
ANALOG SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
MAX105 toc27
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
Typical Operating Characteristics (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
Detailed DescriptionThe MAX105 is a dual, +5V, 6-bit, 800Msps flash ana-
log-to-digital converter (ADC), designed for high-
speed, high-bandwidth I&Q digitizing. Each ADC
(Figure 1) employs a fully differential, wide bandwidth
input stage, 6-bit quantizers and a unique encoding
scheme to limit metastable states to typically one error
per 1016 clock cycles, with no error exceeding a maxi-
mum of 1LSB. An integrated 6:12 output demultiplexer
simplifies interfacing to the part by reducing the output
data rate to one-half the sampling clock rate. The
MAX105 outputs data in LVDS two’s complement for-
mat.
When clocked at 800Msps, the MAX105 provides a typ-
ical signal-to-noise plus distortion (SINAD) of 36.4dB
with a 200MHz input tone. The analog input of the
MAX105 is designed for differential or single-ended use
with a ±400mV full-scale input range. In addition, the
MAX105 features an on-board +2.5V precision
bandgap reference, which is scaled to meet the analog
input full-scale range.
Principle of OperationThe MAX105 employs a flash or parallel architecture.
The key to this high-speed flash architecture is the use
of an innovative, high-performance comparator design.
Each quantizer and downstream logic translates the
comparator outputs into 6-bit, parallel codes in two’s
complement format and passes them on to the internal
6:12 demultiplexer. The demultiplexer enables the
ADCs to provide their output data at half the sampling
speed on primary and auxiliary ports. LVDS data is
available at speeds of up to 400MHz per output port.
Input Amplifier CircuitsAs with all ADCs, if the input waveform is changing
rapidly during conversion, effective number of bits
(ENOB), signal-to-noise plus distortion (SINAD), and
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
