MAX105ECS+ ,Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX105 is a dual, 6-bit, analog-to-digital converter♦ Two Matched 6-Bit, 800Msps ADCs(A ..
MAX1062ACUB+ ,14-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1062BCUB+ ,14-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with 2.7V to 5.25V digital logic.♦ I ..
MAX1062CCUB ,14-Bit / %V / 200ksps ADC with 10A ShutdownApplicationsMotor ControlTEMP. PIN- INLPARTRANGE PACKAGE (LSB)Industrial Process ControlMAX1062ACUB ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceApplications Ordering InformationTemperature Cable/Harness Tester PIN-PART TEMP RANGE INLSensor/Mon ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceFeaturesThe MAX1065/MAX1066 14-bit, low-power successive♦ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1 ..
MAX338EPE ,8-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX338ESE ,8-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX338ESE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX3390EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPMAX3372E–MAX3379E/MAX3390E–MAX3393E19-2328; Rev 3; 9/03±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad ..
MAX3390EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3391EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPapplications that route sig- MAX3372EEKA-T -40°C to +85°C 8 SOT23-8nals externally. The MAX3372E/MA ..
MAX105ECS+
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
General DescriptionThe MAX105 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of
in-phase (I) and quadrature (Q) baseband signals. The
MAX105 converts the analog signals of both I and Q
components to digital outputs at 800Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 200MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX105 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.4dB signal-to-noise
plus distortion (SINAD) with a 200MHz analog input sig-
nal and a sampling speed of 800MHz. A fully differen-
tial comparator design and encoding circuits reduce
out-of-sequence errors, and ensure excellent
metastable performance of only one error per 1016 clock
cycles.
In addition, the MAX105 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX105 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a lower-speed, 400Msps version of the
MAX105, please refer to the MAX107 data sheet.
ApplicationsVSAT Receivers
WLANs
Test Instrumentation
Communications Systems
FeaturesTwo Matched 6-Bit, 800Msps ADCsExcellent Dynamic Performance
36.4dB SINAD at fIN≈
200MHz and
fCLK≈
800MHz Typical INL and DNL: ±0.25LSB Channel-to-Channel Phase Matching: ±0.2°Channel-to-Channel Gain Matching: ±0.04dB6:12 Demultiplexer reduces the Data Rates to
400MHzLow Error Rate: 1016Metastable States at
800MspsLVDS Digital Outputs in Two’s Complement
Format
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input AmplifierREF
PRIMARY
PORT
AUXILIARY
PORT
PRIMARY
PORT
AUXILIARY
PORT
I ADC
Q ADC
MAX107
Block Diagram19-2006; Rev 0; 5/01
Ordering Information
PARTTEMP. RANGEPIN-PACKAGEMAX105ECS-40°C to +85°C80-Pin TQFP-EP
Pin Configuration appears at end of data sheet.
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V
OVCCI and OVCCQ to OGND...................................-0.3V to +4V
AGND to OGND...................................................-0.3V to +0.3V
P0I±to P5I±and A0I±to A5I±
DREADY+, DREADY- to OGNDI.............-0.3V to OVCCI+0.3V
P0Q±to P5Q±, A0Q±to A5Q±
DOR+ and DOR- to OGNDQ................-0.3V to OVCCQ+0.3V
REF to AGNDR...........................................-0.3V to AVCCR+0.3V
Differential Voltage Between INI+ and INI-....................-2V, +2V
Differential Voltage Between INQ+ and INQ-.................-2V, +2V
Differential Voltage Between CLK+ and CLK-...............-2V, +2V
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W
Operating Temperature Range
MAX105ECS.....................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead temperature (soldering, 10s)..................................+300°C
ELECTRICAL CHARACTERISTICS(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolutionRES6Bits
Integral Nonlinearity (Note 1)INL-1±0.21LSB
Differential Nonlinearity
(Note 1)DNLNo missing codes guaranteed-1±0.251LSB
Offset VoltageVOS(Note 2)-1±0.251LSBffset M atchi ng Betw een AD C sOM(Note 2)-0.5±0.10.5LSB
ANALOG INPUTS (INI+, INI-, INQ+, INQ-)Input Open-Circuit VoltageVAOC2.42.52.6V
Input Open-Circuit Voltage
Matching(VINI+ - VIN-) - (VINQ+ - VINQ-)±7.5mV
Common Mode Input Voltage
Range (Note 3)VCMSignal + Offset w.r.t. AGND1.853.05V
Full-Scale Analog Input
Voltage Range (Note 4)VFSR0.760.80.84Vp-p
Input ResistanceRIN1.72kΩ
Input CapacitanceCIN1.5pF
Input Resistance Temperature
CoefficientTCRIN150ppm/°C
Full-Power Analog Input BWFPBW-0.5dB400MHz
REFERENCE OUTPUTReference Output ResistanceRREFReferenced to AGNDR5Ω
Reference Output Voltage√REFISOURCE = 500μA2.452.502.55V
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CLOCK INPUTS (CLK+, CLK-)Clock Input ResistanceRCLKCLK+ and CLK- to AGND5kΩ
Clock Input Resistance
Temperature CoefficientTCRCLK150ppm/°C
Minimum Clock Input
Amplitude500mVp-p
LVDS OUTPUTS (P0I± TO P5I±, P0Q± TO P5Q±, A0I± TO A5I±, A0Q± TO A5Q±, DREADY+, DREADY-, DOR+, DOR-)Differential Output VoltageVOD 247400mVhang e i n M ag ni tud e of V OD
Betw een “0” and “1” S tatesΔVOD ±25mV
Steady-State Common Mode
Output VoltageVOC(SS)1.1251.375V
Change in Magnitude of VOC
Between “0” and “1” StatesΔVOC ±25mV
Differential Output Resistance80160Ω
Short output together2.5Output CurrentShort to OGNDI = OGNDQ25mA
DYNAMIC SPECIFICATIONDifferential5.45.8fIN = 200.018MHz at
-0.5dB FS (Note 9)Single-ended5.75Effective Number of Bits
(Note 8)ENOB
fIN = 400.134MHz at
-0.5dB FSDifferential5.65
Bits
Differential3537fIN = 200.018MHz at
-0.5dB FS (Note 9)Single-ended36.7Signal-to-Noise Ratio
(Notes 10, 11)SNR
fIN = 400.134MHz at
-0.5dB FSDifferential36.5
Differential-44.5-41fIN = 200.018MHz at
-0.5dB FS (Note 9)Single-ended-44.5Total Harmonic Distortion
(Note 11)THD
fIN = 400.134MHz at
-0.5dB FSDifferential-41
dBc
Differential4145fIN = 200.018MHz at
-0.5dB FS (Note 9)Single-ended45Spurious-Free Dynamic RangeSFDR
fIN = 400.134MHz at
-0.5dB FSDifferential41.5
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential3436.4fIN = 200.018MHz at
-0.5dB FS (Note 9)Single-ended36.1Signal-to-Noise Plus Distortion
RatioSINAD
fIN = 400.134MHz at
-0.5dB FSDifferential35.2
Two-Tone IntermodulationTTIMDfIN1 = 124.1660MHz, fIN2 = 126.1260MHz
at -7dBFS-52dBc
Crosstalk Between ADCsXTLKfINI = 200.0180MHz, fINQ = 210.0140MHz
at -0.5dB FS-70dB
Gain Match Between ADCsGM(Note 12)-0.3±0.04+0.3dB
Phase Match Between ADCsPM(Note 12)-2±0.2+2deg
Metastable Error RateLess than 1 in 1016Clock
Cycles
POWER REQUIREMENTSAnalog Supply VoltageAVCC_AVCC = AVCCI = AVCCQ = AVCCR5 ±5%V
Digital Supply VoltageOVCC_OVCC I = OVCC Q3.3 ±10%V
Analog Supply CurrentICCICC = AICCR + AICCI + AICCQ + AICC250320mA
Output Supply CurrentOICCOICC = OICC I + OICC Q400510mA
Analog Power DissipationPDISS2.6Wom m on- M od e Rej ecti on Rati oCMRRVIN_+ = VIN_- = ±0.1V (Note 6)4060dB
Power-Supply Rejection RatioPSRRAVCC = AVCC I = AVCC Q = AVCC R =
+4.75V to +5.25V (Note 7)4057dB
TIMING CHARACTERISTICSMaximum Sample RatefMAX800Msps
Clock Pulse Width LowtPWL0.56ns
Clock Pulse Width HightPWH0.56ns
Aperture DelaytAD100ps
Aperture JittertAJ1.5psRMS
CLK-to-DREADY Propagation
DelaytPD1(Note 13)1.5ns
DREADY-to-DATA
Propagation DelaytPD2(Notes 5, 13)0120300ps
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
Note 1:NL and DNL is measured using a sine-histogram method.
Note 2:Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3:Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input
voltage level does not matter.
Note 4:The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting
algorithm (e.g. FFT).
Note 5:Guaranteed by design and characterization.
Note 6:Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-
mode voltage expressed in dB.
Note 7:Measured with analog power supplies tied to the same potential.
Note 8:Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9:The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10:Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11:Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12:Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of fIN= 200.0180 MHz.
Note 13:Measured with a differential probe, 1pF capacitance.
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 802.816MHz, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDREADY Duty Cycle(Notes 5, 13)4753%
LVDS Output Rise-TimetRDATA20% to 80% (Notes 5, 13)200500ps
LVDS Output Fall-TimetFDATA20% to 80% (Notes 5, 13)200500ps
Any differential pair<65psLVDS Differential SkewtSKEW1Any tw o LV D S outp ut si g nal s excep t D RE AD Y <100ps
DREADY Rise-TimetRDREADY20% to 80% (Notes 5, 13)200500ps
DREADY Fall-TimetFDREADY20% to 80% (Notes 5, 13)200500ps
Primary Port Pipeline DelaytPDP5Clock
Cycles
Auxiliary Port Pipeline DelaytPDA6Clock
Cycles
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifierypical Operating Characteristics(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
8192-POINT FFT,
DIFFERENTIAL INPUT
MAX105 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB FS)
fIN = 125.146MHz
AIN = -0.5dB FS
8192-POINT FFT,
DIFFERENTIAL INPUT
MAX105 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB FS)
fIN = 124.999MHz
AIN = -0.5dB FS
8192-POINT FFT,
DIFFERENTIAL INPUT
MAX105 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB FS)
fIN = 400.124MHz
AIN = -0.5dB FS
TWO-TONE IMD (8192-POINT RECORD),
DIFFERENTIAL INPUT
MAX105 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB FS)
fN1 = 124.166MHz
fIN2 = 126.126MHz
AIN = -7dB FS
fIN1
fIN2
10M1G10G
SINAD vs. ANALOG INPUT FREQUENCY,
DIFFERENTIAL INPUTMAX105 toc06
ANALOG INPUT FREQUENCY (Hz)
AMPLITUDE (dB)
100M
-12dB FS
-6dB FS
-1dB FS
10M1G10G
THD vs. ANALOG INPUT FREQUENCY,
DIFFERENTIAL INPUTMAX105 toc07
ANALOG INPUT FREQUENCY (Hz)
AMPLITUDE (dB)
100M
-12dB FS
-1dB FS
-6dB FS
10M10G1G100M
SFDR vs. ANALOG INPUT FREQUENCY,
DIFFERENTIAL INPUTMAX105 toc08
ANALOG INPUT FREQUENCY (Hz)
AMPLITUDE (dB)
-12dB FS
-1dB FS
-6dB FS
10M10G1G100M
FULL-POWER INPUT BANDWIDTH
SINGLE-ENDED INPUTMAX105 toc09
ANALOG INPUT FREQUENCY (Hz)
GAIN (dB)
10M1G10G
SNR vs. ANALOG INPUT FREQUENCY,
DIFFERENTIAL INPUTMAX105 toc05
ANALOG INPUT FREQUENCY (Hz)
AMPLITUDE (dB)
100M
-1dB FS
-6dB FS
-12dB FS
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input AmplifierTHD vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc12
ANALOG INPUT POWER (dB FS)
THD (dB)
fIN = 199.8535MHz
SNR vs. TEMPERATURE
MAX105 toc14
TEMPERATURE (°C)
SNR (dB)
fIN = 199.8535MHz
SNR vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc10
ANALOG INPUT POWER (dB FS)
SNR (dB)IN = 199.8535MHz
SINAD vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc11
ANALOG INPUT POWER (dB FS)
SINAD (dB)
fIN = 199.8535MHz
SFDR vs. ANALOG INPUT POWER,
DIFFERENTIAL INPUT
MAX105 toc13
ANALOG INPUT POWER (dB FS)
SFDR (dB)
fIN = 199.8535MHz
SINAD vs. TEMPERATURE
MAX105 toc15
TEMPERATURE (°C)
SINAD (dB)
fIN = 199.8535MHz
THD vs. TEMPERATURE
MAX toc16
TEMPERATURE (°C)
THD (dB)
fIN = 199.8535MHz
SFDR vs. TEMPERATURE
MAX105 toc17
TEMPERATURE (°C)
SFDR (dB)
fIN = 199.8535MHz
SNR vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc18
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 202.346MHz
Typical Operating Characteristics (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input AmplifierSINAD vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc19
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 202.346MHz
THD vs. CLOCK FREQUENCY,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc20
CLOCK FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 202.346MHz
ENOB vs. ANALOG SUPPLY VOLTAGE,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc21
ANALOG SUPPLY VOLTAGE (V)
ENOB (Bits)
fIN = 202.0761MHz
SFDR vs. ANALOG SUPPLY VOLTAGE,
DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc22
ANALOG SUPPLY VOLTAGE (V)
SFDR (dB)
fIN = 202.0761MHz
INL vs. DIGITAL OUTPUT CODE
MAX105 toc23
DIGITAL OUTPUT CODE
INL (LSB)
DNL vs. DIGITAL OUTPUT CODE
MAX105 toc24
DIGITAL OUTPUT CODE
DNL (LSB)
REFERENCE VOLTAGE vs. ANALOG
SUPPLY VOLTAGE
MAX toc25
ANALOG SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
ANALOG SUPPLY CURRENT vs.
ANALOG SUPPLY VOLTAGE
MAX105 toc26
ANALOG SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
MAX105 toc27
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
Typical Operating Characteristics (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0,
fCLK= 802.816MHz, differential input at -0.5dB FS, CL= 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA=
TMINto TMAX, unless otherwise noted.Typical values are at TA= +25°C)
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
PINNAMEFUNCTION1, 20T.P.Test Point. Do not connect.REFReference Output
3AVCCRAnalog Reference Supply. Supply voltage for the internal bandgap reference. Bypass to AGNDR
with 0.01µF in parallel with 47pF for proper operation.AGNDRReference, Analog Ground. Connect to AGND for proper operation.
5, 8AGNDII-Channel, Analog Ground. Connect to AGND for proper operation.INI-I-Channel, Differential Input. Negative terminal.INI+I Channel, Differential Input. Positive terminal.
9AVCCII-Channel, Analog Supply. Supplies I-channel common-mode buffer, pre-amplifier and quantizer.
Bypass to AGNDI with 0.01µF in parallel with 47pF for proper operation.CLK+Sampling Clock InputCLK-Complementary Sampling Clock InputAVCCQQ-Channel, Analog Supply. Supplies Q-channel common-mode buffer, pre-amplifier and quantizer.
Bypass to AGNDQ with 0.01µF in parallel with 47pF for proper operation.
13, 16AGNDQQ-Channel, Analog Ground. Connect to AGND for proper operation.INQ+Q-Channel, Differential Input. Positive terminal.INQ-Q-Channel, Differential Input. Negative terminal.
17, 18AGNDAnalog GroundAVCCAnalog Supply. Bypass to AGND with 0.01µF in parallel with 47pF for proper operation.A5Q+Auxiliary Output Data Bit 5 (MSB), Q-ChannelA5Q-Complementary Auxiliary Output Data Bit 5 (MSB), Q-ChannelP5Q+Primary Output Data Bit 5 (MSB), Q-ChannelP5Q-Complementary Primary Output Data Bit 5 (MSB), Q-ChannelA4Q+Auxiliary Output Data Bit 4, Q-ChannelA4Q-Complementary Auxiliary Output Data Bit 4, Q-ChannelP4Q+Primary Output Data Bit 4, Q-ChannelP4Q-Complementary Primary Output Data Bit 4, Q-Channel
29, 35OVCCQQ-Channel Outputs, Digital Supply. Supplies Q-channel output drivers and DOR logic. Bypass to
OGND with 0.01µF in parallel with 47pF for proper operation.
30, 36OGNDQQ-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board
for proper operation.
Pin Description
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
PINNAMEFUNCTIONA3Q+Auxiliary Output Data Bit 3, Q-ChannelA3Q-Complementary Auxiliary Output Data Bit 3, Q-ChannelP3Q+Primary Output Data Bit 3, Q-ChannelP3Q-Complementary Primary Output Data Bit 3, Q-ChannelA2Q+Auxiliary Output Data Bit 2, Q-ChannelA2Q-Complementary Auxiliary Output Data Bit 2, Q-ChannelP2Q+Primary Output Data Bit 2, Q-ChannelP2Q-Complementary Primary Output Data Bit 2, Q-ChannelA1Q+Auxiliary Output Data Bit 1, Q-ChannelA1Q-Complementary Auxiliary Output Data Bit 1, Q-ChannelP1Q+Primary Output Data Bit 1, Q-ChannelP1Q-Complementary Primary Output Data Bit 1, Q-ChannelA0Q+Auxiliary Output Data Bit 0 (LSB), Q-ChannelA0Q-Complementary Auxiliary Output Data Bit 0 (LSB), Q-ChannelP0Q+Primary Output Data Bit 0 (LSB), Q-ChannelP0Q-Complementary Primary Output Data Bit 0 (LSB), Q-ChannelDOR+Complementary LVDS Out-Of-Range BitDOR-LVDS Out-of-Range BitDREADY-Complementary Data-Ready ClockDREADY+Data Ready ClockP0I-Complementary Primary Output Data Bit 0 (LSB), I-ChannelP0I+Primary Output Data Bit 0 (LSB), I-ChannelA0I-Complementary Auxiliary Output Data Bit 0 (LSB), I-ChannelA0I+Auxiliary Output Data Bit 0 (LSB), I-ChannelP1I-Complementary Primary Output Data Bit 1, I-ChannelP1I+Primary Output Data Bit 1, I-ChannelA1I-Complementary Auxiliary Output Data Bit 1, I-ChannelA1I+Auxiliary Output Data Bit 1, I-ChannelP2I-Complementary Primary Output Data Bit 2, I-Channel
Pin Description (continued)
Detailed DescriptionThe MAX105 is a dual, +5V, 6-bit, 800Msps flash ana-
log-to-digital converter (ADC), designed for high-
speed, high-bandwidth I&Q digitizing. Each ADC
(Figure 1) employs a fully differential, wide bandwidth
input stage, 6-bit quantizers and a unique encoding
scheme to limit metastable states to typically one error
per 1016 clock cycles, with no error exceeding a maxi-
mum of 1LSB. An integrated 6:12 output demultiplexer
simplifies interfacing to the part by reducing the output
data rate to one-half the sampling clock rate. The
MAX105 outputs data in LVDS two’s complement for-
mat.
When clocked at 800Msps, the MAX105 provides a typ-
ical signal-to-noise plus distortion (SINAD) of 36.4dB
with a 200MHz input tone. The analog input of the
MAX105 is designed for differential or single-ended use
with a ±400mV full-scale input range. In addition, the
MAX105 features an on-board +2.5V precision
bandgap reference, which is scaled to meet the analog
input full-scale range.
Principle of OperationThe MAX105 employs a flash or parallel architecture.
The key to this high-speed flash architecture is the use
of an innovative, high-performance comparator design.
Each quantizer and downstream logic translates the
comparator outputs into 6-bit, parallel codes in two’s
complement format and passes them on to the internal
6:12 demultiplexer. The demultiplexer enables the
ADCs to provide their output data at half the sampling
speed on primary and auxiliary ports. LVDS data is
available at speeds of up to 400MHz per output port.
Input Amplifier CircuitsAs with all ADCs, if the input waveform is changing
rapidly during conversion, effective number of bits
(ENOB), signal-to-noise plus distortion (SINAD), and
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
PINNAMEFUNCTIONP2I+Primary Output Data Bit 2, I-ChannelA2I-Complementary Auxiliary Output Data Bit 2, I-ChannelA2I+Auxiliary Output Data Bit 2, I-Channel
65, 72OVCCII-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to
OGND with 0.01µF in parallel with 47pF for proper operation.
66, 71OGNDII-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board
for proper operation.P3I-Complementary Primary Output Data Bit 3, I-ChannelP3I+Primary Output Data Bit 3, I-ChannelA3I-Complementary Auxiliary Output Data Bit 3, I-ChannelA3I+Auxiliary Output Data Bit 3, I-ChannelP4I-Complementary Primary Output Data Bit 4, I-ChannelP4I+Primary Output Data Bit 4, I-ChannelA4I-Complementary Auxiliary Output Data Bit 4, I-ChannelA4I+Auxiliary Output Data Bit 4, I-ChannelP5I-Complementary Primary Output Data Bit 5, I-ChannelP5I+Primary Output Data Bit 5, I-ChannelA5I-Complementary Auxiliary Output Data Bit 5, I-ChannelA5I+Auxiliary Output Data Bit 5, I-Channel
Pin Description (continued)
