MAX1005 ,IF UndersamplerELECTRICAL CHARACTERISTICS(VCCA = VCCD = 3.0V, f = 15MHz, R = ¥ , T = T to T , unless otherwise not ..
MAX1005CEE ,IF UndersamplerApplicationsRXEN 14 D13PWT1900AIO+ 4 MAX1005 13 D2PHS/PAIO- 5 12 D3Wireless LoopsTXEN 6 11 D4PCS/N ..
MAX1005EEE ,IF UndersamplerELECTRICAL CHARACTERISTICS(VCCA = VCCD = 3.0V, f = 15MHz, R = ¥ , T = T to T , unless otherwise not ..
MAX1011CEG ,Low-Power / 90Msps / 6-Bit ADCApplications Ordering InformationIF Sampling ReceiversPART TEMP. RANGE PIN-PACKAGEVSAT ReceiversMAX ..
MAX1020BETX+ ,10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeaturesThe MAX1020/MAX1022/MAX1057/MAX1058 integrate a ♦ 10-Bit, 225ksps ADCAnalog Multiplexer wit ..
MAX1022BETX ,10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO PortsApplicationsControls for Optical ComponentsSPI and QSPI are trademarks of Motorola, Inc.Base-Statio ..
MAX337CAI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, GND = 0V, V = +2.4V, V = +0.8V, T = ..
MAX337CAI+ ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersApplicationsOrdering Information appears at end of data sheet.● Precision Data Acquisition● Precisi ..
MAX337CAI+T ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersApplicationsOrdering Information appears at end of data sheet.● Precision Data Acquisition● Precisi ..
MAX337CPI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersApplicationsMAX336CAI 0°C to +70°C 28 SSOPMAX336C/D 0°C to +70°C Dice*Precision Data AcquisitionOrd ..
MAX337CUI ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersMAX336/MAX337 16-Channel/Dual 8-Channel,Low-Leakage, CMOS Analog Multiplexers
MAX337CWI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersMAX336/MAX33719-1193; Rev 0; 4/9716-Channel/Dual 8-Channel,Low-Leakage, CMOS Analog Multiplexers___ ..
MAX1005
IF Undersampler
_______________General DescriptionThe MAX1005 is a combined digitizer and reconstruc-
tion integrated circuit designed to work in systems that
demodulate and modulate communications signals. It
integrates IF undersampling and signal synthesis func-
tions into a single, low-power circuit. Its analog-to-
digital converter (ADC) is used to directly sample or
undersample a downconverted RF signal, while its
digital-to-analog converter (DAC) recreates the IF sub-
carrier and transmission data. The MAX1005’s ADC is
ideal for undersampling applications, due to the analog
input amplifier’s wide (15MHz) bandwidth. The DAC
has very low glitch energy, which minimizes the trans-
mission of unwanted spurious signals. An on-chip
reference provides for low-noise ADC and DAC conver-
sions.
The MAX1005 provides a high level of signal integrity
from a low power budget. It operates from a single
power supply, or from separate analog and digital sup-
plies with independent voltages ranging from +2.7V to
+5.5V. The MAX1005 can operate with an unregulated
analog supply of 5.5V and a regulated digital supply
down to 2.7V. This flexible power-supply operation
saves additional power in complex digital systems.
The MAX1005 has three operating modes: transmit
(DAC active), receive (ADC active), and shutdown
(ADC and DAC inactive). In shutdown mode, the total
supply current drops below 1μA. The device requires
only 2.4μs to wake up from shutdown mode. The
MAX1005 is ideal for hand-held, as well as base-station
applications. It is available in a tiny 16-pin QSOP pack-
age specified for operation over both the commercial
and extended temperature ranges.
________________________ApplicationsPWT1900
PHS/P
Wireless Loops
PCS/N
____________________________FeaturesDifferential-Input, 5-Bit ADCDifferential-Output, 7-Bit DAC15Msps Min Conversion Rate25MHz -1dB Full-Power Bandwidth44dB SFDR for ADC
39dB at 10.7MHz SFDR (Imaged) for DACInternal Voltage ReferenceParallel Logic InterfaceSingle-Supply Operation (+2.7V to +5.5V)0.1μA Low-Power Shutdown ModeF UndersamplerVCCDCLK
TOP VIEW
MAX1005
QSOPDGND
RXEN
TXEN
AIO+
AIO-
AGND
VCCA
__________________Pin Configuration19-1291; Rev 0; 9/97
PARTMAX1005CEE
MAX1005EEE-40°C to +85°C
0°C to +70°C
TEMP. RANGEPIN-PACKAGE16 QSOP
16 QSOP
______________Ordering Information
Functional Diagram appears at end of data sheet.
F UndersamplerABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCCA = VCCD = 3.0V, fCLK= 15MHz, RL= ¥, TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCA to AGND........................................................-0.3V, +6.0V
VCCD to DGND........................................................-0.3V, +6.0V
VCCA to VCCD...................................................................±6.3V
Digital I/O Pins (D0–D6, CLK, RXEN, TXEN)
to DGND.................................-0.3V to (VCCD + 0.3V) or 6.0V
(whichever is smaller)Analog I/O Pins (AIO+, AIO-)
to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V)
AGND to DGND........................................................-0.3V, +0.3V
Power Dissipation (TA= +70°C)
QSOP (derate 5.90mW/°C above 70°C)......................470mW
Operating Temperature Ranges
MAX1005CEE.....................................................0°C to +70°C
MAX1005EEE...................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
(Notes 9, 10)
AIO+ = AIO-
(Note 4)
(Notes 6, 7)
(Note 3)
(Note 5)
CONDITIONS-42dB-42-24THDTotal Harmonic Distortion368400432VINFull-Scale Input Range
LSB±2Offset Error
LSB±0.2DNLDifferential Nonlinearity
LSB±0.2INLIntegral Nonlinearity
Bits5NResolution67PSRPower-Supply Rejection
CLK
period0.5DAC Latency
dBc-50Clock Feedthrough 0.72.4tWAKEWakeup Time Exiting Shutdown
LSB±0.2±1INLIntegral Nonlinearity
Bits7NResolution
-28dBcTHD+NTotal Harmonic Distortion plus
NoisedBc2839SFDRSpurious-Free Dynamic Range
LSB±0.2±1DNLDifferential Nonlinearity
LSB±1Offset Error
mVp-p736800864VOUTTransmit Full-Scale Output Voltage
UNITSMINTYPMAXSYMBOLPARAMETERVCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 3.0V
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
(Note 9)
(Note 9)
4.9Bits4.54.9ENOBEffective Number of BitsdB2444SFDRSpurious-Free Dynamic Range
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
TRANSMIT DAC DC ACCURACY(Note 1)
TRANSMIT DAC DYNAMIC PERFORMANCE(TA= +25°C) (Note 2)
TRANSMIT ADC DC ACCURACY(Note 8)
RECEIVE ADC DYNAMIC PERFORMANCE(TA= +25°C) (Note 8)
F UndersampleELECTRICAL CHARACTERISTICS (continued)(VCCA = VCCD = 3.0V, fCLK= 15MHz, RL= ¥, TA= TMINto TMAX, unless otherwise noted.)
VCCD = 2.7V
to 5.5V
VCCD = 2.7V
to 5.5V
D0–D4, VCCD = 2.7V to 5.5V, ISINK= 50μA
D0–D4, VCCD = 2.7V to 5.5V,
ISOURCE= 200μA
VCCA = VCCD = 3.0V, CL≤12.5pF,
RXEN = TXEN
VCCA = VCCD
= 3.0V, ≤12.5pF
AIO+ or AIO- to GND
Differential between AIO+ and AIO-
VCCA = VCCD
= 3.0V, ≤12.5pF
CONDITIONS-0.10.5V0.3VCCDVILInput Low Voltage
VCCD - VCCD +
0.7VCCD
VIHInput High Voltage00.5VOLOutput Low VoltageVCCD - 1.0VCCDVOHOutput High Voltage<0.15ICCA +
ICDShutdown Supply Current
ICCDDigital Supply Current
ICCAAnalog Supply Current0.62.4tWAKEWakeup Time Exiting Shutdown
Mode
Msps15
MHz1525Input Full-Power Bandwidth
(-1dB)
Conversion Rate2.75.5VCCA,
VCCDSupply Voltage4CINInput Capacitance (Note 6)
LSB<0.1PSRPower-Supply Rejection1.562.002.44RINInput Resistance
ppm/°C-2000TCRINInput Resistance Temperature
Coefficient
UNITSMINTYPMAXSYMBOLPARAMETERRXEN, TXEN
D0–D6, CLK
RXEN, TXEN
D0–D6, CLK
VIN= 90% of full scale
RXEN = 0, TXEN = 1,
ADC off, DAC on
RXEN = 1, TXEN = 0,
ADC on, DAC off
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz= +25°C, differential between AIO+ and
AIO-
RXEN = 0, TXEN = 1,
ADC off, DAC on
RXEN = 1, TXEN = 0,
ADC on, DAC off
DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK)(Note 12)
POWER REQUIREMENTS
ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11)
CONDITIONSF Undersampler
ELECTRICAL CHARACTERISTICS (continued)(VCCA = VCCD = 3.0V, fCLK= 15MHz, RL= ¥, TA= TMINto TMAX, unless otherwise noted.)
RXEN, TXEN;
VCCD = 2.7V
to 3.6V
D0–D6, CLK; VCCD = 2.7V to 5.5V≤12.5pF = +25°C (Note 6)= +25°C (Note 6)
RXEN, TXEN;
VCCD = 3.6V
to 5.5V
D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)
CONDITIONS7
IINInput Current1320tDOADC CLK to Output Data Valid4555CLK Duty Cycle50.3tHOLDDAC Data Hold Time50.6tDSDAC Data Setup Time8CINInput Capacitance
UNITSMINTYPMAXSYMBOLPARAMETERTXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
TXEN = RXEN
TXEN = RXEN
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
Note 1:TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-
Point Linearity method.
Note 2:fIN= 4.3MHz digital sine wave applied to DAC data inputs; fCLK= 15MHz. The reference frequency (fREF) is defined to be
10.7MHz (fCLK- fIN). All frequency components present in the DAC output waveform except for fREFand fINare consid-
ered spurious.
Note 3:For DAC SFDR measurements, the amplitude of fREF(10.7MHz) is compared to the amplitudes of all frequency compo-
nents of the output waveform except for fIN(4.3MHz).
Note 4:For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of
all harmonic and noise components of the output waveform (except for fINand fREF) to the RMS amplitude of the fREFcom-
ponent.
Note 5:Clock feedthrough is defined as the difference in amplitude between the fREFcomponent and the fCLKcomponent when
measured differentially from AIO+ to AIO-.
Note 6:Guaranteed by design. Not production tested.
Note 7:The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to
propagate through to the DAC switches.
Note 8:RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-
entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.
Note 9:fIN= 10.7MHz, fCLK= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (fREF) is defined to be 4.3MHz
(fCLK- fIN). All components except for fREFand fINare considered spurious.
Note 10:Receive ADC THD measurements include the first five harmonics.
Note 11:CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause
latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are
required, then bypass these pins only to VCCA.
Note 12:All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are
measured to VOH(AC)for rising output signals and to VOL(AC)for falling output signals. The values for VOH(AC)and VOL(AC)
as a function of the VCCD supply are shown in the following table:
VCCD (V)VOH(AC)(V)VOL(AC)(V)2.7 to 3.3VCCD - 1.10.5
3.3 to 5.52/3 x VCCD0.5
TIMING CHARACTERISTICS (Data Outputs: RL= 1MΩ, CL= 15pF, TA= TMINto TMAX, unless otherwise noted.) (Note 12)
F UndersampleRECEIVE ADC
INTEGRAL NONLINEARITY
AX1005-01
CODE
(L
RECEIVE ADC
DIFFERENTIAL NONLINEARITY
AX1005-02
CODE
(L
TRANSMIT DAC
INTEGRAL NONLINEARITY
AX1005-03
CODE
(L
TRANSMIT DAC
DIFFERENTIAL NONLINEARITY
AX1005-04
CODE
(L
RECEIVE ADC FFT PLOT
AX1005-05
FREQUENCY (MHz)
(d
fIN = 10.7MHz
fCLK = 15MHz
256 POINTS10100
FULL POWER ANALOG
INPUT BANDWIDTHAX1005-06
ANALOG INPUT FREQUENCY (MHz)
(d
VIN = 90% OF FULL SCALE
__________________________________________Typical Operating Characteristics(VCCA = VCCD = 3.0V, TA = +25°C, unless otherwise noted.)
_______________Detailed DescriptionThe MAX1005 is designed to operate with the Maxim
PWT1900 (TAG-6) wireless transceiver chipset consisting
of the MAX2411 RF transceiver, the MAX2511 IF trans-
ceiver, and the MAX1007 power-control/diversity IC. The
MAX1005 integrates all the functions of an IF undersam-
pler into a single low-power integrated circuit. It is also
well suited for other time-division duplex (TDD) communi-
cations systems. This device includes a 7-bit transmit
DAC, a 5-bit receive ADC, two internal bandgap refer-
ences, clock drivers, and all necessary interface and
control logic.
Transmit DACThe low-side alias frequency (fCLK - fOUT= 10.7MHz)
generated by the MAX1005’s 7-bit DAC is used to recre-
ate the IF sub-carrier and transmission data in TDD and
other communications systems. The DAC accepts CMOS
input data in the twos-complement format and outputs a
corresponding analog voltage differentially between
AIO+ and AIO-. The full-scale output voltage range is typ-
ically ±400mV. The DAC code table is shown in Table 1.
Table 1. Transmit DAC Code Table
Receive ADCThe 5-bit receive ADC is used to directly sample or
undersample a downconverted RF signal. The ADC
converts an analog input signal to a 5-bit digital output
code in the twos-complement format. Figure 1 shows
the ADC transfer function.
Analog input signals are applied differentially between
AIO+ and AIO-, with a full-scale range of ±200mV. An
internal amplifier buffers the input signal and drives the
comparator array, minimizing loading on the external
signal source. The input amplifier has a full-power -1dB
bandwidth of at least 15MHz, making this device ideally
suited for undersampling applications.
F Undersampler
______________________________________________________________Pin DescriptionTwo MSBs for DAC input data. D6 is the MSB.D6, D59, 10
Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4–D0 function as the five lower bits of DAC input
data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4–D0 function as the five data outputs for the
ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0–D4 should
not be externally held high, to prevent excessive input leakage currents.
D4–D011–15
Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling
edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is
active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is
updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down
(TXEN = RXEN).
CLK16
Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin.AIO-5
Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN
enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its low-
power shutdown mode.
TXEN6
Analog Ground. Connect to analog ground plane.AGND7
Analog Supply Voltage, +2.7V to +5.5VVCCA8
Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin.AIO+4
Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables
the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shut-
down mode.
RXEN3
PINDigital Ground. Connect to digital ground plane.DGND2
Digital Supply Voltage, +2.7V to +5.5VVCCD1
FUNCTIONNAME
DAC INPUT DATAANALOG OUTPUT 011 1111+FS
000 00000
100 0000-FS
