MAX1003CAX ,Low-Power / 90Msps / Dual 6-Bit ADCApplicationsDirect Broadcast Satellite (DBS) Receivers ______________Ordering InformationVSAT Recei ..
MAX1005 ,IF UndersamplerELECTRICAL CHARACTERISTICS(VCCA = VCCD = 3.0V, f = 15MHz, R = ¥ , T = T to T , unless otherwise not ..
MAX1005CEE ,IF UndersamplerApplicationsRXEN 14 D13PWT1900AIO+ 4 MAX1005 13 D2PHS/PAIO- 5 12 D3Wireless LoopsTXEN 6 11 D4PCS/N ..
MAX1005EEE ,IF UndersamplerELECTRICAL CHARACTERISTICS(VCCA = VCCD = 3.0V, f = 15MHz, R = ¥ , T = T to T , unless otherwise not ..
MAX1011CEG ,Low-Power / 90Msps / 6-Bit ADCApplications Ordering InformationIF Sampling ReceiversPART TEMP. RANGE PIN-PACKAGEVSAT ReceiversMAX ..
MAX1020BETX+ ,10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeaturesThe MAX1020/MAX1022/MAX1057/MAX1058 integrate a ♦ 10-Bit, 225ksps ADCAnalog Multiplexer wit ..
MAX337CAI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral Description ________
MAX337CAI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, GND = 0V, V = +2.4V, V = +0.8V, T = ..
MAX337CAI+ ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersApplicationsOrdering Information appears at end of data sheet.● Precision Data Acquisition● Precisi ..
MAX337CAI+T ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersApplicationsOrdering Information appears at end of data sheet.● Precision Data Acquisition● Precisi ..
MAX337CPI ,16-Channel/Dual 8-Channel, Low-Leakage, CMOS Analog MultiplexersApplicationsMAX336CAI 0°C to +70°C 28 SSOPMAX336C/D 0°C to +70°C Dice*Precision Data AcquisitionOrd ..
MAX337CUI ,16-Channel Dual 8 Channel, Low Leakage, CMOS Analog MultiplexersMAX336/MAX337 16-Channel/Dual 8-Channel,Low-Leakage, CMOS Analog Multiplexers
MAX1003CAX
Low-Power / 90Msps / Dual 6-Bit ADC
_______________General DescriptionThe MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5°phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
________________________ApplicationsDirect Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
____________________________FeaturesTwo Matched 6-Bit ADCs High Sampling Rate: 90Msps per ADC Low Power Dissipation: 350mWExcellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input±1/4LSB INL and DNL (typ)Internal Bandgap Voltage ReferenceInternal Oscillator with Overdrive Capability55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential InputsUser-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)1/4LSB Channel-to-Channel Offset Matching (typ)0.1dB Gain and 0.5°Phase Matching (typ)Single-Ended or Differential Input DriveFlexible, 3.3V, CMOS-Compatible Digital Outputs
MAX1003, 90Msps, Dual 6-Bit ADC
_________________________________________________________Functional Diagram
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +5V ±5%, VCCO= 3.3V ±300mV, TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND ............................................................-0.3V to 6.5V
VCCOto OGND........................................................-0.3V to 6.5V
GND to OGND ........................................................-0.3V to 0.3V
Digital and Clock Output Pins to OGND...-0.3V to VCCO(10sec)
All Other Pins to GND...............................................-0.3V to VCC
Continuous Power Dissipation (TA= +70°C)
SSOP (derate 11.8mW/°C above +70°C)...................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS(VCC= +5V ±5%, VCCO= 3.3V ±300mV, TA= +25°C, unless otherwise noted.)
Note 1:Best-fit straight-line linearity method.
Note 2:A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3:PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCCsupply voltage,
expressed in decibels.
Note 4:The current in the VCCOsupply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5:Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).
Note 6:tPDand tSKEWare measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLKis measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
__________________________________________Typical Operating Characteristics(VCC= +5V ±5%, VCCO= 3.3V ±300mV, fCLK= 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, TA= +25°C, unless
otherwise noted.)
_______________Detailed Description
Converter OperationThe MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (µPs) with +3.3V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1003 in a typical application.
Programmable Input AmplifiersThe MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
______________________________________________________________Pin Description
MAX1003Single-ended and differential AC-coupled input circuits
are shown in Figures 2 and 3. Each of the amplifier
inputs is internally biased to a 2.35V reference through
a 20kΩresistor, eliminating external DC bias circuits. A
series 0.1µF capacitor is required at each amplifier
input for AC-coupled signals.
When operating with AC-coupled inputs, the input
amplifiers’ DC offset voltage is nulled to within ±1/2LSB
by an on-chip offset-correction amplifier. An external
compensation capacitor is required to set the dominant
pole of the offset-correction amplifier’s frequency
response (Figures 2 and 3). The compensation capaci-
tor will determine the low-frequency corner of the ana-
log input response according to the following formula:= 1 / (0.1 x C)
where C is the value of the compensation capacitor in
µF, and fcis the corner frequency in Hz.
Low-Power, 90Msps, Dual 6-Bit ADCFigure 1. Commercial Satellite Receiver System
