M95320-RMB6TG ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockAbsolute Maximum Ratings . . . . . . . 22DC AND AC PARAMETERS . 23Table 10. Operating Con ..
M95320-WDW6TP ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95320-WMN3 ,64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES . . . . 9Power-up . . . . . 9Power On Reset: VCC Lock-Out Write Protect ..
M95320-WMN3T ,64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95320-WMN3T/B ,64KBIT AND 32KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKBlock Diagram . 112/39M95640, M95320INSTRUCTIONS . . 12Table 4. Instruction Set ..
M95320-WMN3TP ,64Kbit and 32Kbit Serial SPI Bus EEPROM With High Speed ClockBlock Diagram . 112/39M95640, M95320INSTRUCTIONS . . 12Table 4. Instruction Set ..
MAX178ACNG ,Calibrated 12-Bit ADC with T/H and ReferenceELECTRICAL CHARACTERISTICS
(VDD = +15V, Vcc = +5\/, Vss = -5V, REFIN = +5 OV, all specifications ..
MAX178ACNG ,Calibrated 12-Bit ADC with T/H and ReferenceFeatures
. Continuous Transparent Calibration of Offset
and Gain
. True 12-Bit Performance w ..
MAX178ACNG+ ,Calibrated, 12-Bit ADC with Track/Hold and ReferenceELECTRICAL CHARACTERISTICS
(VDD = +15V, Vcc = +5\/, Vss = -5V, REFIN = +5 OV, all specifications ..
MAX178ACNG+ ,Calibrated, 12-Bit ADC with Track/Hold and ReferenceGeneral Description
The MAX178 is a complete, calibrated 12-bit A/D con-
verter (ADC) which inc ..
MAX178ACWG ,Calibrated 12-Bit ADC with T/H and ReferenceELECTRICAL CHARACTERISTICS
(VDD = +15V, Vcc = +5\/, Vss = -5V, REFIN = +5 OV, all specifications ..
MAX178BCNG ,Calibrated 12-Bit ADC with T/H and ReferenceApplications
Digital-Signal Processing
Audio and Telecom Processing
High-Speed Data Acquisitio ..
M95320-RMB6TG-M95320-WMN3TP-M95320-WMN6P-M95640-WDW6T-M95640-WDW6TG-M95640-WDW6TP-M95640-WMN3TP-M95640-WMN6P-M95640-WMN6TP
32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock
1/42May 2005
M95320 M95320-W M95320-R M95320-S
M95640 M95640-W M95640-R M95640-S32Kbit and 64Kbit Serial SPI Bus EEPROMs
With High Speed Clock
FEATURES SUMMARY Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes) Single Supply Voltage: 4.5 to 5.5V for M95320 and M95640 2.5 to 5.5V for M95320-W and M95320-W 1.8 to 5.5V for M95320-R and M95640-R 1.65 to 5.5V for M95320-S and M95640-S 20MHz, 10MHz, 5MHz or 2MHz clock rates 5ms or 10ms Write Time Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 32 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 100000 or 1 million Erase/Write
Cycles (depending on ordering options) More than 40-Year Data Retention
Table 1. Product List
M95640, M95320
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Table 2. How to Identify Previous, Current and New Products by the Process Identification Letter5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. 8 Pin Package Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 4. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 5. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/42
M95640, M95320Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 6. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 8. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 9. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 10.Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Write Status Register (WRSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 12.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 10. Operating Conditions (M95320 and M95640) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 11. Operating Conditions (M95320-W and M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 12. Operating Conditions (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 13. Operating Conditions (M95320-S and M95640-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 14. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 15.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 16. DC Characteristics (M95320 and M95640, Device Grade 6) . . . . . . . . . . . . . . . . . . . . .24
Table 17. DC Characteristics (M95320 and M95640, Device Grade 3) . . . . . . . . . . . . . . . . . . . . .25
Table 18. DC Characteristics (M95320-W and M95640-W, Device Grade 6) . . . . . . . . . . . . . . . . .26
Table 19. DC Characteristics (M95320-W and M95640-W, Device Grade 3) . . . . . . . . . . . . . . . . .27
Table 20. DC Characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 21. DC Characteristics (M95320-S and M95640-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M95640, M95320Table 22. AC Characteristics (M95320 and M95640, Device Grade 6). . . . . . . . . . . . . . . . . . . . . .28
Table 23. AC Characteristics (M95320 and M95640, Device Grade 3). . . . . . . . . . . . . . . . . . . . . .29
Table 24. AC Characteristics (M95320-W and M95640-W, Device Grade 6) . . . . . . . . . . . . . . . . .30
Table 25. AC Characteristics (M95320-W and M95640-W, Device Grade 3) . . . . . . . . . . . . . . . . .31
Table 26. AC Characteristics (M95320-R and M95640-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 27. AC Characteristics (M95320-S and M95640-S, Device Grade 3) . . . . . . . . . . . . . . . . . .33
Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 17.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 19.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .36
Table 28. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . .36
Figure 20.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .37
Table 29. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 21.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .38
Table 30. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . .38
Figure 22.MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Outline . . . . . . . . . . . .39
Table 31. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Mechanical Data . . . .39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Table 32. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5/42
M95640, M95320
SUMMARY DESCRIPTIONThese electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus.
The M95320, M95320-W, M95320-R and
M95320-S are 32Kbit devices organized as 4096
x 8 bits. The M95640, M95640-W, M95640-R and
M95640-S are 64Kbit devices organized as 8192
x 8 bits.
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 3. and Figure 2..
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
The devices are available in three different ver-
sions identified by a specific marking (see Table
2.).
Table 2. How to Identify Previous, Current and New Products by the Process Identification LetterNote:1. For further information, please ask your ST Sales Office for Process Change Notices.
M95640, M95320
SIGNAL DESCRIPTIONDuring all operations, VCC must be held stable and
within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, VIL
or VOL, as specified in Table 16. to Table 20.).
These signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write operations.
7/42
M95640, M95320
CONNECTING TO THE SPI BUSThese devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4. shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
M95640, M95320
SPI ModesThese devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
9/42
M95640, M95320
OPERATING FEATURES
Power-UpWhen the power supply is turned on, VCC rises
from VSS to VCC.
During this time, the Chip Select (S) must be al-
lowed to follow the VCC voltage. It must not be al-
lowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power On Reset: VCC Lock-Out Write ProtectIn order to prevent inadvertent Write operations
during Power-up, each device include a Power On
Reset (POR) circuit. At Power-up, the device will
not respond to any instruction until VCC has
reached the Power On Reset threshold voltage.
This threshold is lower than the VCC min operating
voltage defined in Tables 10, 11, 12 and 13.
Similarly, as soon as VCC drops from the normal
operating voltage, below the Power On Reset
threshold voltage, the device stops responding to
any instruction sent to it.
Prior to selecting and issuing instructions to the
memory, a valid stable VCC voltage must be ap-
plied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion o
the internal write cycle (tW).
Power-downAt Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on VCC.
Active Power and Standby Power ModesWhen Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
consumes ICC, as specified in Table 16. to Table
When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
Power mode, and the device consumption drops
to ICC1.
Hold ConditionThe Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6.).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6. also shows what happens if the rising
and falling edges are not timed to coincide with
Serial Clock (C) being Low.
M95640, M95320
Status RegisterFigure 7. shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 4. Status Register Format
Data Protection and Protocol ControlNon-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms: Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution. All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events: Power-up Write Disable (WRDI) instruction
completion Write Status Register (WRSR) instruction
completion Write (WRITE) instruction completion The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:
b7 b0
Write In Progress Bit
11/42
M95640, M95320 The ‘last bit of the instruction’ can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions). The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Table 5. Write-Protected Block Size
M95640, M95320
MEMORY ORGANIZATIONThe memory is organized as shown in Figure 7..
13/42
M95640, M95320
INSTRUCTIONSEach instruction starts with a single-byte code, as
summarized in Table 6..
If an invalid instruction is sent (one not contained
in Table 6.), the device automatically deselects it-
self.
Table 6. Instruction Set
M95640, M95320
Write Enable (WREN)The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Write Disable (WRDI)One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion.
15/42
M95640, M95320
Read Status Register (RDSR)The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 10..
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 4.) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
M95640, M95320
Write Status Register (WRSR)The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11..
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is tW) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 4..
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
Table 7. Protection ModesNote:1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5..
The protection features of the device are summa-
rized in Table 5..
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W): If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction. If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
17/42
M95640, M95320(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
Table 8. Address Range BitsNote: b15 to b13 are Don’t Care on the 64 Kbit devices.
b15 to b12 are Don’t Care on the 32 Kbit devices.
M95640, M95320
Read from Memory Array (READ)As shown in Figure 12., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
19/42
M95640, M95320
Write to Memory Array (WRITE)As shown in Figure 13., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of Figure 13., this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period tWC (as specified in Ta-
ble 22. to Table 26.), at the end of which the Write
in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14., the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions: if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in) if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
M95640, M95320
21/42
M95640, M95320
POWER-UP AND DELIVERY STATE
Power-up StateAfter Power-up, the device is in the following state: Standby Power mode deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be started). not in the Hold Condition the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
INITIAL DELIVERY STATEThe device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
