M95160-WMN6TP ,16 Kbit SPI bus EEPROM with high-speed clockLogic diagram . . . . 6Figure 2. 8-pin package connections (top view) . 7Figure 3. WLCS ..
M95256 ,256/128 Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95256-MW6 ,256 Kbit (32K x8)serial SPI bus EEPROM with high speed clock, operating = 4.5 V to 5.5 VFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M95256-MW6T ,256Kbit Serial SPI Bus EEPROM With High Speed ClockAbsolute Maximum Ratings . . . . . . . 21DC AND AC PARAMETERS . 22Table 8. Operating Cond ..
M95256-RMW6TP ,256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M95256VMW6 ,256Kbit Serial SPI Bus EEPROM With High Speed ClockM95256M95128256Kbit and 128Kbit Serial SPI Bus EEPROMWith High Speed Clock
MAX1775EEE-T ,Dual-Output Step-Down DC-DC Converter for PDA/Palmtop ComputersApplicationsPART TEMP RANGE PIN-PACKAGEHand-Held ComputersMAX1775EEE -40°C to +85°C 16 QSOPPDAsInte ..
MAX1775EEE-T ,Dual-Output Step-Down DC-DC Converter for PDA/Palmtop ComputersFeaturesThe MAX1775 dual, step-down DC-DC converter gen-♦ Dual, High-Efficiency, Synchronous Rectif ..
MAX1776EUA ,24V, 600mA Internal Switch, 100% Duty Cycle, Step-Down ConverterFeaturesThe MAX1776 high-efficiency step-down converter pro- Fixed 5V or Adjustable Outputvides an ..
MAX1776EUA ,24V, 600mA Internal Switch, 100% Duty Cycle, Step-Down ConverterApplications Ordering InformationNotebook ComputersPART TEMP RANGE PIN-PACKAGEDistributed Power Sys ..
MAX1776EUA ,24V, 600mA Internal Switch, 100% Duty Cycle, Step-Down ConverterELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V = +12V, SHDN = IN, T = 0°C to +85°C, unless other ..
MAX1776EUA+ ,24V, 600mA Internal Switch, 100% Duty Cycle, Step-Down ConverterFeaturesThe MAX1776 high-efficiency step-down converter pro-♦ Fixed 5V or Adjustable Outputvides an ..
M95160-RMN6TP-M95160WMN6TP-M95160-WMN6TP
16-Kbit SPI bus EEPROM with high-speed clock
October 2014 DocID022580 Rev 7 1/48
M95160 M95160-W M95160-R M95160-DF16-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet - production data Features Compatible with the Serial Peripheral Interface
(SPI) bus Memory array 16 Kb (2 Kbytes) of EEPROM Page size: 32 bytes Additional Write lockable Page
(Identification page) Write Byte Write within 5 ms Page Write within 5 ms Write Protect: quarter, half or whole memory
array High-speed clock: 20 MHz Single supply voltage: 2.5 V to 5.5 V for M95160-W 1.8 V to 5.5 V for M95160-R 1.7 V to 5.5 V for M95160-DF Operating temperature range: from -40°C up to
+85°C Enhanced ESD protection More than 4 million Write cycles More than 200-year data retention Packages RoHS compliant and halogen-free
(ECOPACK2®)
Contents M95160 M95160-W M95160-R M95160-DF2/48 DocID022580 Rev 7
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID022580 Rev 7 3/48
M95160 M95160-W M95160-R M95160-DF Contents6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.7 Read Identification Page (available only in M95160-D devices) . . . . . . . 26
6.8 Write Identification Page (available only in M95160-D devices) . . . . . . . 27
6.9 Read Lock Status (available only in M95160-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95160-D devices) . . . . . . . . . . . . . . . . . . . . . 29
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of tables M95160 M95160-W M95160-R M95160-DF
4/48 DocID022580 Rev 7
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Operating conditions (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Operating conditions (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Operating conditions (M95160-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. DC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. DC characteristics (M95160-R or M95160-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . 35
Table 17. AC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18. AC characteristics (M95160-R or M95160-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . 37
Table 19. AC characteristics (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. AC characteristics (M95160-W, device grade 6)
End of life products: these values apply only to M95160-WMN6TP/S
and M95160-WDW6TP/S devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41
Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 42
Table 23. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. M95160-RCS6TP/S WLCSP package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DocID022580 Rev 7 5/48
M95160 M95160-W M95160-R M95160-DF List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with bumps on the underside) . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Serial output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 41
Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 43
Figure 26. M95160-RCS6TP/S WLCSP package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Description M95160 M95160-W M95160-R M95160-DF
6/48 DocID022580 Rev 7
1 Description
The M95160 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 2048 x 8 bits, accessed through the SPI bus.
The M95160-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95160-R can
operate with a supply voltage from 1.8 V to 5.5 V, and the M95160-DF can operate with a
supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
The M95160-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
DocID022580 Rev 7 7/48
M95160 M95160-W M95160-R M95160-DF Description See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
Figure 3. WLCSP connections (top view, marking side, with bumps on the underside)
Memory organization M95160 M95160-W M95160-R M95160-DF DocID022580 Rev 7
2 Memory organization
The memory is organized as shown in the following figure.
DocID022580 Rev 7 9/48
M95160 M95160-W M95160-R M95160-DF Signal description
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care. o start the Hold condition, the device must be selected, with Chip Select (S) driven low.
Signal description M95160 M95160-W M95160-R M95160-DF
10/48 DocID022580 Rev 7
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 V CC supply voltage
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
DocID022580 Rev 7 11/48
M95160 M95160-W M95160-R M95160-DF Connecting to the SPI bus Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the SHCH requirement is met. The typical value of R is 100 kΩ.
Connecting to the SPI bus M95160 M95160-W M95160-R M95160-DF DocID022580 Rev 7
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 6. SPI modes supported
DocID022580 Rev 7 13/48
M95160 M95160-W M95160-R M95160-DF Operating features
5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state: in Standby Power mode, deselected, Status Register values: The Write Enable Latch (WEL) bit is reset to 0. The Write In Progress (WIP) bit is reset to 0. The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 5).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
Operating features M95160 M95160-W M95160-R M95160-DF
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5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be: deselected (Chip Select S should be allowed to follow the voltage applied on VCC), in Standby Power mode (there should not be any internal write cycle in progress).
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. o enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial Data
Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had (a)(b) This resets the internal logic, except the WEL and WIP bits of the Status Register. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
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The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms: Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight. All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only. The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence: The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions). The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Instructions M95160 M95160-W M95160-R M95160-DF
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6 Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically enters
a Wait state until deselected.
For read and write commands to memory array and Identification Page, the address is
defined by two bytes as explained in Table 4.
Table 3. Instruction set Instruction available only for the M95160-D device.
Table 4. Significant bits within the two address bytes (1)(2) A: Significant address bit. x: bit is Don’t Care. Instruction available only for the M95160-D device.
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6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8. Write Enable (WREN) sequence
Instructions M95160 M95160-W M95160-R M95160-DF
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6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion.
Figure 9. Write Disable (WRDI) sequence
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6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle is
in progress. When one of these cycles is in progress, it is recommended to check the Write
In Progress (WIP) bit before sending a new instruction to the device. It is also possible to
read the Status Register continuously, as shown in Figure 10.
Figure 10. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
Instructions M95160 M95160-W M95160-R M95160-DF
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6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5. Status Register format
b7 b0
Write In Progress bit
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6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits: The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2. The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Instructions M95160 M95160-W M95160-R M95160-DF
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The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin: If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction). If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by: either setting the SRWD bit after driving the Write Protect (W) input pin low, or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Table 6. Protection modes As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
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6.5 Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 12. Read from Memory Array (READ) sequence Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Instructions M95160 M95160-W M95160-R M95160-DF
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6.6 Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.
Figure 13. Byte Write (WRITE) sequence Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions: if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before), if a Write cycle is already in progress, if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in), if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
