M95080-MN3TP/S ,Automotive 8 Kbit serial SPI bus EEPROMAbsolute maximum ratings . 26Table 8. Operating conditions (M95080, device grade 3) . 27Ta ..
M95080-MN6 ,16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed ClockBlock Diagram . 11INSTRUCTIONS . . 12Table 5. Instruction Set . 12Write Enabl ..
M95080-MN6 ,16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed ClockLogic Diagram . . 5Figure 3. DIP, SO, TSSOP and MLP Connections (Top View) . . . . . 5Tabl ..
M95080-MN6T ,16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95080-RMN6TP ,8 Kbit SPI bus EEPROM with high-speed clockfeatures . 135.1 Supply voltage (V ) 13CC5.1.1 Operating supply voltage (V ) . . . . ..
M95080-WDW6 ,16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed ClockBlock Diagram . 11INSTRUCTIONS . . 12Table 5. Instruction Set . 12Write Enabl ..
MAX176ACPA+ ,Serial Output, 250ksps, 12-Bit ADC with Track/Hold and ReferenceGeneral Description
The MAX176 is a complete analog-to-digital converter
(ADC) that achieves a ..
MAX176ACWE ,Serial-Output, 250Ksps 12-Bit ADC with T/H and Refernce79-OO?5:hhw " 12/92
MAX176ACWE ,Serial-Output, 250Ksps 12-Bit ADC with T/H and RefernceFeatures
. 12-Bit Resolution and Linearity
. 0.4ps Track/Hold Acquisition Time
. 3.5ps Max ..
MAX176ACWE ,Serial-Output, 250Ksps 12-Bit ADC with T/H and RefernceFeatures
. 12-Bit Resolution and Linearity
. 0.4ps Track/Hold Acquisition Time
. 3.5ps Max ..
MAX176AEPA ,Serial-Output, 250Ksps 12-Bit ADC with T/H and RefernceFeatures
. 12-Bit Resolution and Linearity
. 0.4ps Track/Hold Acquisition Time
. 3.5ps Max ..
MAX176AEWE ,Serial-Output, 250Ksps 12-Bit ADC with T/H and RefernceELECTRICAL CHARACTERISTICS
(VDD = +5V i5%_ Vss = -11 4V to -IS75V, fCLK = 4MHE for MAX176_C/E an ..
M95080-MN3TP/S-M95080-WMN3TP/S
Automotive 8 Kbit serial SPI bus EEPROM
January 2012 Doc ID 022569 Rev 1 1/38
M95080-125Automotive 8-Kbit serial SPI bus EEPROM
Features Compatible with the Serial Peripheral Interface
(SPI) bus Memory array8 Kb (1 Kbyte) of EEPROM Page size: 32 bytes Write Byte Write within 5 ms Page Write within 5 ms Write Protect: quarter, half or whole memory
array High-speed clock: 5 MHz Single supply voltage: 4.5 V to 5.5 V for M95080 2.5 V to 5.5 V for M95080-W Operating temperature range: from -40°C up to
+125°C Enhanced ESD protection More than 1 million Write cycles More than 40-year data retention Packages RoHS compliant and halogen-free
(ECOPACK®)
M95080-125 ContentsDoc ID 022569 Rev 1 2/38
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contents M95080-1253/38 Doc ID 022569 Rev 1
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
M95080-125 List of tables
Doc ID 022569 Rev 1 4/38
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95080, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M95080-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. DC characteristics (M95080, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (M95080-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. AC characteristics (M95080, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. AC characteristics (M95080-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 34
Table 17. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of figures M95080-125
5/38 Doc ID 022569 Rev 1
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
M95080-125 Description
Doc ID 022569 Rev 1 6/38
1 Description
The M95080 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 1024 x 8 bits, accessed through the SPI bus.
The M95080 devices can operate with a supply range from 2.5 V up to 5.5 V, and are
guaranteed over the -40 °C/+125 °C temperature range. They are compliant with the
Automotive standard AEC-Q100 Grade1.
Figure 1. Logic diagram
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1. Signal names
Description M95080-125
7/38 Doc ID 022569 Rev 1
Figure 2. 8-pin package connections (top view) See Section 10: Package mechanical data section for package dimensions, and how to identify pin1.
M95080-125 Memory organization
Doc ID 022569 Rev 1 8/38
2 Memory organization
The memory is organized as shown in the following figure.
Figure 3. Block diagram
Signal description M95080-125
9/38 Doc ID 022569 Rev 1
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care. o start the Hold condition, the device must be selected, with Chip Select (S) driven low.
M95080-125 Signal description
Doc ID 022569 Rev 1 10/38
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 V CC supply voltage
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
Connecting to the SPI bus M95080-125 Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4. Bus master and memory devices on the SPI bus The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..
M95080-125 Connecting to the SPI bus
Doc ID 022569 Rev 1 12/38
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI modes supported
Operating features M95080-125
13/38 Doc ID 022569 Rev 1
5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of nF to 100 nF) close to the VCC/VSS device pins.
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state: in Standby Power mode, deselected, Status Register values: The Write Enable Latch (WEL) bit is reset to 0. The Write In Progress (WIP) bit is reset to 0. The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
M95080-125 Operating features
Doc ID 022569 Rev 1 14/38
5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be: deselected (Chip Select S should be allowed to follow the voltage applied on VCC), in Standby Power mode (there should not be any internal write cycle in progress).
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3 Hold condition This resets the internal logic, except the WEL and WIP bits of the Status Register. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
Operating features M95080-125
15/38 Doc ID 022569 Rev 1
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms: Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight. All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only. The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C). wo points should be noted in the previous sentence: The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions). The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
M95080-125 Instructions
Doc ID 022569 Rev 1 16/38
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7. Write Enable (WREN) sequence
Table 3. Instruction set
Table 4. Address range bits Upper MSBs are Don’t Care.
Instructions M95080-125
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6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
M95080-125 Instructions
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6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure9.
Figure 9. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set 1, the relevant memory area (as defined in Table 5) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
Instructions M95080-125
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6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5. Status Register format
b7 b0
Write In Progress bit
