M95040-MN3TP/S ,Automotive 4 Kbit serial SPI bus EEPROMFeatures■ Compatible with the Serial Peripheral Interface (SPI) bus■ Memory array– 1 Kbit, 2 Kbit o ..
M95040-MN6 ,4KBIT, 2KBIT AND 1KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKAbsolute Maximum Ratings . . . . . . . 20DC AND AC PARAMETERS . 21Table 8. Operating Cond ..
M95040-MN6TP ,4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed ClockBlock Diagram . 11INSTRUCTIONS . . 12Table 5. Instruction Set . 12Write Enabl ..
M95040-WBN6 ,4K serial SPI EEPROM with high speed clockFEATURES . . . . 9Power-up . . . . . 9Power-down . . . 9Active Power and Sta ..
M95040-WDW3TP ,4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95040-WDW6TG ,4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed ClockFEATURES . . . . 9Power-up . . . . . 9Power-down . . . 9Active Power and Sta ..
MAX1760EUB+ ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC ConverterApplicationsU10-2MAX1760HEUB 10 µMAX HighDigital Cordless Phones PCS Phones*EP = Exposed paddle.Wir ..
MAX1760EUB+ ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC ConverterApplicationsU10-2MAX1760HEUB 10 µMAX HighDigital Cordless Phones PCS Phones*EP = Exposed paddle.Wir ..
MAX1760EUB+T ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC ConverterELECTRICAL CHARACTERISTICS(CLK/SEL = FB = PGND = GND, ISET = REF, OUT = POUT, V = 3.6V, T = 0°C to ..
MAX1760EUB-T ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC ConverterELECTRICAL CHARACTERISTICS (continued)(CLK/SEL = FB = PGND = GND, ISET = REF, OUT = POUT, V = 3.6V, ..
MAX1760EUB-T ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC Converterapplications. The♦ Low-Noise, Constant-Frequency Operation (1MHz)MAX1760 is activated by a logic-lo ..
MAX1760EUB-T ,0.8A, Low-Noise, 1MHz, Step-Up DC-DC Converterapplications. They combine low quies-♦ Up to 800mA Outputcent supply current (100µA) with a high 1M ..
M95020-WMN3TP/S-M95040-MN3TP/S
Automotive 1 Kbit serial SPI bus EEPROM
January 2012 Doc ID 022545 Rev 1 1/36
M95040-125
M95020-125 M95010-125Automotive 4-Kbit, 2-Kbit and 1-Kbit SPI bus EEPROM
Features Compatible with the Serial Peripheral Interface
(SPI) bus Memory array 1 Kbit, 2 Kbit or 4 Kbit of EEPROM Page size: 16 bytes Write protection by block: 1/4, 1/2 or whole
memory5 MHz clock frequency Write cycle within 5 ms Operating temperature range: -40 °C to
+125°C Single supply voltage: 4.5 V to 5.5 V for M950x0 2.5 V to 5.5 V for M950x0-W More than 1 million Write cycles More than 40-year data retention Enhanced ESD protection Packages RoHS-compliant and halogen-free
(ECOPACK2®)
Contents M95040-125, M95020-125, M95010-1252/36 Doc ID 022545 Rev 1
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.9.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M95040-125, M95020-125, M95010-125 ContentsDoc ID 022545 Rev 1 3/36
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of tables M95040-125, M95020-125, M95010-125
4/36 Doc ID 022545 Rev 1
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Operating conditions (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. DC characteristics (M950x0, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. DC characteristics (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. AC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. AC characteristics (M950x0-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. SO8N — 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. TSSOP8 — 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 33
Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
M95040-125, M95020-125, M95010-125 List of figures
Doc ID 022545 Rev 1 5/36
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. SO8N — 8-lead plastic small outline 150 mils body width, package outline. . . . . . . . . . . . 32
Figure 19. TSSOP8 — 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . 33
Description M95040-125, M95020-125, M95010-125
6/36 Doc ID 022545 Rev 1
1 Description
The M950x0-125 devices are 1-Kbit, 2-Kbit and 4-Kbit Electrically Erasable PROgrammable
Memories (EEPROM) accessed through the SPI bus, synchronized with a clock running up
to 5 MHz.
The devices can operate with supply voltages ranging from 2.5 V to 5.5V.
The devices are guaranteed over the -40°C/+125°C temperature range and are compliant
with the Automotive standard AEC-Q100 Grade1.
Figure 1. Logic diagram
Figure 2. 8-pin package connections See Section 10: Package mechanical data for package dimensions, and how to identify pin1.
M95040-125, M95020-125, M95010-125 Description
Doc ID 022545 Rev 1 7/36
Table 1. Signal names
Signal description M95040-125, M95020-125, M95010-125
8/36 Doc ID 022545 Rev 1
2 Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals can be held high or low (according to voltages of VIH, VOH,
VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described
next.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care. o start the Hold condition, the device must be selected, with Chip Select (S) driven low.
M95040-125, M95020-125, M95010-125 Signal description
Doc ID 022545 Rev 1 9/36
2.6 Write Protect (W)
This input signal is used to control whether the memory is write protected. When Write
Protect (W) is held low, writes to the memory are disabled, but other operations remain
enabled. Write Protect (W) must either be driven high or low, but must not be left floating.
2.7 V SS ground
VSS is the reference for the VCC supply voltage.
2.8 Supply voltage (V CC)
2.9 Supply voltage (V CC)
2.9.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see operating condition
tables in Section 9: DC and AC parameters). This voltage must remain stable and valid until
the end of the transmission of the instruction and, for a Write instruction, until the completion
of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10
nF to 100 nF) close to the VCC/VSS package pins.
2.9.2 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal reset threshold voltage (this threshold is defined in operating condition
tables in Section 9: DC and AC parameters) as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state: in Standby Power mode deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S)) Status register value: the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. The device must not be accessed until VCC reaches a valid and stable VCC
voltage within the specified [VCC(min), VCC(max)] range defined in operating condition
tables in Section 9: DC and AC parameters.
Signal description M95040-125, M95020-125, M95010-125
10/36 Doc ID 022545 Rev 1
2.9.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure3).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in operating condition tables in Section 9: DC and AC parameters and the rise time
must not vary faster than 1 V/µs.
2.9.4 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in operating condition tables in Section 9: DC and AC
parameters), the device must be: deselected (Chip Select S should be allowed to follow the voltage applied on VCC) in Standby Power mode (there should not be any internal write cycle in progress).
M95040-125, M95020-125, M95010-125 Connecting to the SPI bus 11/36 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.
Figure 3. Bus master and memory devices on the SPI bus The Write Protect (W) and Hold (HOLD) signals should be driven high or low as appropriate.
Connecting to the SPI bus M95040-125, M95020-125, M95010-125 Doc ID 022545 Rev 1
3.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
M95040-125, M95020-125, M95010-125 Operating features
Doc ID 022545 Rev 1 13/36
4 Operating features
4.1 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care. o enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure5).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
Figure 5. Hold condition activation
4.2 Status register
Figure 6 shows the position of the Status register in the control logic of the device. This
register contains a number of control bits and status bits, as shown in Table 4: Status
register format. For a detailed description of the Status register bits, see Section 6.3: Read
Status Register (RDSR).
Operating features M95040-125, M95020-125, M95010-125
14/36 Doc ID 022545 Rev 1
4.3 Data protection and protocol control o help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows: The WEL bit is reset at power-up. Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status register). Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected. Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 2. Write-protected block size
M95040-125, M95020-125, M95010-125 Memory organization
Doc ID 022545 Rev 1 15/36
5 Memory organization
The memory is organized as shown in Figure6.
Instructions M95040-125, M95020-125, M95010-125
16/36 Doc ID 022545 Rev 1
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 7. Write Enable (WREN) sequence
Table 3. Instruction set X = Don’t Care. A8 = 1 for the upper half of the memory array of the M95040-125, and 0 for the lower half, and is Don’t
Care for other devices.
M95040-125, M95020-125, M95010-125 Instructions
Doc ID 022545 Rev 1 17/36
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion Write Protect (W) line being held low.
Figure 8. Write Disable (WRDI) sequence
Instructions M95040-125, M95020-125, M95010-125
18/36 Doc ID 022545 Rev 1
6.3 Read Status Register (RDSR)
One of the major uses of this instruction is to allow the MCU to poll the state of the Write In
Progress (WIP) bit. This is needed because the device will not accept further WRITE or
WRSR instructions when the previous Write cycle is not yet finished.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is first driven low.
The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state
of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle is
terminated by driving Chip Select (S) high.
The Status register may be read at any time, even during a Write cycle (whether it be to the
memory area or to the Status register). All bits of the Status register remain valid, and can
be read using the RDSR instruction. However, during the current Write cycle, the values of
the non-volatile bits (BP0, BP1) become frozen at a constant value. The updated value of
these bits becomes available when a new RDSR instruction is executed, after completion of
the Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write
In Progress (WIP)) are dynamically updated during the ongoing Write cycle.
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status
register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 2: Write-protected block size) becomes
protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
Table 4. Status register format
b7 b0
Write In Progress bit
