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M93S56-WMN6TP
2 Kbit (16-bit wide) MICROWIRE serial access EEPROM with block protection
Features Compatible with MICROWIRE bus serial interface • Memory array − 1 Kbit, 2 Kbit or 4 Kbit of EEPROM − Organized by word (16b) − Page = 4 words • Write − Byte write within 5 ms − Page write within 5 ms − Ready/busy signal during programming • User defined write protected area • High-speed clock: 2 MHz • Single supply voltage: − 2.5 V to 5.5 V • Operating temperature range: • -40 °C up to +85 °C. • Enhanced ESD protection • More than 4 million write cycles • More than 200-year data retention
Packages PDIP8 ECOPACK®1 • TSSOP8 ECOPACK®2 • SO8 ECOPACK®2
Contents Description ........................................................................................ 5 Signal description ............................................................................ 6 2.1 Serial data output (Q) ........................................................................ 6
2.2 Serial data input (D) .......................................................................... 6
2.3 Serial clock (C) .................................................................................. 6
2.4 Chip select (S) ................................................................................... 6
2.5 Protection register (PRE) .................................................................. 6
2.6 Write protect (W) ............................................................................... 6
2.7 VSS ground ........................................................................................ 6
2.8 Supply voltage (VCC) ......................................................................... 6
2.8.1 Operating supply voltage VCC ............................................................. 6
2.8.2 Device reset ........................................................................................ 7
2.8.3 Power-up conditions ........................................................................... 7
2.8.4 Power-down ........................................................................................ 7
Operating features ............................................................................ 8 Clock pulse counter ......................................................................... 9 Instructions ..................................................................................... 10 5.1 Read ............................................................................................... 12
5.2 Write enable and write disable ........................................................ 12
5.3 Write to memory array (WRITE) ...................................................... 13
5.4 Page write ....................................................................................... 14
5.5 Write all ........................................................................................... 15
5.6 Write protection and protect register ............................................... 16
Power-up and delivery states ........................................................ 21 6.1 Power-up state ................................................................................ 21
6.2 Initial delivery state .......................................................................... 21
Maximum ratings ............................................................................ 22 DC and AC parameters .................................................................. 23 Package mechanical data .............................................................. 27
10 Part numbering ............................................................................... 30
11 Revision history .............................................................................. 31 List of tables Table 1: Signal names ................................................................................................................................ 5 Table 2: Instruction set for the M93S46 .................................................................................................... 10 Table 3: Instruction set for the M93S66, M93S56 .................................................................................... 11 Table 4: Absolute maximum ratings ......................................................................................................... 22 Table 5: Operating conditions (M93Sx6-W) ............................................................................................. 23 Table 6: AC test measurement conditions ................................................................................................ 23 Table 7: Capacitance ................................................................................................................................ 23 Table 8: Memory cell data retention ......................................................................................................... 23 Table 9: Cycling performance ................................................................................................................... 24 Table 10: DC Characteristics (M93Sx6-W, device grade 6) ..................................................................... 24 Table 11: AC Characteristics (M93Sx6-W, device grade 6) ..................................................................... 24 Table 12: SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data ............. 27 Table 13: PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package mechanical data 28 Table 14: TSSOP8 - 8-lead thin shrink small outline, package mechanical data ..................................... 29 Table 15: Document revision history ........................................................................................................ 31
List of figures Figure 1: Logic diagram .............................................................................................................................. 5 Figure 2: 8-pin package connections .......................................................................................................... 5 Figure 3: Write sequence with one clock glitch .......................................................................................... 9 Figure 4: READ sequence ........................................................................................................................ 12 Figure 5: WRITE sequence ...................................................................................................................... 13 Figure 6: WEN and WDS sequences ....................................................................................................... 13 Figure 7: PAWRITE sequence .................................................................................................................. 15 Figure 8: WRAL sequence ........................................................................................................................ 15 Figure 9: PREAD sequence ...................................................................................................................... 18 Figure 10: PRWRITE sequence ............................................................................................................... 18 Figure 11: PREN sequence ...................................................................................................................... 19 Figure 12: PRCLEAR sequence ............................................................................................................... 19 Figure 13: PRDS sequence ...................................................................................................................... 20 Figure 14: AC test measurement I/O waveform ....................................................................................... 23 Figure 15: Synchronous timing (start and op-code input) ......................................................................... 25 Figure 16: Synchronous timing (read or write) ......................................................................................... 26 Figure 17: Synchronous timing (read or write) ......................................................................................... 26 Figure 18: SO8N – 8-lead plastic small outline 150 mils body width, package outline ............................ 27 Figure 19: PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline .......................................... 28 Figure 20: TSSOP8 - 8-lead thin shrink small outline, package outline ................................................... 29 Figure 21: Ordering information scheme .................................................................................................. 30
Description The M93S46, M93S56, M93S66 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 64, 128 or 256 words (one word is 16 bits), accessed through the MICROWIRE bus.
The M93S46, M93S56, M93S66 can operate with a supply voltage from 2.5 V to 5.5 V over an ambient temperature range of -40 °C / +85 °C.
Figure 1: Logic diagram
Figure 2: 8-pin package connections 1. See Section 9: "Package mechanical data" for package dimensions, and how to identify pin-1.
Table 1: Signal names Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max).
All of the input and output signals can be held high or low (according to voltages of VIL, VIH, VOL or VOH, as specified in Table 10: "DC Characteristics (M93Sx6-W, device grade 6)". These signals are described next.
2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the rising edge of Serial Clock (C).
2.2 Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3 Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the rising edge of Serial Clock (C).
2.4 Chip select (S) When this input signal is low, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) high selects the device, placing it in the Active Power mode.
2.5 Protection register (PRE) The Protection enable (PRE) signal must be driven High before and during the instructions accessing the Protection Register.
2.6 Write protect (W) This input signal is used to control the memory in write protected mode. When Write Protect (W) is held low, writes to the memory are disabled, but other operations remain enabled. Write Protect (W) must either be driven high or low, but must not be left floating.
2.7 VSS ground VSS is the reference for the VCC supply voltage.
2.8 Supply voltage (VCC)
2.8.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 5: "Operating conditions (M93Sx6-W)"). This voltage must remain stable and valid until the end of the
transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
2.8.2 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage
When VCC passes over the POR threshold, the device is reset and is in the following state: in Standby Power mode • deselected
The device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 5: "Operating conditions (M93Sx6-W)".
2.8.3 Power-up conditions When the power supply is turned on, VCC must rise continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should be driven low. It is therefore recommended to connect the S line to VCC via a suitable pull-down resistor.
2.8.4 Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 5: "Operating conditions (M93Sx6-W)", the device must be: deselected (S driven low) • in Standby Power mode (there should not be any internal write cycle in progress).
Operating features The device is compatible with the MICROWIRE protocol. All instructions, addresses and input data bytes are shifted into the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes high. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the rising edge of the Serial Clock (C) after the read instruction has been clocked into the device.
The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write, Write All and instructions used to set the memory protection. These are summarized in Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56").
A Read Data from Memory (READ) instruction loads the address of the first word to be read into an internal address counter. The data contained at this address is then clocked out serially. The address counter is automatically incremented after the data is output and, if the Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data words. In this way, the memory can be read as a data stream, or continuously as the address counter automatically rolls over to 00h when the highest address is reached.
Writing data is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the Write Protected area.
Up to 4 words may be written with help of the Page Write instruction and the whole memory may also be erased, or written to a predetermined pattern by using the Write All instruction, within the time required by a write cycle (tW).
After the start of the write cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High.
Within the memory, a user defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protection Register, located outside of the memory array.
As a final protection step, data in this user defined area may be permanently protected by programming a One Time Programming bit (OTP bit) which locks the Protection Register content.
Clock pulse counter In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the Bus Master (the micro- controller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 3: "Write sequence with one clock glitch".) and may lead to the writing of erroneous data at an erroneous address.
To combat this problem, the M93Sx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, PAWRITE, WRALL, PRWRITE or PRCLEAR instruction isaborted, and the contents of the memory are not modified.
The number of clock cycles expected for each in- struction, and for each member of the M93Sx6 family, are summarized in Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56". For example, a Write Data to Memory (WRITE) instruction on the M93S56 (or M93S66) expects 27 clock cycles from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
Figure 3: Write sequence with one clock glitch Instructions The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56". Each instruction consists of the following parts, as shown in Figure 4: "READ sequence", Figure 5: "WRITE sequence" and Figure 6: "WEN and WDS sequences": Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. • A start bit, which is the first '1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). • Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). • The address bits of the byte or word that is to be accessed. For the M93S46, the address is made up of 6 bits (see Table 2: "Instruction set for the M93S46"). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3: "Instruction set for the M93S66, M93S56").
The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 11: "AC Characteristics (M93Sx6-W, device grade 6)".
Table 2: Instruction set for the M93S46
Note: (1) X = Don’t Care bit.
Table 3: Instruction set for the M93S66, M93S56 WDS
Notes: (1) Address bit A7 is not decoded by the M93S56.
(2) X = Don’t Care bit.
5.1 Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the internal address counter and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read.
5.2 Write enable and write disable The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6 initializes itself so that write instructions are disabled. After a Write Enable (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.
Figure 4: READ sequence 1. For the meanings of An and Qn, see Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56".
Figure 5: WRITE sequence 1. For the meanings of An and Dn, see Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56".
Figure 6: WEN and WDS sequences 1. For the meanings of Xn, see Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56".
5.3 Write to memory array (WRITE) The Write Data to Memory instruction is composed of the Start bit plus the op-code followed by the address and the 16 data bits to be written.
Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle.
Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.
5.4 Page write A Page Write to Memory (PAWRITE) instruction contains the first address to be written, followed by up to 4 data words. After the receipt of each data word, bits A1-A0 of the internal address counter are incremented, the high order bits remaining unchanged (A7-A2 for M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words addresses the protected area.
Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle. Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.
Figure 7: PAWRITE sequence 1. For the meanings of An and Dn, see Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56".
5.5 Write all The Write All Memory with same data (WRAL) instruction is valid only after the Protection Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All Memory with same data (WRAL) instruction simultaneously writes the whole memory with the same data word given in the instruction.
Figure 8: WRAL sequence 1. For the meanings of Xn and Dn, see Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66, M93S56".
Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, and after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle. Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle.
5.6 Write protection and protect register The Protection Register on the M93Sx6 is used to adjust the amount of memory that is to be write protected. The write protected area extends from the address given in the Protection Register, up to the top address in the M93Sx6 device.
Two flag bits are used to indicate the Protection Register status: Protection Flag: this is used to enable/disable protection of the write-protected area of the M93Sx6 memory • OTP bit: when set, this disables access to the Protection Register, and thus prevents any further modifications to the value in the Protection Register.
The lower-bound memory address is written to the Protection Register using the Protection Register Write (PRWRITE) instruction. It can be read using the Protection Register Read (PRREAD) instruction.
The Protection Register Enable (PREN) instruction must be executed before any PRCLEAR, PRWRITE or PRDS instruction, and with appropriate levels applied to the Protection Enable (PRE) and Write Enable (W) signals.
Write-access to the Protection Register is achieved by executing the following sequence: Execute the Write Enable (WEN) instruction • Execute the Protection Register Enable (PREN) instruction • Execute one PRWRITE, PRCLEAR or PRDS instructions, to set a new boundary address in the Protection Register, to clear the protection address (to all 1s), or permanently to freeze the value held in the Protection Register.
Protection register read The Protection Register Read (PRREAD) instruction outputs, on Serial Data Output (Q), the content of the Protection Register, followed by the Protection Flag bit. The Protection Enable (PRE) signal must be driven High before and during the instruction.
As with the Read Data from Memory (READ) instruction, a dummy 0 bit is output first. Since it is not possible to distinguish between the Protection Register being cleared (all 1s) or having been written with all 1s, the user must check the Protection Flag status (and not the Protection Register content) to ascertain the setting of the memory protection.
Protection register enable The Protection Register Enable (PREN) instruction is used to authorize the use of instructions that modify the Protection Register (PRWRITE, PRCLEAR, PRDS). The
