M93S66-WMN6T ,4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block ProtectionM93S66, M93S56M93S464Kbit, 2Kbit and 1Kbit (16-bit wide)MICROWIRE Serial Access EEPROM with Block P ..
M93S66WMN6TP ,4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block ProtectionFEATURES SUMMARY■ Industry Standard MICROWIRE Bus Figure 1. Packages■ Single Supply Voltage:– 4.5 t ..
M93S66-WMN6TP ,4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block ProtectionFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1SUMMARY DESCRIPTION ..
M93S66-WMN6TP ,4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block ProtectionAbsolute Maximum Ratings . . . . . . . 16DC AND AC PARAMETERS . 17Table 5. Operating Cond ..
M95010 ,4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed ClockM95040M95020, M950104Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROMWith High Speed Clock
M95010-MN3 ,4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed ClockLogic Diagram . . 5Figure 3. DIP, SO and TSSOP Connections . . 5Table 2. Signal Names ..
MAX17480GTL+ ,AMD 2-/3-Output Mobile Serial VID ControllerMAX1748019-4443; Rev 0; 2/09AMD 2-/3-Output Mobile SerialVID Controller
MAX17480GTL+T ,AMD 2-/3-Output Mobile Serial VID ControllerFeaturesThe MAX17480 is a triple-output, step-down, fixed- ♦ Dual-Output Fixed-Frequency Core Suppl ..
MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterApplicationsTFT Active Matrix LCD DisplaysTOP VIEWPassive Matrix LCD DisplaysRDY 1 16 TGNDPDAsFB 2 ..
MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterFeaturesThe MAX1748 triple-output DC-DC converter in a low- Three Integrated DC-DC Convertersprofi ..
MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterELECTRICAL CHARACTERISTICS(V = +3.0V, SHDN = IN, V = V = 10V, TGND = PGND = GND, C = 0.22µF, C = 47 ..
MAX1748EUE+ ,Triple-Output TFT-LCD DC-DC ConvertersELECTRICAL CHARACTERISTICS(V = +3.0V, SHDN = IN, V = V = 10V, TGND = PGND = GND, C = 0.22µF, C = 47 ..
M93S46BN6-M93S46-MN6-M93S46-MN6T-M93S46-WMN6-M93S46-WMN6P-M93S46-WMN6T-M93S46-WMN6TP-M93S56-MN6-M93S56-MN6T-M93S56-WBN6-M93S56WMN6-M93S56-WMN6-M93S56-WMN6T-M93S66-MN6-M93S66-WBN6-M93S66-WMN6-M93S66-WMN6P-M93S66-WMN6T-M93S66WMN6TP-M93S66-WMN6TP
4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection
1/34April 2004
M93S66, M93S56
M93S464Kbit, 2Kbit and 1Kbit (16-bit wide)
MICROWIRE Serial Access EEPROM with Block Protection
FEATURES SUMMARY Industry Standard MICROWIRE Bus Single Supply Voltage: 4.5 to 5.5V for M93Sx6 2.5 to 5.5V for M93Sx6-W 1.8 to 5.5V for M93Sx6-R Single Organization: by Word (x16) Programming Instructions that work on: Word
or Entire Memory Self-timed Programming Cycle with Auto-
Erase User Defined Write Protected Area Page Write Mode (4 words) Ready/Busy Signal During Programming Speed: 1MHz Clock Rate, 10ms Write Time
(Current product, identified by process
identification letter F or M) 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process
identification letter W or G) Sequential Read Operation Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
Figure 1. Packages
M93S66, M93S56, M93S46
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6. Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 8. AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . .17
3/34
M93S66, M93S56, M93S46Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 10.Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .28
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .28
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .29
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .31
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . .31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . .32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
M93S66, M93S56, M93S46
SUMMARY DESCRIPTIONThis specification covers a range of 4K, 2K, 1K bit
serial Electrically Erasable Programmable Memo-
ry (EEPROM) products (respectively for M93S66,
M93S56, M93S46). In this text, these products are
collectively referred to as M93Sx6.
Figure 2. Logic Diagram
Table 1. Signal NamesThe M93Sx6 is accessed through a serial input (D)
and output (Q) using the MICROWIRE bus proto-
col. The memory is divided into 256, 128, 64 x16
bit words (respectively for M93S66, M93S56,
M93S46).
The M93Sx6 is accessed by a set of instructions
which includes Read, Write, Page Write, Write All
and instructions used to set the memory protec-
tion. These are summarized in Table 2. and Table
3.).
A Read Data from Memory (READ) instruction
loads the address of the first word to be read into
an internal address pointer. The data contained at
this address is then clocked out serially. The ad-
dress pointer is automatically incremented after
the data is output and, if the Chip Select Input (S)
is held High, the M93Sx6 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream from 16 to 4096 bits (for
the M93S66), or continuously as the address
counter automatically rolls over to 00h when the
highest address is reached.
Within the time required by a programming cycle
(tW), up to 4 words may be written with help of the
Page Write instruction. the whole memory may
also be erased, or set to a predetermined pattern,
by using the Write All instruction.
Within the memory, a user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a Pro-
tection Register, located outside of the memory ar-
ray. As a final protection step, data may be
permanently protected by programming a One
Time Programming bit (OTP bit) which locks the
Protection Register content.
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an erase cycle prior to the Write
instruction. The Write instruction writes 16 bits at a
time into one of the word locations of the M93Sx6,
the Page Write instruction writes up to 4 words of
16 bits to sequential locations, assuming in both
cases that all addresses are outside the Write Pro-
tected area. After the start of the programming cy-
cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
en High.
Figure 3. DIP, SO and TSSOP ConnectionsNote: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
5/34
M93S66, M93S56, M93S46An internal Power-on Data Protection mechanism
in the M93Sx6 inhibits the device when the supply
is too low.
POWER-ON DATA PROTECTIONTo prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode. At Power-up and Power-down, the device
must not be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltage reaches the operating value VCC
specified in Table 5. to Table 6.. When VCC reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
For the M93Sx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Sx6-
W (3V range) and M93Sx6-R (2V range) the POR
threshold voltage is around 1.5V.
INSTRUCTIONSThe instruction set of the M93Sx6 devices con-
tains seven instructions, as summarized in Table
2. to Table 3.. Each instruction consists of the fol-
lowing parts, as shown in Figure 4.: Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low. A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code). The address bits of the byte or word that is to
be accessed. For the M93S46, the address is
made up of 6 bits (see Table 2.). For the
M93S56 and M93S66, the address is made up
of 8 bits (see Table 3.).
The M93Sx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in Table 16. to Table 19..
M93S66, M93S56, M93S46
Table 2. Instruction Set for the M93S46Note:1. X = Don’t Care bit.
7/34
M93S66, M93S56, M93S46
Table 3. Instruction Set for the M93S66, M93S56Note:1. X = Don’t Care bit. Address bit A7 is not decoded by the M93S56.
M93S66, M93S56, M93S46
Figure 4. READ, WRITE, WEN and WDS SequencesNote: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..
9/34
M93S66, M93S56, M93S46
ReadThe Read Data from Memory (READ) instruction
outputs serial data on Serial Data Output (Q).
When the instruction is received, the op-code and
address are decoded, and the data from the mem-
ory is transferred to an output shift register. A dum-
my 0 bit is output first, followed by the 16-bit word,
with the most significant bit first. Output data
changes are triggered by the rising edge of Serial
Clock (C). The M93Sx6 automatically increments
the internal address register and clocks out the
next byte (or word) as long as the Chip Select In-
put (S) is held High. In this case, the dummy 0 bit
is not output between bytes (or words) and a con-
tinuous stream of data can be read.
Write Enable and Write DisableThe Write Enable (WEN) instruction enables the
future execution of write instructions, and the Write
Disable (WDS) instruction disables it. When power
is first applied, the M93Sx6 initializes itself so that
write instructions are disabled. After an Write En-
able (WEN) instruction has been executed, writing
remains enabled until an Write Disable (WDS) in-
struction is executed, or until VCC falls below the
power-on reset threshold voltage. To protect the
memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) in-
struction after every write cycle. The Read Data
from Memory (READ) instruction is not affected by
the Write Enable (WEN) or Write Disable (WDS)
instructions.
WriteThe Write Data to Memory (WRITE) instruction is
composed of the Start bit plus the op-code fol-
lowed by the address and the 16 data bits to be
written.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (tSLSH) before the status information
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
M93S66, M93S56, M93S46
Figure 5. PAWRITE and WRAL SequenceNote: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
Page WriteA Page Write to Memory (PAWRITE) instruction
contains the first address to be written, followed by
up to 4 data words.
After the receipt of each data word, bits A1-A0 of
the internal address register are incremented, the
high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users
must take care, in the software, to ensure that the
last word address has the same upper order ad-
dress bits as the initial address transmitted to
avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction
will not be executed if any of the 4 words address-
es the protected area.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
11/34
M93S66, M93S56, M93S46be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (tSLSH) before the status information
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
Write AllThe Write All Memory with same Data (WRAL) in-
struction is valid only after the Protection Register
has been cleared by executing a Protection Reg-
ister Clear (PRCLEAR) instruction. The Write All
Memory with same Data (WRAL) instruction simul-
taneously writes the whole memory with the same
data word given in the instruction.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (tSLSH) before the status information
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
M93S66, M93S56, M93S46
Figure 6. PREAD, PRWRITE and PREN SequencesNote: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
13/34
M93S66, M93S56, M93S46
Figure 7. PRCLEAR and PRDS SequencesNote: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
M93S66, M93S56, M93S46
WRITE PROTECTION AND THE PROTECTION REGISTERThe Protection Register on the M93Sx6 is used to
adjust the amount of memory that is to be write
protected. The write protected area extends from
the address given in the Protection Register, up to
the top address in the M93Sx6 device.
Two flag bits are used to indicate the Protection
Register status: Protection Flag: this is used to enable/disable
protection of the write-protected area of the
M93Sx6 memory OTP bit: when set, this disables access to the
Protection Register, and thus prevents any
further modifications to the value in the
Protection Register.
The lower-bound memory address is written to the
Protection Register using the Protection Register
Write (PRWRITE) instruction. It can be read using
the Protection Register Read (PRREAD) instruc-
tion.
The Protection Register Enable (PREN) instruc-
tion must be executed before any PRCLEAR,
PRWRITE or PRDS instruction, and with appropri-
ate levels applied to the Protection Enable (PRE)
and Write Enable (W) signals.
Write-access to the Protection Register is
achieved by executing the following sequence: Execute the Write Enable (WEN) instruction Execute the Protection Register Enable
(PREN) instruction Execute one PRWRITE, PRCLEAR or PRDS
instructions, to set a new boundary address in
the Protection Register, to clear the protection
address (to all 1s), or permanently to freeze
the value held in the Protection Register.
Protection Register ReadThe Protection Register Read (PRREAD) instruc-
tion outputs, on Serial Data Output (Q), the con-
tent of the Protection Register, followed by the
Protection Flag bit. The Protection Enable (PRE)
signal must be driven High before and during the
instruction.
As with the Read Data from Memory (READ) in-
struction, a dummy 0 bit is output first. Since it is
not possible to distinguish between the Protection
Register being cleared (all 1s) or having been writ-
ten with all 1s, the user must check the Protection
Flag status (and not the Protection Register con-
tent) to ascertain the setting of the memory protec-
tion.
Protection Register EnableThe Protection Register Enable (PREN) instruc-
tion is used to authorize the use of instructions that
modify the Protection Register (PRWRITE,
PRCLEAR, PRDS). The Protection Register En-
able (PREN) instruction does not modify the Pro-
tection Flag bit value.
Note: A Write Enable (WEN) instruction must be
executed before the Protection Register Enable
(PREN) instruction. Both the Protection Enable
(PRE) and Write Enable (W) signals must be driv-
en High during the instruction execution.
Protection Register ClearThe Protection Register Clear (PRCLEAR) in-
struction clears the address stored in the Protec-
tion Register to all 1s, so that none of the memory
is write-protected by the Protection Register. How-
ever, it should be noted that all the memory re-
mains protected, in the normal way, using the
Write Enable (WEN) and Write Disable (WDS) in-
structions.
The Protection Register Clear (PRCLEAR) in-
struction clears the Protection Flag to 1. Both the
Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Clear (PRCLEAR) instruction.
Protection Register WriteThe Protection Register Write (PRWRITE) instruc-
tion is used to write an address into the Protection
Register. This is the address of the first word to be
protected. After the Protection Register Write
(PRWRITE) instruction has been executed, all
memory locations equal to and above the speci-
fied address are protected from writing.
The Protection Flag bit is set to 0, and can be read
with Protection Register Read (PRREAD) instruc-
tion. Both the Protection Enable (PRE) and Write
Enable (W) signals must be driven High during the
instruction execution.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Write (PRWRITE) instruction, but it is not
necessary to execute first a Protection Register
Clear (PRCLEAR).
Protection Register DisableThe Protection Register Disable (PRDS) instruc-
tion sets the One Time Programmable (OTP) bit.
This instruction is a ONE TIME ONLY instruction
which latches the Protection Register content, this
content is therefore unalterable in the future. Both
the Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution. The OTP bit cannot be directly read, it
can be checked by reading the content of the Pro-
tection Register, using the Protection Register
Read (PRREAD) instruction, then by writing this
same value back into the Protection Register, us-
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M93S66, M93S56, M93S46ing the Protection Register Write (PRWRITE) in-
struction. When the OTP bit is set, the Ready/Busy
status cannot appear on Serial Data Output (Q).
When the OTP bit is not set, the Busy status ap-
pears on Serial Data Output (Q).
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Disable (PRDS) instruction.
COMMON I/O OPERATIONSerial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
CLOCK PULSE COUNTERIn a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the Bus Master (the micro-
controller). This can lead to a misalignment of the
instruction of one or more bits (as shown in Figure
8.) and may lead to the writing of erroneous data
at an erroneous address.
To combat this problem, the M93Sx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, PAWRITE,
WRALL, PRWRITE or PRCLEAR instruction is
aborted, and the contents of the memory are not
modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Sx6
family, are summarized in Table 2. to Table 3.. For
example, a Write Data to Memory (WRITE) in-
struction on the M93S56 (or M93S66) expects 27
clock cycles from the start bit to the falling edge of
Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
M93S66, M93S56, M93S46
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum RatingsNote:1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
17/34
M93S66, M93S56, M93S46
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M93Sx6)
Table 6. Operating Conditions (M93Sx6-W)
Table 7. Operating Conditions (M93Sx6-R)
Table 8. AC Measurement Conditions (M93Sx6)Note: Output Hi-Z is defined as the point where data out is no longer driven.
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R)Note: Output Hi-Z is defined as the point where data out is no longer driven.
